Datasheet IDT74FCT573SOB, IDT74FCT573CPB, IDT74FCT573CP, IDT74FCT573CLB, IDT74FCT573CEB Datasheet (Integrated Device Technology)



Integrated Device Technology, Inc.

FAST CMOS OCTAL
TRANSPARENT LATCHES

IDT54/74FCT373/A/C
IDT54/74FCT533/A/C
IDT54/74FCT573/A/C

FEATURES

• IDT54/74FCT373/533/573 equivalent to FAST speed
and drive

• IDT54/74FCT373A/533A/573A up to 30% faster than
FAST

• Equivalent to FAST output drive over full temperature
and voltage supply extremes

•I

OL = 48mA (commercial) and 32mA (military)

• CMOS power levels (1mW typ. static)

• Octal transparent latch with 3-state output control

• JEDEC standard pinout for DIP and LCC

• Product available in Radiation Tolerant and Radiation
Enhanced versions

• Military product compliant to MIL-STD-883, Class B

FUNCTIONAL BLOCK DIAGRAMS

IDT54/74FCT373 AND IDT54/74FCT573

D

0

D

G

D

1

D

O

G

D

2

D

O

D

3

D

O

G

DESCRIPTION

The IDT54/74FCT373/A/C, IDT54/74FCT533/A/C and
IDT54/74FCT573/A/C are octal transparent latches built us­ing an advanced dual metal CMOS technology. These octal
latches have 3-state outputs and are intended for bus oriented
applications. The flip-flops appear transparent to the data
when Latch Enable (LE) is HIGH. When LE is LOW, the data
that meets the set-up time is latched. Data appears on the bus
when the Output Enable (OE) is LOW. When OE is HIGH, the

bus output is in the high-impedance state.

D

4

D

O

G

G

D

5

D

O

G

D

6

D

O

G

D

7

D

O

G

O

LE

OE

0

O

1

O

2

O

3

O

4

O

5

O

6

O

7

O

2602 cnv* 01

IDT54/74FCT533

D0

D

G

LE

OE

The IDT logo is a registered trademark of Integrated Device Technology, Inc.
FAST is a trademark of National Semiconductor Co.

D1

D

O

G

0

O

D2

D

O

G

1

O

D3

D

O

G

2

O

D4

D

O

G

3

O

D5

D

O

G

4

O

D6

D

O

G

5

O

D7

D

O

O

G

6

O

7

O

2602 cnv* 02

MILITARY AND COMMERCIAL TEMPERATURE RANGES MAY 1992

1992 Integrated Device Technology, Inc. 7.12 DSC-4624/2

1

IDT54/74FCT373/533/573/A/C
FAST CMOS OCTAL TRANSPARENT LATCHES MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN CONFIGURATIONS

IDT54/74FCT373

IDT54/74FCT573

OE

O0
D0

D1

O1
O2

D2

D3

O3

GND

2
3
4

5
6
7
8
9
10 11

DIP/SOIC/CERPACK

OE

D

0

D

1

D

2

D

3

D

4

D

5

D

6

D

7

GND

DIP/SOIC/CERPACK

20
19
18

P20-1
D20-1

SO20-2

E20-1

17
16

15

&

14
13
12

TOP VIEW

1
2

3
4
5
6
7
8
9

P20-1
D20-1

SO20-2

E20-1

20
19
18
17
16
15

&

14
13
12

10 11

TOP VIEW

VCC1
O
D7
D6
O6
O5
D
D4

O4
LE

INDEX

O0

7

D1
O1
O2

5

D2
D3

D0

3 2 20 19

4

1

5
6

L20-2

7
8

OE

VCC

O7

18

D7
D6

17

O6

16

O5

15
14

D5

9 10111213

4

LE

D4

O

O3

GND

LCC

TOP VIEW

V
O

O
O
O
O

O
O

O
LE

CC

0
1
2
3
4
5
6
7

INDEX

0

1

D

D

3 2 20 19

D
D
D
D
D

4

2

5

3
4

6
7

5

8

6

1

L20-2

9 10111213

7

D

OE

LE

CC

V

7

O

0

O

6

O

18
17

16
15
14

O

1

O

2

O

3

O

4

O

5

GND

LCC

TOP VIEW

IDT54/74FCT533

OE

O

0

2
D0
D1

O1
O2
D2
D3
O3

GND

3

4

5

6

7

8

9

10 11

DIP/SOIC/CERPACK

P20-1
D20-1

SO20-2

&

E20-1

TOP VIEW

20
19
18
17

16
15
14
13
12

VCC1
O
D7
D6

O6
O5
D
D4
O4
LE

INDEX

7

D1 D7
O1

O2

5

D2
D3

4
5
6
7
8

0D0

O

3 2 20 19

1

L20-2

OE

CC

V

7

O

18

D

17
16
15
14

6

O6
O5

D5

9 10111213

4

LE

4

O

D

3

O

GND

LCC

TOP VIEW

7.12 2

2602 cnv* 03–08

IDT54/74FCT373/533/573/A/C
FAST CMOS OCTAL TRANSPARENT LATCHES MILITARY AND COMMERCIAL TEMPERATURE RANGES

FUNCTION TABLE (FCT533)

(1)

FUNCTION TABLE (FCT373 and FCT573)

(1)

Inputs Outputs

DN LE

OE

OE

O

N

O

HHLL

LHLH

XXHZ

NOTE:

1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
Z = High Impedance

2602 tbl 05

PIN DESCRIPTION

Pin Names Description

DN Data Inputs

LE Latch Enable Input (Active HIGH)

OE

ON 3-State Outputs

O

N Complementary 3-State Outputs

ABSOLUTE MAXIMUM RATINGS

Symbol Rating Commercial Military Unit

(2)

VTERM

VTERM

TA Operating

TBIAS Temperature

TSTG Storage

PT Power Dissipation 0.5 0.5 W
IOUT DC Output

NOTES:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability. No terminal voltage
may exceed V

2. Input and V

3. Outputs and I/O terminals only.

Terminal Voltage
with Respect to
GND

(3)

Terminal Voltage
with Respect to
GND

Temperature

Under Bias

Temperature

Current

Output Enable Input (Active LOW)

–0.5 to +7.0 –0.5 to +7.0 V

–0.5 to V

CC –0.5 to VCC V

0 to +70 –55 to +125 °C

–55 to +125 –65 to +135 °C

–55 to +125 –65 to +150 °C

120 120 mA

CC by +0.5V unless otherwise noted.

CC terminals only.

2602 tbl 07

(1)

2602 tbl 01

Inputs Outputs

DN LE

OE

OE

ON

HHLH

LHLL

XXHZ

NOTE:

1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
Z = High Impedance

2602 tbl 06

CAPACITANCE (TA = +25°C, f = 1.0MHz)

Symbol Parameter Conditions Typ. Max. Unit

CIN Input

Capacitance

COUT Output

Capacitance

NOTE: 2602 tbl 02

1. This parameter is measured at characterization but not tested.

VIN = 0V 6 10 pF

VOUT = 0V 8 12 pF

7.12 3

IDT54/74FCT373/533/573/A/C
FAST CMOS OCTAL TRANSPARENT LATCHES MILITARY AND COMMERCIAL TEMPERATURE RANGES

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE

Following Conditions Apply Unless Otherwise Specified: VLC = 0.2V; VHC = VCC – 0.2V
Commercial: T

Symbol Parameter Test Conditions

VIH Input HIGH Level Guaranteed Logic HIGH Level 2.0 — — V
VIL Input LOW Level Guaranteed Logic LOW Level — — 0.8 V
II H Input HIGH Current VCC = Max. VI = VCC —— 5µA

II L Input LOW Current VI = 0.5V — — –5

IOZH Off State (High Impedance) VCC = Max. VO = VCC ——10µA

IOZL VO = 0.5V — — –10

VIK Clamp Diode Voltage VCC = Min., IN = –18mA — –0.7 –1.2 V
IOS Short Circuit Current VCC = Max.
VOH Output HIGH Voltage VCC = 3V, VIN = VLC or VHC, IOH = –32µAVHC VCC —V

VOL Output LOW Voltage VCC = 3V, VIN = VLC or VHC, IOL = 300µA — GND VLC V

NOTES: 2602 tbl 03

1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.

2. Typical values are at V

3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.

4. This parameter is guaranteed but not tested.

A = 0°C to +70°C, VCC = 5.0V ± 5%; Military: TA = –55°C to +125°C, VCC

(1)

= 5.0V ± 10%

Min. Typ.

(2)

VI = 2.7V — — 5

VI = GND — — –5

Output Current VO = 2.7V — — 10

VO = GND — — –10

(3)

, VO = GND –60 –120 — mA

VCC = Min. IOH = –300µAVHC VCC —
VIN = VIH or VIL IOH = –12mA MIL. 2.4 4.3 —

IOH = –15mA COM'L. 2.4 4.3 —

VCC = Min. IOL = 300µA — GND VLC
VIN = VIH or VIL IOL = 32mA MIL. — 0.3 0.5

IOL = 48mA COM'L. — 0.3 0.5

CC = 5.0V, +25°C ambient and maximum loading.

Max. Unit

(4)

(4)

(4)

(4)

(4)

7.12 4

IDT54/74FCT373/533/573/A/C
FAST CMOS OCTAL TRANSPARENT LATCHES MILITARY AND COMMERCIAL TEMPERATURE RANGES

POWER SUPPLY CHARACTERISTICS

VLC = 0.2V; VHC = VCC – 0.2V

Symbol Parameter Test Conditions

ICC

∆ICC
ICCD Dynamic Power Supply

Quiescent Power Supply Current VCC = Max.

V

IN ≥ VHC; V IN ≤ VLC

Quiescent Power Supply Current
TTL Inputs HIGH

VCC = Max.
V

IN = 3.4V

VCC = Max.

(4)

Current

Outputs Open

OE

= GND

(3)

(1)

VIN ≥ VHC
V

IN ≤ VLC

Min. Typ.

— 0.2 1.5 mA

— 0.5 2.0 mA
— 0.15 0.25 mA/

One Input Toggling
50% Duty Cycle

IC Total Power Supply Current

(6)

VCC = Max.
Outputs Open
fi = 10MHz
50% Duty Cycle

OE

= GND

LE

= VCC

VIN ≥ VHC
V

IN ≤ VLC

(FCT)

IN = 3.4V

V
V

IN = GND

— 1.7 4.0 mA

— 2.0 5.0

One Bit Toggling
VCC = Max.
Outputs Open
fi = 2.5MHz
50% Duty Cycle

OE

= GND

LE

= VCC

VIN ≥ VHC
V

IN ≤ VLC

(FCT)

IN = 3.4V

V
V

IN = GND

— 3.2 6.5

— 5.2 14.5

Eight Bits Toggling

NOTES: 2602 tbl 04

1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.

2. Typical values are at V

3. Per TTL driven input (V

4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.

5. Values for these conditions are examples of the I

C = IQUIESCENT + IINPUTS + IDYNAMIC

6. I
IC = ICC + ∆ICC DHNT + ICCD (fCP/2 + fiNi)
I

CC = Quiescent Current

CC = Power Supply Current for a TTL High Input (VIN = 3.4V)

∆I

H = Duty Cycle for TTL Inputs High

D

T = Number of TTL Inputs at DH

N
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
f

CP = Clock Frequency for Register Devices (Zero for Non-Register Devices)
i = Input Frequency

f

i = Number of Inputs at fi

N
All currents are in milliamps and all frequencies are in megahertz.

CC = 5.0V, +25°C ambient.

IN = 3.4V); all other inputs at VCC or GND.

CC formula. These limits are guaranteed but not tested.

(2)

Max. Unit

MHz

(5)

(5)

7.12 5

IDT54/74FCT373/533/573/A/C
FAST CMOS OCTAL TRANSPARENT LATCHES MILITARY AND COMMERCIAL TEMPERATURE RANGES

SWITCHING CHARACTERISTICS OVER OPERATING RANGE FOR FCT373/A/C/FCT573/A/C

FCT373/573 FCT373A/573A FCT373C/573C

Symbol Parameter Conditions

tPLH
tPHL

tPLH
tPHL
tPZH

Propagation Delay

N to ON

D
Propagation Delay

N

LE to O
Output Enable Time

CL = 50pF

R

L = 500Ω

tPZL
tPHZ

Output Disable Time
tPLZ
tSU Set-up Time HIGH

or LOW, D

N to LE

tH Hold Time HIGH

or LOW, D

N to LE

tW LE Pulse Width HIGH

(2)

Com'l.

(1)

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit

1.5 8.0 1.5 8.5 1.5 5.2 1.5 5.6 1.5 4.2 1.5 5.1 ns

2.0 13.0 2.0 15.0 2.0 8.5 2.0 9.8 2.0 5.5 2.0 8.0 ns

1.5 12.0 1.5 13.5 1.5 6.5 1.5 7.5 1.5 5.5 1.5 6.3 ns

1.5 7.5 1.5 10.0 1.5 5.5 1.5 6.5 1.5 5.0 1.5 5.9 ns

2.0 — 2.0 — 2.0 — 2.0 — 2.0 — 2.0 — ns

1.5 — 1.5 — 1.5 — 1.5 — 1.5 — 1.5 — ns

6.0 — 6.0 — 5.0 — 6.0 — 5.0 — 6.0 — ns

Mil.

(2)

Com'l.

(2)

Mil.

(2)

Com'l.

(2)

Mil.

(2)

2602 tbl 08

SWITCHING CHARACTERISTICS OVER OPERATING RANGE FOR FCT533/A/C

FCT533 FCT533A FCT533C

(2)

Com'l.

Symbol Parameter Conditions

tPLH
tPHL

tPLH
tPHL
tPZH

Propagation Delay
D

N to ON

Propagation Delay
LE to

O

N

Output Enable Time

CL = 50pF

R

L = 500Ω

tPZL
tPHZ

Output Disable Time
tPLZ
tSU Set-up Time HIGH

or LOW, D

N to LE

tH Hold Time HIGH

or LOW, D

N to LE

tW LE Pulse Width HIGH

NOTES: 2602 tbl 09

1. See test circuit and waveforms.

2. Minimum limits are guaranteed but not tested on Propagation Delays.

(1)

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit

1.5 10.0 1.5 12.0 1.5 5.2 1.5 5.6 1.5 4.7 1.5 5.1 ns

2.0 13.0 2.0 14.0 2.0 8.5 2.0 9.8 2.0 6.9 2.0 8.0 ns

1.5 11.0 1.5 12.5 1.5 6.5 1.5 7.5 1.5 5.5 1.5 6.3 ns

1.5 7.0 1.5 8.5 1.5 5.5 1.5 6.5 1.5 5.0 1.5 5.9 ns

2.0 — 2.0 — 2.0 — 2.0 — 2.0 — 2.0 — ns

1.5 — 1.5 — 1.5 — 1.5 — 1.5 — 1.5 — ns

6.0 — 6.0 — 5.0 — 6.0 — 5.0 — 6.0 — ns

Mil.

(2)

Com'l.

(2)

Mil.

(2)

Com'l.

(2)

Mil.

(2)

7.12 6

IDT54/74FCT373/533/573/A/C
FAST CMOS OCTAL TRANSPARENT LATCHES MILITARY AND COMMERCIAL TEMPERATURE RANGES

TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS

VCC

500Ω

Pulse

Generator

VIN

D.U.T.

RT

VOUT

50pF

CL

500Ω

7.0V

SWITCH POSITION

Test Switch

Open Drain

Disable Low Closed

Enable Low

All Other Tests Open

DEFINITIONS: 2537 tbl 10

CL = Load capacitance: includes jig and probe capacitance.

T = Termination resistance: should be equal to ZOUT of the Pulse

R

Generator.

SET-UP, HOLD AND RELEASE TIMES PULSE WIDTH

DATA

INPUT

TIMING

INPUT

ASYNCHRONOUS CONTROL

PRESET

CLEAR

ETC.

SYNCHRONOUS CONTROL

PRESET

CLOCK ENABLE

CLEAR

ETC.

t

tSU

SU

t

REM

t

t

H

H

3V

1.5V
0V

3V

1.5V
0V

3V

1.5V
0V

3V

1.5V
0V

LOW-HIGH-LOW

HIGH-LOW-HIGH

PULSE

PULSE

1.5V

t

W

1.5V

SAME PHASE

INPUT TRANSITION

OUTPUT

OPPOSITE PHASE

INPUT TRANSITION

ENABLE AND DISABLE TIMESPROPAGATION DELAY

ENABLE DISABLE

0.3V

0.3V

3V

1.5V
0V

3.5V

V

OL

V

OH

0V

3V

1.5V

t

PLH

t

PLH

t

t

PHL

PHL

0V
V

OH

1.5V
V

OL

3V

1.5V
0V

CONTROL

INPUT

OUTPUT

NORMALLY

LOW

OUTPUT

NORMALLY

HIGH

t

PZL

SWITCH
CLOSED

t

PZH

SWITCH
OPEN

3.5V

1.5V

1.5V
0V

t

PHZ

t

PLZ

NOTES 2537 drw 04

1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH.

2. Pulse Generator for All Pulses: Rate ≤ 1.0 MHz; Z
t

R ≤ 2.5ns.

O ≤ 50Ω; tF ≤ 2.5ns;

7.12 7

IDT54/74FCT373/533/573/A/C
FAST CMOS OCTAL TRANSPARENT LATCHES MILITARY AND COMMERCIAL TEMPERATURE RANGES

ORDERING INFORMATION

FCT

IDT XX

Temp. Range

XXXX
Device TypeXPackage

X

Process

Blank
B

P
D
SO
L
E

373
573
533
373A
573A
533A
373C
573C
533C

54
74

Commercial
MIL-STD-883, Class B

Plastic DIP
CERDIP
Small Outline IC
Leadless Chip Carrier
CERPACK

Non-Inverting Octal Transparent Latch
Non-Inverting Octal Transparent Latch
Inverting Octal Transparent Latch
Fast Non-Inverting Octal Transparent Latch
Fast Non-Inverting Octal Transparent Latch
Fast Inverting Octal Transparent Latch
Super Fast Non-Inverting Octal Transparent Latch
Super Fast Non-Inverting Octal Transparent Latch
Super Fast Inverting Octal Transparent Latch

°

C to +125°C

–55
0

°

C to +70°C

2602 cnv* 14

7.12 8