Datasheet IDT74FCT3932100PV, IDT74FCT3932100PA, IDT74FCT32932100PV Datasheet (Integrated Device Technology)
IDT74FCT3932-100, IDT74FCT32932-100
LOW SKEW PLL-BASED CLOCK DRIVER COMMERCIAL TEMPERATURE RANGES
9.9 1
Integrated Device Technology, Inc.
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
1
COMMERCIAL TEMPERATURE RANGE NOVEMBER 1996
1996 Integrated Device Technology, Inc. 9.9 DSC-3267/2
FEATURES:
• 0.5 MICRON CMOS Technology
• Guaranteed low skew
• 16 programmable frequency configurations
• 17 3-state outputs: ±24 mA FCT3932
±8 mA FCT32932
• Output configuration:
BANK1: 4 outputs
BANK2: 8 outputs
BANK3: 5 outputs
• Dedicated feedback output (Q_FB)
• Maximum output frequency: 100MHz
•V
CC = 3.3V ±0.3V
• Inputs can be driven from 3.3V or 5V components
• Available in 48 SSOP, TSSOP packages
• Suited to SDRAM applications
feedback path delay should be made to match this output path
delay.
The PLL consists of the phase/frequency detector, charge
pump, loop filter and VCO. The FCT3932 requires no external
loop filter components.
The FCT3932 provides 17 outputs grouped in 3 banks with
individual 3-state control and an additional dedicated feedback output with no disable. Connecting Q_FB to FEEDBACK
ensures uninterrupted PLL operation when all outputs are
disabled.
Individual bank 3-state allows users to disable unused
outputs in order to limit power dissipation or minimize switching noise. It also allows users to shut down outputs in low
power modes while maintaining phase lock.
The FCT3932 provides a LOCK pin that goes high when the
device is phase-locked.
The user can bypass the PLL for testability purposes by
deasserting PLL_EN. In this "test" mode, the input frequency
is not limited to the specified range.
The FCT3932 provides an asynchronous reset input,
RST
,
which resets all outputs. This initializes all internal registers so
that outputs start up in a known state.
APPLICATIONS:
SDRAM DIMM Clock, Caches, high speed microproces-
sors, motherboard clock distribution to DIMMs.
3.3V LOW SKEW PLL-BASED
CMOS CLOCK DRIVER
IDT74FCT3932-100
IDT74FCT32932-100
ADVANCE INFORMATION
FUNCTIONAL BLOCK DIAGRAM
3267 drw 01
DESCRIPTION:
The FCT3932 uses phase-lock loop technology to lock the
frequency and phase of the feedback to the input reference
clock. It provides a large number of low skew outputs that are
configurable in 16 different modes using the CNTRL 1-4
inputs. A dedicated output, Q_FB, is provided to supply the
PLL feedback and it should be connected to the FEEDBACK
input. Q_FB is located adjacent to FEEDBACK to minimize
the delay in the feedback path. In order to offset any delay in
the output path from the FCT3932 output to a receiving device,
Phase/Freq.
Detector
FEEDBACK
REF_IN
PLL_EN
Mux
0
1
Charge
Pump &
Loop Filter
Voltage
Controlled
Oscillator
OE
1
Q4
1-4
(BANK 1)
Q81-8
(BANK 2)
Q51-5
(BANK 3)
Q_FB
C
O
N
T
R
O
L
LOCK
OE
3
CNTRL1-4
OE
2
RST
IDT74FCT3932-100, IDT74FCT32932-100
LOW SKEW PLL-BASED CMOS CLOCK DRIVER COMMERCIAL TEMPERATURE RANGES
9.9 2
PIN CONFIGURATIONS ABSOLUTE MAXIMUM RATINGS
(1)
NOTE:
1. This parameter is measured at characterization but not tested.
CAPACITANCE (TA = +25°C, f = 1.0MHz)
3267 lnk 02
3267 drw 02
*NC = No connect
Q5
5
GND
CNTRL2
V
CC
FEEDBACK
AV
CC
AGND
OE2
CNTRL1
CNTRL3
CNTRL4
Q_FB
GND
REF_IN
NC
GND
OE3
RST
OE1
Q5
4
Q5
3
GND
Q5
2
Q5
1
V
CC
Q4
3
GND
Q4
2
V
CC
V
CC
Q8
8
GND
Q8
6
Q8
7
Q4
4
Q4
1
Q8
5
39
29
30
31
32
33
34
35
36
37
38
25
26
27
28
48
47
41
42
43
44
45
46
40
1
2
3
4
5
6
7
8
9
10
12
13
14
15
16
17
18
19
20
11
21
22
23
24
SSOP
TSSOP
TOP VIEW
SO48-1
SO48-2
V
CC
V
CC
Q8
4
PLL_EN
LOCK
V
CC
Q8
3
GND
Q8
2
Q8
1
GND
Symbol Parameter
(1)
Conditions Typ. Max. Unit
C
IN
Input
Capacitance
VIN = 0V 3.2 5.0 pF
C
I/O
I/O
Capacitance
V
OUT
= 0V 3.7 8.0 pF
Symbol Description Max. Unit
VTERM
(2)
Terminal Voltage with Respect to
GND
–0.5 to +4.6 V
VTERM
(3)
Terminal Voltage with Respect to
GND
–0.5 to +7.0 V
VTERM
(4)
Terminal Voltage with Respect to
GND
–0.5 to VCC
+ 0.5
V
TSTG Storage Temperature –65 to +150 °C
IOUT DC Output Current –60 to +60 mA
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. Vcc terminals.
3. Input terminals.
4. Output and I/O terminals.
3267 tbl 01
IDT74FCT3932-100, IDT74FCT32932-100
LOW SKEW PLL-BASED CLOCK DRIVER COMMERCIAL TEMPERATURE RANGES
9.9 3
PIN DESCRIPTION
Pin Name I/O Description
REF_IN I Reference clock input.
FEEDBACK I Feedback input to phase detector.
Q41-4 O BANK1 clock outputs.
Q81-8 O BANK2 clock outputs.
Q51-5 O BANK3 clock outputs.
OE
1-3 I Output enable controls for BANKS 1, 2 and 3 (Active LOW).
CNTRL1-4 I Control lines to select output configuration (see table).
Q_FB O Dedicated PLL feedback output.
RST
I Asynchronous reset (Active LOW).
PLL_EN I Disables phase-lock for low frequency testing (Refer to functional block diagram).
LOCK O PLL "LOCK" indicator (HIGH when PLL is locked).
3267 tbl 03
MODE CNTRL
4 3 2 1
Q_FEEDBACK Q_BANK1
(4 outputs)
Q_BANK2
(8 outputs)
Q_BANK3
(5 outputs)
FIN Range
0 0 0 0 0 F (divide-by-1)
F
F F 50-100MHz
1 0 0 0 1 F (divide-by-1)
F
F F/2 50-100MHz
2 0 0 1 0 F (divide-by-1) F F F 50-100MHz
3 0 0 1 1 F (divide-by-1) F F/2 F/2 50-100MHz
4 0 1 0 0 F (divide-by-1) F F/3 F 50-100MHz
5 0 1 0 1 F (divide-by-3) 3F 3F F 16.7-33.3MHz
6 0 1 1 0 F (divide-by-3) 3F F 3F 16.7-33.3MHz
7 0 1 1 1 F (divide-by-3) 3F 3F 3F 16.7-33.3MHz
8 1 0 0 0 F (divide-by-2) 2F 2F 2F 25-50MHz
9 1 0 0 1 F (divide-by-2) 2F F 2F 25-50MHz
10 1 0 1 0 F (divide-by-2) 2F F F 25-50MHz
11 1 0 1 1 F (divide-by-2) 2F F F/2 25-50MHz
12 1 1 0 0 F (divide-by-2) 2F F/2 F 25-50MHz
13 1 1 0 1 F (divide-by-4) 4F 2F 4F 12.5-25MHz
14 1 1 1 0 F (divide-by-4) 4F 2F 2F 12.5-25MHz
15 1 1 1 1 F (divide-by-4) 4F 2F F 12.5-25MHz
3267 tbl 04
OUTPUT FREQUENCY CONFIGURATION AND INPUT FREQUENCY RANGE TABLE
IDT74FCT3932-100, IDT74FCT32932-100
LOW SKEW PLL-BASED CMOS CLOCK DRIVER COMMERCIAL TEMPERATURE RANGES
9.9 4
Symbol Parameter Test Conditions
(1)
Min. Typ.
(2)
Max. Unit
VIH Input HIGH Level (Input pins) Guaranteed Logic HIGH Level 2.0 — 5.5 V
Input HIGH Level (I/O pins) 2.0 — VCC+0.5
VIL Input LOW Level Guaranteed Logic LOW Level –0.5 — 0.8 V
(Input and I/O pins)
II H Input HIGH Current (Input pins) VCC = Max. VI = 5.5V — — ±1 µA
II L Input LOW Current (Input pins) VI = GND — — ±1
IOZH High Impedance Output Current VCC = Max. VO = VCC ——±1µA
IOZL (3-State Output pins) VO = GND — — ±1
VIK Clamp Diode Voltage VCC = Min., IIN = –18mA — –0.7 –1.2 V
IODH Output HIGH Current VCC = 3.3V, VIN = VIH or VIL, VO = 1.5V
(3)
–36 –75 mA
IODL Output LOW Current VCC = 3.3V, VIN = VIH or VIL, VO = 1.5V
(3)
50 75 mA
ICCL
ICCH
ICCZ
Quiescent Power Supply Current VCC = Max., VIN = GND or VCC —— 6mA
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: TA = 0°C to 70°C, VCC = 3.3V ± 0.3V
3267 tbl 05
TYPE 2 DRIVER - FCT32932
Symbol Parameter Test Conditions
(1)
Min. Typ.
(2)
Max. Unit
VOH Output HIGH Voltage VCC = Min. IOH = –0.1mA VCC–0.2 — — V
VIN = VIH or VIL
VCC = 3.0V
V
IN = VIH or VIL
IOH = –8mA 2.4
(4)
3.0 —
VOL Output LOW Voltage VCC = Min. IOL = 0.05mA — — 0.2 V
VIN = VIH or VIL IOL = 4mA — 0.2 0.4
IOL = 8mA — 0.3 0.5
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 3.3V, +25°C ambient.
3. Not more than one output should be tested at one time. Duration of the test should not exceed one second.
4. V
OH = VCC –0.6V at rated current.
TYPE 1 DRIVER - FCT3932
3267 tbl 06
3267 tbl 07
Symbol Parameter Test Conditions
(1)
Min. Typ.
(2)
Max. Unit
VOH Output HIGH Voltage VCC = Min. IOH = –0.1mA VCC–0.2 — — V
VIN = VIH or VIL
VCC = 3.0V
V
IN = VIH or VIL
IOH = –8mA 2.2
(4)
2.4 —
VOL Output LOW Voltage VCC = Min. IOL = 0.1mA — — 0.2 V
VIN = VIH or VIL IOL = 16mA — 0.2 0.4
IOL = 24mA — 0.3 0.5
IDT74FCT3932-100, IDT74FCT32932-100
LOW SKEW PLL-BASED CLOCK DRIVER COMMERCIAL TEMPERATURE RANGES
9.9 5
POWER SUPPLY CHARACTERISTICS
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics.
2. Typical values are at V
CC = 3.3V, +25°C ambient.
3. Per TTL driven input; all other inputs at V
CC or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations. It is derived with Q frequency as the reference.
5. Values for these conditions are examples of the I
CC formula. These limits are guaranteed but not tested.
6. I
C = IQUIESCENT + IINPUTS + IDYNAMIC
IC = ICC + ∆ICC DHNT + ICCD (f) + ILOAD
ICC = Quiescent Current (ICCL, ICCH and ICCZ)
∆I
CC = Power Supply Current for a TTL High Input
D
H = Duty Cycle for TTL Inputs High
N
T = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
f = SYNC input frequency
I
LOAD = Dynamic Current due to load.
3267 tbl 08
Symbol Parameter Test Conditions
(1)
Min. Typ.
(2)
Max. Unit
∆ICC Quiescent Power Supply Current
TTL Inputs HIGH
VCC = Max. VIN = VCC –0.6V
(3)
— 2.0 30 µA
ICCD Dynamic Power Supply
Current
(4)
VCC = Max.
All Outputs Open
50% Duty Cycle
VIN = VCC F = 50Mhz
V
IN = GND
MODE 10
—72 µA/
MHz/
bit
IC Total Power Supply Current
(5,6)
VCC = Max.
PLL_EN = 1, LOCK = 1, MODE 10
REF_IN frequency = 50MHz.
All outputs open
—62 mA
INPUT TIMING REQUIREMENTS
Symbol Parameter Min. Max. Unit
tRISE/FALL Rise/Fall Times REF_IN input (0.8V to 2.0V) — 3.0 ns
Frequency Input Frequency REF_IN input Modes 0, 1, 2, 3, 4 50 100 MHz
Modes 5, 6, 7 16.7 33.3
Modes 8, 9, 10, 11, 12 25 50
Modes 13, 14, 15 12.5 25
Duty Cycle Input Duty Cycle, REF_IN input 25 75 %
3267 tbl 09
OUTPUT FREQUENCY SPECIFICATIONS
3267 tbl 10
Mode Parameter Min. Max. Unit
0, 1, 2, 3,4 Operating F, F Outputs 50 100 MHz
frequency F/2 Outputs 25 50
F/3 Outputs 16.7 33.3
5, 6, 7 Operating 3F Outputs 50 100
frequency F Outputs 16.7 33.3
8, 9, 10, 11, 12 Operating 2F Outputs 50 100
frequency F Outputs 25 50
F/2 Outputs 12.5 25
13, 14, 15 Operating 4F Outputs 50 100
frequency 2F Outputs 25 50
F Outputs 12.5 25
IDT74FCT3932-100, IDT74FCT32932-100
LOW SKEW PLL-BASED CMOS CLOCK DRIVER COMMERCIAL TEMPERATURE RANGES
9.9 6
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
(7)
GENERAL AC SPECIFICATION NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested.
3. These specifications are guaranteed but not production tested.
4. Under equally loaded conditions, as specified under test conditions and at a fixed temperature and voltage.
5. With V
CC fully powered-on and Q_FB properly connected to the FEEDBACK pin.
6. The tPD spec gives the limits of the phase offset between the REF_IN input and the Q_FB output.
7. The AC specifications are only guaranteed with the decoupling scheme shown in figure 2.
3267 tbl 13
Feedback Output
tPD = ±0.5ns
REF_IN input
Offset
3267 drw 03
Symbol Parameter Condition
(1)
Min.
(2)
Max. Unit
tPD
(3)
REF_IN-Q_FB
Propagation Delay
(REF_IN input to Q outputs)
No Load –0.5 +0.5 ns
tRISE/FALL Rise/Fall Time (between 0.8 and 2.0V) FCT3932 CL = 20pF for FCT3932 0.5 1.5 ns
All Outputs FCT32932 CL = 10pF for FCT32932 0.5 2.0
tPW
(3)
Output Duty Cycle 45 55 %
tSKEWr
(3,4)
Output to Output Skew (All outputs at
same frequency rising edge)
— 500 ps
tSKEWf
(3,4)
Output to Output Skew (All outputs at
same frequency falling edge)
— 500 ps
tSKEWall
(3,4)
Output to Output Skew (All outputs,
rising edge any frequency)
— 1.0 ns
tLOCK
(5)
Time required to acquire
Phase-Lock from time
REF_IN input signal is received
110ms
tPZH
tPZL
Output Enable Time OEx
(LOW-to-HIGH) to Q
3.0 8.0 ns
tPHZ
tPLZ
Output Disable Time OEx
(HIGH-to-LOW) to Q
3.0 8.0 ns
IDT74FCT3932-100, IDT74FCT32932-100
LOW SKEW PLL-BASED CLOCK DRIVER COMMERCIAL TEMPERATURE RANGES
9.9 7
Figure 2. Recommended Decoupling for the FCT3932/FCT32932
NOTES:
1. Figure 2 shows a decoupling scheme which will be effective in most FCT3932 applications. The following guidelines should be followed for stable, jitterfree operation:
a. All decoupling capacitors should be connected as close to the package as possible. (Preferably at the device pins).
b. The 10µF and 0.1µF bypass capacitors provide protection from power supply and ground plane transients.
3267 drw 04
(1)
(7)
(13)
(24)
(43)
(37)
(36)
(30)
0.1µF
0.1µF
Board V
CC Plane
0.1µF
FCT3932
10µF
0.1µF
0.1µF
STANDARD LOAD (USED WHEN SPECIFIED)
50pF
500
Ω
IDT74FCT3932-100, IDT74FCT32932-100
LOW SKEW PLL-BASED CMOS CLOCK DRIVER COMMERCIAL TEMPERATURE RANGES
9.9 8
TEST CIRCUITS AND WAVEFORMS
TEST CIRCUIT
PROPAGATION DELAY, OUTPUT SKEW
ENABLE/DISABLE TEST CIRCUIT
3267 drw 05
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH
2. Pulse Generator for All Pulses: t
F ≤ 2.5ns; tR ≤ 2.5ns
3267 drw 06
ENABLE AND DISABLE TIMES SWITCH POSITION
DEFINITIONS:
C
L= Load capacitance: includes jig and probe capacitance.
R
T = Termination resistance: should be equal to ZOUT of the Pulse
Generator.
Test Switch
Open Drain
Disable Low
Enable Low
6V
Disable High
Enable High
GND
All Other tests Open
CONTROL
INPUT
3V
1.5V
0V
3.5V
0V
OUTPUT
NORMALLY
LOW
OUTPUT
NORMALLY
HIGH
SWITCH
CLOSED
SWITCH
OPEN
V
OL
V
OH
0.3V
0.3V
t
PLZ
t
PZL
t
PZH
t
PHZ
3.5V
0V
1.5V
1.5V
ENABLE DISABLE
3267 drw 08
3267 lnk 14
REF_IN
INPUT
Q_FB
3V
1.5V
0V
VOH
1.5V
VOL
VOH
1.5V
VOL
VOH
1.5V
VOL
VOH
1.5V
VOL
Qxx
Qyy
Qzz
tPD
tSKEWf
tSKEWf
tSKEWr
tSKEWf
tSKEWr
tSKEWall
tSKEWr
3267 drw 07
Pulse
Generator
D.U.T.
V
CC
V
IN
V
OUT
500
Ω
GND
6.0V
500
Ω
R
T
C
L
Open
Pulse
Generator
R
T
D.U.T.
V
CC
V
IN
V
OUT
C
L
IDT74FCT3932-100, IDT74FCT32932-100
LOW SKEW PLL-BASED CLOCK DRIVER COMMERCIAL TEMPERATURE RANGES
9.9 9
ORDERING INFORMATION
IDT XX
Temp. Range
XXXX
Device Type
X
Package
PV
PA
3932
32932
Small Shrink Outline Package (SO48-1)
Thin Shrink Small Outline Package (SO48-2)
3.3V Low skew PLL-based
CMOS clock driver
74
0
°
C to +70°C
FCT
X
Speed
3267 drw 09
100
50 - 100Mhz
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