Datasheet IDT74FCT574TDB, IDT74FCT574TD, IDT74FCT574TQB, IDT74FCT574TQ, IDT74FCT574TPYB Datasheet (Integrated Device Technology)

MILITARY AND COMMERCIAL TEMPERATURE RANGES AUGUST 1995

1995 Integrated Device Technology, Inc. 6.13 DSC-4214/5

Integrated Device Technology, Inc.

DESCRIPTION

The FCT374T/FCT2374T, FCT534T and FCT574T/
FCT2574T are 8-bit registers built using an advanced dual
metal CMOS technology. These registers consist of eight D­type flip-flops with a buffered common clock and buffered 3­state output control. When the output enable (OE) input is

LOW, the eight outputs are enabled. When the OE input is
HIGH, the outputs are in the high-impedance state.

Input data meeting the set-up and hold time requirements
of the D inputs is transferred to the Q outputs on the LOW-to­HIGH transition of the clock input.

The FCT2374T and FCT2574T have balanced output drive
with current limiting resistors. This offers low ground bounce,
minimal undershoot and controlled output fall times-reducing
the need for external series terminating resistors. FCT2xxxT
parts are plug-in replacements for FCTxxxT parts.

1

FAST CMOS OCTAL D
REGISTERS (3-STATE)

FEATURES:

• Common features:

– Low input and output leakage ≤1µA (max.)
– CMOS power levels
– True TTL input and output compatibility

– VOH = 3.3V (typ.)
– V

OL = 0.3V (typ.)

– Meets or exceeds JEDEC standard 18 specifications
– Product available in Radiation Tolerant and Radiation

Enhanced versions

– Military product compliant to MIL-STD-883, Class B

and DESC listed (dual marked)

– Available in DIP, SOIC, SSOP, QSOP, CERPACK

and LCC packages

• Features for FCT374T/FCT534T/FCT574T:

– Std., A, C and D speed grades
– High drive outputs (-15mA IOH, 48mA IOL)

• Features for FCT2374T/FCT2574T:

– Std., A, and C speed grades
– Resistor outputs (-15mA IOH, 12mA IOL Com.)

(-12mA IOH, 12mA IOL Mil.)

– Reduced system switching noise

D0

Q0

D1

Q1

D2

Q2

D3

Q3

D4

Q4

D5

Q5

D6

Q6

D7

Q7

CP

OE

D
Q

CP

D

CP

D

CP

D

CP

D

CP

D

CP

D

CP

D

CP

2569 drw 01

QQQ Q

Q

QQ

2569 drw 02

D0

Q0

D1

Q1

D2

Q2

D3

Q3

D4

Q4

D5

Q5

D6

Q6

D7

Q7

CP

OE

D
Q

CP

D

Q

CP

D
Q

CP

D
Q

CP

D

Q

CP

D
Q

CP

D
Q

CP

D

Q

CP

FUNCTIONAL BLOCK DIAGRAM FCT534T

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

IDT54/74FCT374T/AT/CT/DT - 2374T/AT/CT

IDT54/74FCT534T/AT/CT

IDT54/74FCT574T/AT/CT/DT - 2574T/AT/CT

FUNCTIONAL BLOCK DIAGRAM FCT374/FCT2374T AND FCT574/FCT2574T

6.13 2

IDT54/74FCT374T/AT/CT/DT - 2374T/AT/CT, IDT54/74FCT534T/AT/CT, IDT54/74FCT574T/AT/CT/DT - 2574T/AT/CT
FAST CMOS OCTAL D REGISTERS (3-STATE) MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT54/74FCT534T

PIN CONFIGURATIONS

IDT54/74FCT374T

IDT54/74FCT574T

2569 drw 04

2569 drw 05

2569 drw 03

INDEX

D

1

Q

1

Q

2

D

2

D

3

D

7

D

6

Q

6

Q

5

D

5

LCC

TOP VIEW

3 2 20 19

1

4
5

6
7
8

18
17

16
15
14

910111213

L20-2

D

0Q0

OE

V

CCQ7

Q

3

GND

CP

Q

4

D

4

OE

Q

0

D0

D1
Q1
Q2
D2

D3
Q3

GND

Q

7

D7
D6
Q6
Q5

D4

CP

D

5

Q4

VCC1

2
3
4

5
6
7
8
9
10 11

12

13

14

15

16

17

18

19

20

DIP/SOIC/SSOP/QSOP/CERPACK

TOP VIEW

P20-1

D20-1
SO20-2
SO20-7
SO20-8

&

E20-1

OE

D

0

D

1

D

2

D

3

D

4

D

5

D

6

D

7

GND

Q

0

Q

1

Q

2

Q

3

Q

4

Q

6

CP

Q

5

Q

7

V

CC

1
2

3
4
5
6
7
8
9
10 11

12

13

14

15

16

17

18

19

20

DIP/SOIC/SSOP/QSOP/CERPACK

TOP VIEW

P20-1

D20-1
SO20-2
SO20-7
SO20-8

&

E20-1

OE

Q

0

D0
D1

Q1
Q2

D2
D3

Q3

GND

Q

7

D7
D6

Q6
Q5

D4

CP

D

5

Q4

VCC1

2
3
4

5
6
7
8
9
10 11

12

13

14

15

16

17

18

19

20

DIP/SOIC/QSOP/CERPACK

TOP VIEW

P20-1

D20-1
SO20-2
SO20-8

&

E20-1

INDEX

D1 D7

LCC

TOP VIEW

D

6

Q6
Q5

D5

Q1
Q2
D2
D3

3 2 20 19

1

4
5
6
7
8

18
17
16
15
14

9 10111213

L20-2

D0

VCC

Q7

Q0

OE

Q3

GND

CP

Q

4

D4

INDEX

D2
D3
D4
D5
D6

Q1
Q2
Q3
Q4
Q5

D7

GND

CP

Q

7

Q6

LCC

TOP VIEW

3 2 20 19

1

4
5
6
7
8

18
17
16
15
14

9 10111213

L20-2

D1

D0

OE

V

CC

Q0

IDT54/74FCT374T/AT/CT/DT - 2374T/AT/CT, IDT54/74FCT534T/AT/CT, IDT54/74FCT574T/AT/CT/DT - 2574T/AT/CT
FAST CMOS OCTAL D REGISTERS (3-STATE) MILITARY AND COMMERCIAL TEMPERATURE RANGES

6.13 3

PIN DESCRIPTION

FUNCTION TABLE

(1)

ABSOLUTE MAXIMUM RATINGS

(1)

CAPACITANCE (TA = +25°C, f = 1.0MHz)

Symbol Rating Commercial Military Unit

VTERM

(2)

Terminal Voltage
with Respect to
GND

–0.5 to +7.0 –0.5 to +7.0 V

VTERM

(3)

Terminal Voltage
with Respect to
GND

–0.5 to

V

CC +0.5

–0.5 to

VCC +0.5

V

TA Operating

Temperature

0 to +70 –55 to +125 °C

TBIAS Temperature

Under Bias

–55 to +125 –65 to +135 °C

TSTG Storage

Temperature

–55 to +125 –65 to +150 °C

PT Power Dissipation 0.5 0.5 W
IOUT DC Output

Current

–60 to +120 –60 to +120 mA

2569 tbl 01

NOTES:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT­INGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability. No terminal voltage may exceed
V

CC by +0.5V unless otherwise noted.

2. Input and V

CC terminals only.

3. Outputs and I/O terminals only.

2569 lnk 03

NOTE: 2569 tbl 02

1. H = HIGH Voltage Level

L = LOW Voltage Level
X = Don’t Care
Z = High Impedance
NC = No Change

↑ = LOW-to-HIGH transition

NOTE:

1. This parameter is measured at characterization but not tested.

2569 lnk 04

Symbol Parameter

(1)

Conditions Typ. Max. Unit

CIN Input

Capacitance

VIN = 0V 6 10 pF

COUT Output

Capacitance

VOUT = 0V 8 12 pF

Pin Names Description

DN D flip-flop data inputs
CP Clock Pulse for the register. Enters data on

LOW-to-HIGH transition.

QN 3-state outputs, (true)

Q

N 3-state outputs, (inverted)

OE

Active LOW 3-state Output Enable input

534 374/574

Inputs Outputs Internal Outputs Internal

Function

OE

OE

CP DN

Q

Q

N QN QN

Q

Q

N

HI-Z H

H

L

H

X
X

Z
Z

NC
NC

Z
Z

NC
NC

LOAD REGISTER L

L
H
H

↑
↑
↑
↑

L

H

L

H

H

L
Z
Z

L

H

L

H

L

H

Z
Z

H

L

H

L

6.13 4

IDT54/74FCT374T/AT/CT/DT - 2374T/AT/CT, IDT54/74FCT534T/AT/CT, IDT54/74FCT574T/AT/CT/DT - 2574T/AT/CT
FAST CMOS OCTAL D REGISTERS (3-STATE) MILITARY AND COMMERCIAL TEMPERATURE RANGES

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE

Following Conditions Apply Unless Otherwise Specified:
Commercial: TA = 0°C to +70°C, VCC = 5.0V ± 5%; Military: TA = –55°C to +125°C, VCC = 5.0V ± 10%

Symbol Parameter Test Conditions

(1)

Min. Typ.

(2)

Max. Unit

V

IH

Input HIGH Level Guaranteed Logic HIGH Level 2.0 — — V

V

IL

Input LOW Level Guaranteed Logic LOW Level — — 0.8 V

I

I H

Input HIGH Current

(4)

VCC = Max. VI = 2.7V — —

±

1

µ

A

I

I L

Input LOW Current

(4)

VI = 0.5V — —

±

1

I

OZH

High Impedance Output Current VCC = Max. VO = 2.7V — —

±

1

µ

A

I

OZL

(3-State Output pins)

(4)

VO = 0.5V — —

±

1

II Input HIGH Current

(4)

VCC = Max., VI = V

CC

(Max.) — —

±

1

µ

A

V

IK

Clamp Diode Voltage VCC = Min., I

IN

= –18mA — –0.7 –1.2 V

V

H

Input Hysteresis

—

— 200 — mV

I

CC

Quiescent Power Supply Current VCC = Max., VIN = GND or V

CC

— 0.01 1 mA

2569 lnk 05

OUTPUT DRIVE CHARACTERISTICS FOR FCT374T/534T/574T

Symbol Parameter Test Conditions

(1)

Min. Typ.

(2)

Max. Unit

V

OH

Output HIGH Voltage VCC = Min.

V

IN

= V

IH

or V

IL

IOH = –6mA MIL.
I

OH

= –8mA COM'L.

2.4 3.3 — V

IOH = –12mA MIL.
I

OH

= –15mA COM'L.

2.0 3.0 — V

V

OL

Output LOW Voltage VCC = Min.

V

IN

= V

IH

or V

IL

I

OL

= 32mA MIL.

I

OL

= 48mA COM'L.

— 0.3 0.5 V

I

OS

Short Circuit Current VCC = Max., VO = GND

(3)

–60 –120 –225 mA

OUTPUT DRIVE CHARACTERISTICS FOR FCT2374T/2574T

2569 lnk 06

2569 lnk 07

NOTES:

1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.

2. Typical values are at Vcc = 5.0V, +25°C ambient.

3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.

4. The test limit for this parameter is ±5µA at T

A = –55°C.

Symbol Parameter Test Conditions

(1)

Min. Typ.

(2)

Max. Unit

IODL Output LOW Current VCC = 5V, VIN = VIH or VIL, VOUT = 1.5V

(3)

16 48 — mA

IODH Output HIGH Current VCC = 5V, VIN = VIH or V IL, VOUT = 1.5V

(3)

–16 –48 — mA

VOH Output HIGH Voltage VCC = Min.

V

IN = VIH or VIL

IOH = –12mA MIL.
I

OH = –15mA COM'L.

2.4 3.3 — V

VOL Output LOW Voltage VCC = Min.

V

IN = VIH or VIL

IOL = 12mA — 0.3 0.50 V

IDT54/74FCT374T/AT/CT/DT - 2374T/AT/CT, IDT54/74FCT534T/AT/CT, IDT54/74FCT574T/AT/CT/DT - 2574T/AT/CT
FAST CMOS OCTAL D REGISTERS (3-STATE) MILITARY AND COMMERCIAL TEMPERATURE RANGES

6.13 5

POWER SUPPLY CHARACTERISTICS

NOTES:

1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.

2. Typical values are at V

CC = 5.0V, +25°C ambient.

3. Per TTL driven input (V

IN = 3.4V). All other inputs at VCC or GND.

4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.

5. Values for these conditions are examples of the I

CC formula. These limits are guaranteed but not tested.

6. I

C = IQUIESCENT + IINPUTS + IDYNAMIC

IC = ICC + ∆ICC DHNT + ICCD (fCP/2 + fiNi)
I

CC = Quiescent Current

∆I

CC = Power Supply Current for a TTL High Input (VIN = 3.4V)

D

H = Duty Cycle for TTL Inputs High

N

T = Number of TTL Inputs at DH

ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
f

CP = Clock Frequency for Register Devices (Zero for Non-Register Devices)

f

i = Input Frequency

N

i = Number of Inputs at fi

All currents are in milliamps and all frequencies are in megahertz.

2569 tbl 08

Symbol Parameter Test Conditions

(1)

Min. Typ.

(2)

Max. Unit

∆ICC Quiescent Power Supply Current

TTL Inputs HIGH

VCC = Max.
V

IN = 3.4V

(3)

— 0.5 2.0 mA

ICCD Dynamic Power Supply

Current

(4)

VCC = Max.
Outputs Open

VIN = VCC
VIN = GND

FCTxxxT — 0.15 0.25 mA/

MHz

OE

= GND
One Input Toggling
50% Duty Cycle

FCT2xxxT — 0.06 0.12

IC Total Power Supply Current

(6)

VCC = Max.
Outputs Open

VIN = VCC
VIN = GND

FCTxxxT — 1.5 3.5 mA

fCP = 10MHz
50% Duty Cycle

FCT2xxxT — 0.6 2.2

OE

= GND
fi = 5MHz

VIN = 3.4
V

IN = GND

FCTxxxT — 2.0 5.5

50% Duty Cycle
One Bit Toggling

FCT2xxxT 1.1 4.2

VCC = Max.
Outputs Open

VIN = VCC
VIN = GND

FCTxxxT — 3.8 7.3

(5)

fCP = 10MHz
50% Duty Cycle

FCT2xxxT — 1.5 4.0

(5)

OE

= GND
Eight Bits Toggling

VIN = 3.4
V

IN = GND

FCTxxxT — 6.0 16.3

(5)

fi = 2.5MHz
50% Duty Cycle

FCT2xxxT — 3.8 13.0

(5)

6.13 6

IDT54/74FCT374T/AT/CT/DT - 2374T/AT/CT, IDT54/74FCT534T/AT/CT, IDT54/74FCT574T/AT/CT/DT - 2574T/AT/CT
FAST CMOS OCTAL D REGISTERS (3-STATE) MILITARY AND COMMERCIAL TEMPERATURE RANGES

SWITCHING CHARACTERISTICS OVER OPERATING RANGE

NOTES: 2569 tbl 10

1. See test circuit and waveforms.

2. Minimum limits are guaranteed but not tested on Propagation Delays.

3. O

N for FCT374/2374T and FCT574/2574T, ON for FCT534T.

4. This parameter is guaranteed but not tested.

2569 tbl 09

FCT374T/534T/574T

FCT2374T/2574T

FCT374AT/534AT/574AT

FCT2374AT/2574AT

Com'l. Mil. Com'l. Mil.

Symbol Parameter Conditions

(1)

Min.

(2)

Max. Min.

(2)

Max. Min.

(2)

Max. Min.

(2)

Max.

Unit

tPLH
tPHL

Propagation Delay
CP to Q

N

(3)

CL = 50pF

R

L = 500Ω

2.0 10.0 2.0 11.0 2.0 6.5 2.0 7.2 ns

tPZH
tPZL

Output Enable Time 1.5 12.5 1.5 14.0 1.5 6.5 1.5 7.5 ns

tPHZ
tPLZ

Output Disable Time 1.5 8.0 1.5 8.0 1.5 5.5 1.5 6.5 ns

tSU Set-up Time HIGH

or LOW, D

N to CP

2.0 — 2.0 — 2.0 — 2.0 — ns

tH Hold Time HIGH

or LOW, D

N to CP

1.5 — 1.5 — 1.5 — 1.5 — ns

tW CP Pulse Width

HIGH or LOW

7.0 — 7.0 — 5.0 — 6.0 — ns

FCT374CT/534CT/574CT

FCT2374CT/2574CT FCT374DT/574DT

Com'l. Mil. Com'l. Mil.

Symbol Parameter Conditions

(1)

Min.

(2)

Max. Min.

(2)

Max. Min.

(2)

Max. Min.

(2)

Max.

Unit

tPLH
tPHL

Propagation Delay
CP to Q

N

(3)

CL = 50pF

R

L = 500Ω

2.0 5.2 2.0 6.2 2.0 4.2 — — ns

tPZH
tPZL

Output Enable Time 1.5 5.5 1.5 6.2 1.5 4.8 — — ns

tPHZ
tPLZ

Output Disable Time 1.5 5.0 1.5 5.7 1.5 4.0 — — ns

tSU Set-up Time HIGH

or LOW, D

N to CP

2.0 — 2.0 — 2.0 — — — ns

tH Hold Time HIGH

or LOW, D

N to CP

1.5 — 1.5 — 1.0 — — — ns

tW CP Pulse Width

HIGH or LOW

(4)

5.0 — 6.0 — 3.0 — — — ns

IDT54/74FCT374T/AT/CT/DT - 2374T/AT/CT, IDT54/74FCT534T/AT/CT, IDT54/74FCT574T/AT/CT/DT - 2574T/AT/CT
FAST CMOS OCTAL D REGISTERS (3-STATE) MILITARY AND COMMERCIAL TEMPERATURE RANGES

6.13 7

SET-UP, HOLD AND RELEASE TIMES PULSE WIDTH

SWITCH POSITION

ENABLE AND DISABLE TIMESPROPAGATION DELAY

Test

Switch

Disable Low

Enable Low

Closed

All Other Tests

Open

Open Drain

DEFINITIONS:

C

L= Load capacitance: includes jig and probe capacitance.

R

T = Termination resistance: should be equal to ZOUT of the Pulse

Generator.

TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS

Pulse

Generator

R

T

D.U.T.

V

CC

V

IN

C

L

V

OUT

50pF

500

Ω

500

Ω

7.0V

3V

1.5V
0V

3V

1.5V
0V

3V

1.5V
0V

3V

1.5V

0V

DATA

INPUT

TIMING

INPUT

ASYNCHRONOUS CONTROL

PRESET

CLEAR

ETC.

SYNCHRONOUS CONTROL

t

SU

t

H

t

REM

t

SU

t

H

HIGH-LOW-HIGH

PULSE

LOW-HIGH-LOW

PULSE

t

W

1.5V

1.5V

SAME PHASE

INPUT TRANSITION

3V

1.5V
0V

1.5V

V

OH

t

PLH

OUTPUT

OPPOSITE PHASE

INPUT TRANSITION

3V

1.5V
0V

t

PLH

t

PHL

t

PHL

V

OL

CONTROL

INPUT

3V

1.5V
0V

3.5V

0V

OUTPUT

NORMALLY

LOW

OUTPUT

NORMALLY

HIGH

SWITCH
CLOSED

SWITCH
OPEN

V

OL

0.3V

0.3V

t

PLZ

t

PZL

t

PZH

t

PHZ

3.5V

0V

1.5V

1.5V

ENABLE DISABLE

V

OH

PRESET

CLEAR

CLOCK ENABLE

ETC.

2569 drw 06

2569 drw 07

2569 drw 08

2569 drw 09

2569 drw 10

NOTES:

1. Diagram shown for input Control Enable-LOW and input Control Disable­HIGH

2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; t

F ≤ 2.5ns; tR ≤ 2.5ns

6.13 8

IDT54/74FCT374T/AT/CT/DT - 2374T/AT/CT, IDT54/74FCT534T/AT/CT, IDT54/74FCT574T/AT/CT/DT - 2574T/AT/CT
FAST CMOS OCTAL D REGISTERS (3-STATE) MILITARY AND COMMERCIAL TEMPERATURE RANGES

ORDERING INFORMATION

IDT XX

Temp. Range

XXXX

Device TypeXPackage

X

Process

Blank
B

P
D
SO
L
E
PY
Q

374T
574T
534T
374AT
574AT
534AT
374CT
574CT
534CT
374DT
574DT

Commercial
MIL-STD-883, Class B

Plastic DIP
CERDIP
Small Outline IC
Leadless Chip Carrier
CERPACK
Shrink Small Outline Package
Quarter-size Small Outline Package

Non-Inverting Octal D Register
Non-Inverting Octal D Register
Inverting Octal D Register

54
74

–55

°

C to +125°C

0

°

C to +70°C

FCT

X

Family

Blank2High Drive

Balanced Drive

2569 drw 11