Datasheet IDT74FCT299CSOB, IDT74FCT299CSO, IDT74FCT299CPB, IDT74FCT299CP, IDT74FCT299CLB Datasheet (Integrated Device Technology)
...
Integrated Device Technology, Inc.
FAST CMOS
8-INPUT UNIVERSAL
SHIFT REGISTER
IDT54/74FCT299
IDT54/74FCT299A
IDT54/74FCT299C
FEATURES:
• IDT54/74FCT299 equivalent to FAST speed
• IDT54/74FCT299A 25% faster than FAST
• IDT54/74FCT299C 35% faster than FAST
• Equivalent to FAST output drive over full temperature
and voltage supply extremes
•IOL = 48mA (commercial) and 32mA (military)
• CMOS power levels (1mW typ. static)
• TTL input and output level compatible
• CMOS output level compatible
• Substantially lower input current levels than FAST
(5µA max.)
• 8-input universal shift register
• JEDEC standard pinout for DIP and LCC
• Product available in Radiation Tolerant and Radiation
Enhanced versions
• Military product compliant to MIL-STD-883, Class B
• Standard Military Drawing# 5962-86862 is listed on this
function. Refer to section 2.
FUNCTIONAL BLOCK DIAGRAM
S1 S0
DESCRIPTION:
The IDT54/74FCT299 and IDT54/74FCT299A/C are built
using an advanced dual metal CMOS technology. The IDT54/
74FCT299 and IDT54/74FCT299A/C are 8-input universal
shift/storage registers with 3-state outputs. Four modes of
operation are possible: hold (store), shift left, shift right and
load data. The parallel load inputs and flip-flop outputs are
multiplexed to reduce the total number of package pins.
Additional outputs are provided for flip-flops Q0 and Q7 to
allow easy serial cascading. A separate active LOW Master
Reset is used to reset the register.
DS7
DS
0
CP
D
P
C
CD
Q
0
MR
OE1
OE2
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
FAST is a registered trademark of National Semiconductor Co.
Q
CD
D
P
C
Q
CD
D
Q
D
P
C
CD
P
C
Q
CD
D
P
C
Q
CD
D
P
C
Q
D
P
C
CD
Q
I/O6I/O5I/O4I/O3I/O2I/O1I/O0 I/O7
CD
D
C
Q
2561 drw 01
P
MILITARY AND COMMERCIAL TEMPERATURE RANGES MAY 1992
1994 Integrated Device Technology, Inc. 7.11 DSC-4604/3
1
Q7
IDT54/74FCT299/A/C
FAST CMOS 8-INPUT UNIVERSAL SHIFT REGISTER MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
S0
OE1
OE2
I/O6
I/O4
I/O2
I/O0
Q0
MR
GND
1
2
P20-1
3
D20-1
4
S020-2
5
6
E20-1
7
8
9
10
DIP/SOIC/CERPACK
TOP VIEW
20
Vcc
19
S1
18
DS7
17
Q
7
16
15
14
13
12
11
I/O7
I/O5
I/O
I/O
CP
DS
&
PIN DESCRIPTION
Pin Names Description
CP Clock Pulse Input (Active Edge Rising)
0 Serial Data Input for Right Shift
DS
7 Serial Data Input for Left Shift
DS
0, S1 Mode Select Inputs
S
MR
1, OE2 3-State Output Enable Inputs (Active LOW)
OE
0–I/O7 Parallel Data Inputs or 3-State Parallel Outputs
I/O
0, Q7 Serial Outputs
Q
Asynchronous Master Reset Input (Active LOW)
2
INDEX
I/O
6
I/O
4
I/O
2
I/O
0
Q
3
1
0
0
FUNCTION TABLE
OE
32
4
5
6
7
8
10 11 12 13
9
MR
TOP VIEW
(1)
1
OE
L20-2
GND
LCC
1
0
S
20 19
0
DS
Vcc
CP
1
S
18
17
16
15
14
1
I/O
2561 drw 02
DS
Q
I/O
I/O
I/O
7
7
7
5
3
Inputs
1 S0 CP Response
MRMRS
L X X X Asynchronous Reset Q
HH H ↑Parallel Load; I/O
0–Q7 = LOW
n → Qn
HL H ↑Shift Right; DS0 → Q0, Q0 → Q1, etc.
HH L ↑Shift Left; DS
7 → Q7, Q7→ Q6, etc.
H L L X Hold
NOTE: 2561 tbl 02
1. H = HIGH Voltage Level
L = LOW Voltage Level
2561 tbl 01
X = Don’t Care
↑ = LOW-to-HIGH clock transition
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol Rating Commercial Military Unit
(2)
V
TERM
Terminal Voltage –0.5 to +7.0 –0.5 to +7.0 V
with Respect
to GND
(3)
V
TERM
Terminal Voltage –0.5 to VCC –0.5 to VCC V
with Respect
to GND
T
A Operating 0 to +70 –55 to +125 °C
Temperature
T
BIAS Temperature –55 to +125 –65 to +135 °C
Under Bias
T
STG Storage –55 to +125 –65 to +150 °C
Temperature
P
T Power Dissipation 0.5 0.5 W
OUT DC Output Current 120 120 mA
I
NOTES: 2561 tbl 03
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability. No terminal voltage
may exceed Vcc by +0.5 unless otherwise noted.
2. Inputs and V
3. Outputs and I/O terminals only.
CC terminals only.
CAPACITANCE (TA = +25°C, f = 1.0MHz)
Symbol Parameter
IN Input Capacitance VIN = 0V 6 10 p F
C
I/O I/O Capacitance VOUT = 0V 8 12 pF
C
NOTE: 2561 tbl 04
1. This parameter is guaranteed by characterization data and not tested.
(1)
Conditions Typ. Max. Unit
7.11 2
IDT54/74FCT299/A/C
FAST CMOS 8-INPUT UNIVERSAL SHIFT REGISTER MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: VLC = 0.2V; VHC = VCC – 0.2V
Commercial: TA = 0°C to +70°C, VCC = 5.0V ± 5%; Military: TA = –55°C to +125°C, VCC = 5.0V ± 10%
Symbol Parameter Test Conditions
IH Input HIGH Level Guaranteed Logic HIGH Level 2.0 — — V
V
V
IL Input LOW Level Guaranteed Logic LOW Level — — 0.8 V
I
IH Input HIGH Current VCC = Max. VI = VCC ——5µA
(Except I/O Pins) V
(1)
I = 2.7V — — 5
Min. Typ.
IIL Input LOW Current VI = 0.5V — — –5
(Except I/O Pins) VI = GND — — –5
I
IH Input HIGH Current VCC = Max. VI = VCC ——15µA
(I/O Pins Only) V
I = 2.7V — — 15
IIL Input LOW Current VI = 0.5V — — –15
(I/O Pins Only) VI = GND — — –15
V
IK Clamp Diode Voltage Vcc = Min., IN = –18mA — –0.7 –1.2 V
I
OS Short Circuit Current Vcc = Max.
V
OH Output HIGH Voltage Vcc = 3V, VIN = VLC or VHC, IOH = –32µAVHC VCC —V
Vcc = Min. I
V
IN = VIH or VIL IOH = –12mA MIL. 2.4 4.3 —
V
OL Output LOW Voltage Vcc = 3V, VIN = VLC or VHC, IOL = 300µA — GND VLC V
Vcc = Min. I
(3)
, VO = GND –60 –120 — mA
OH = –300µAVHC VCC —
I
OH = –15mA COM’L. 2.4 4.3 —
OL = 300µA — GND VLC
VIN = VIH or VIL IOL = 32mA MIL. — 0.3 0.5
I
OL = 48mA COM’L. — 0.3 0.5
NOTES: 2561 tbl 05
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. This parameter is guaranteed but not tested.
(2)
Max. Unit
(4)
(4)
(4)
(4)
(4)
7.11 3
IDT54/74FCT299/A/C
FAST CMOS 8-INPUT UNIVERSAL SHIFT REGISTER MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
VLC = 0.2V; VHC = VCC – 0.2V
Symbol Parameter Test Conditions
CC Quiescent Power Supply Vcc = Max. — 0.2 1.5 mA
I
Current V
∆ICC Quiescent Power Supply Vcc = Max. — 0.5 2.0 mA
Current TTL Inputs HIGH V
IN ≥ VHC; VIN ≤ VLC
IN = 3.4V
(3)
(1)
Min. Typ.
(2)
Max. Unit
ICCD Dynamic Power Supply Vcc = Max. VIN ≥ VHC — 0.15 0.25 mA/MHz
Current
(4)
Outputs Open VIN ≤ VLC
OE
1 = OE2 = GND
MR
= V
CC
S0 = S1 = VCC
DS0 = DS1 = GND
One Input Toggling
50% Duty Cycle
I
C Total Power Supply Vcc = Max. VIN ≥ VHC — 1.7 4.0 mA
Current
(6)
Outputs Open VIN ≤ VLC
fCP = 10MHz (FCT)
50% Duty Cycle
OE
1 = OE2 = GND
MR
= V
CC
S0 = S1 = VCC
DS0 = DS7 = GND VIN = 3.4V — 2.2 6.0
One Bit Toggling V
at f
i = 5MHz
IN = GND
50% Duty Cycle
Vcc = Max. V
IN ≥ VHC — 4.0 7.8
(5)
Outputs Open VIN ≤ VLC
fCP = 10MHz (FCT)
50% Duty Cycle
OE
1 = OE2 = GND
MR
= V
CC
S0 = S1 = VCC
DS0 = DS7 = GND VIN = 3.4V — 6.2 16.8
(5)
Eight Bits Toggling VIN = GND
at f
i = 2.5MHz
50% Duty Cycle
NOTES: 2561 tbl 06
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
3. Per TTL driven input (V
4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
5. Values for these conditions are examples of the I
6. I
C = IQUIESCENT + IINPUTS + IDYNAMIC
IC = ICC + ∆ICC DHNT + ICCD (fCP/2 + fiNi)
CC = Quiescent Current
I
CC = Power Supply Current for a TTL High Input (VIN = 3.4V)
∆I
D
H = Duty Cycle for TTL Inputs High
T = Number of TTL Inputs at DH
N
ICCD = Dynamic Current Caused by an Output Transition Pair (HLH or LHL)
CP = Clock Frequency for Register Devices (Zero for Non-Register Devices)
f
f
i = Input Frequency
i = Number of Inputs at fi
N
All currents are in milliamps and all frequencies are in megahertz.
CC = 5.0V, +25°C ambient.
IN = 3.4V); all other inputs at VCC or GND.
CC formula. These limits are guaranteed but not tested.
7.11 4
IDT54/74FCT299/A/C
FAST CMOS 8-INPUT UNIVERSAL SHIFT REGISTER MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT54/74FCT299 IDT54/74FCT299A IDT54/74FCT299C
Com’l. Mil. Com’l. Mil. Com’l. Mil.
Symbol Parameter Condition
PLH Propagation Delay CL = 50pF 2.0 10.0 2.0 14.0 2.0 7.2 2.0 9.5 2.0 6.5 2.0 7.5 ns
t
t
PHL CP to Q0 or Q7 RL = 500Ω
t
PLH Propagation Delay 2.0 12.0 2.0 12.0 2.0 7.2 2.0 9.5 2.0 6.5 2.0 7.5 ns
t
PHL CP to I/On
(1)
tPHL Propagation Delay 2.0 10.0 2.0 10.5 2.0 7.2 2.0 9.5 2.0 6.5 2.0 7.5 ns
MR
to Q0 or Q7
tPHL Propagation Delay 2.0 15.0 2.0 15.0 2.0 8.7 2.0 11.5 2.0 6.5 2.0 7.5 ns
MR
to I/On
tPZH Output Enable Time 1.5 11.0 1.5 15.0 1.5 6.5 1.5 7.5 1.5 6.5 1.5 7.5 ns
t
PZL
OE
n to I/On
tPHZ Output Disable Time 1.5 7.0 1.5 9.0 1.5 6.0 1.5 6.5 1.5 6.0 1.5 6.5 ns
t
PLZ
OE
n to I/On
tSU Set-up Time HIGH 7.5 — 7.5 — 3.5 — 4.0 — 3.5 — 4.0 — ns
or LOW
S
0 or S1 to CP
t
H Hold Time HIGH 1.0 — 1.0 — 1.0 — 1.0 — 1.0 — 1.0 — ns
or LOW
S
0 or S1 to CP
t
SU Set-up Time HIGH 5.5 — 5.5 — 4.0 — 4.5 — 4.0 — 4.5 — ns
or LOW I/O
n, DS0
or DS7 to CP
t
H Hold Time HIGH 1.5 — 1.5 — 1.5 — 1.5 — 1.5 — 1.5 — ns
or LOW I/O
n, DS0
or DS7 to CP
t
W CP Pulse width 7.0 — 7.0 — 5.0 — 6.0 — 5.0 — 6.0 — ns
HIGH or LOW
t
W
MR
Pulse Width 7.0 — 7.0 — 5.0 — 6.0 — 5.0 — 6.0 — ns
LOW
t
REM Recovery Time 7.0 — 7.0 — 5.0 — 6.0 — 5.0 — 6.0 — ns
MR
to CP
NOTES: 2561 tbl 07
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
Min.
(2)
Max. Min.
(2)
Max. Min.
(2)
Max. Min.
(2)
Max. Min.
(2)
Max. Min.
(2)
Max. Unit
7.11 5
IDT54/74FCT299/A/C
FAST CMOS 8-INPUT UNIVERSAL SHIFT REGISTER MILITARY AND COMMERCIAL TEMPERATURE RANGES
TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS
VCC
500Ω
Pulse
Generator
VIN
D.U.T.
RT
VOUT
50pF
CL
500Ω
7.0V
SWITCH POSITION
Test Switch
Open Drain
Disable Low Closed
Enable Low
All Other Tests Open
DEFINITIONS: 2561 tbl 08
CL = Load capacitance: includes jig and probe capacitance.
T = Termination resistance: should be equal to ZOUT of the Pulse
R
Generator.
SET-UP, HOLD AND RELEASE TIMES PULSE WIDTH
DATA
INPUT
TIMING
INPUT
ASYNCHRONOUS CONTROL
PRESET
CLEAR
ETC.
SYNCHRONOUS CONTROL
PRESET
CLOCK ENABLE
CLEAR
ETC.
t
tSU
SU
t
REM
t
t
H
H
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
LOW-HIGH-LOW
HIGH-LOW-HIGH
PULSE
PULSE
1.5V
t
W
1.5V
SAME PHASE
INPUT TRANSITION
OUTPUT
OPPOSITE PHASE
INPUT TRANSITION
t
t
PLH
PLH
t
t
PHL
PHL
3V
1.5V
0V
V
OH
1.5V
V
OL
3V
1.5V
0V
ENABLE AND DISABLE TIMESPROPAGATION DELAY
ENABLE DISABLE
3V
CONTROL
INPUT
OUTPUT
NORMALLY
LOW
OUTPUT
NORMALLY
HIGH
t
PZL
SWITCH
CLOSED
t
PZH
SWITCH
OPEN
3.5V
1.5V
1.5V
0V
t
PHZ
t
PLZ
NOTES 2561 drw 04
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH.
2. Pulse Generator for All Pulses: Rate ≤ 1.0 MHz; Z
R ≤ 2.5ns.
t
1.5V
0V
3.5V
0.3V
V
OL
V
OH
0.3V
0V
O ≤ 50Ω; tF ≤ 2.5ns;
7.11 6
IDT54/74FCT299/A/C
FAST CMOS 8-INPUT UNIVERSAL SHIFT REGISTER MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDT
Temperature
Range
XX
FCT
Device Type
X
X
Package
X
Process
Blank
B
P
D
SO
L
E
299
299A
299C
54
74
Commercial
MIL-STD-883, Class B
Plastic DIP
CERDIP
Small Outline IC
Leadless Chip Carrier
CERPACK
8-Input Universal Shift Register
Fast 8-Input Universal Shift Register
Super Fast 8-Input Universal Shift Register
–55°C to +125°C
°C to +70°C
0
2561 drw 03
7.11 7
Loading...