Datasheet IDT74FCT273P, IDT74FCT273LB, IDT74FCT273L, IDT74FCT273EB, IDT74FCT273E Datasheet (Integrated Device Technology)



Integrated Device Technology, Inc.

FAST CMOS
OCTAL FLIP-FLOP
WITH MASTER RESET

IDT54/74FCT273
IDT54/74FCT273A
IDT54/74FCT273C

FEATURES:

• IDT54/74FCT273 equivalent to FAST speed;

• IDT54/74FCT273A 45% faster than FAST

• IDT54/74FCT273C 55% faster than FAST

• Equivalent to FAST output drive over full temperature
and voltage supply extremes

•IOL = 48mA (commercial) and 32mA (military)

• CMOS power levels (1mW typ. static)

• TTL input and output level compatible

• CMOS output level compatible

• Substantially lower input current levels than FAST
(5µA max.)

• Octal D flip-flop with Master Reset

• JEDEC standard pinout for DIP and LCC

• Product available in Radiation Tolerant and Radiation
Enhanced versions

• Military product compliant to MIL-STD-883, Class B

FUNCTIONAL BLOCK DIAGRAM

2

D

D

Q

CP

R

D

CP

0

D

D

Q

CP

R

D

1

D

D

Q

CP

R

D

DESCRIPTION:

The IDT54/74FCT273/A/C are octal D flip-flops built using
an advanced dual metal CMOS technology. The IDT54/
74FCT273/A/C have eight edge-triggered D-type flip-flops
with individual D inputs and O outputs. The common buffered
Clock (CP) and Master Reset (MR) inputs load and reset

(clear) all flip-flops simultaneously.

The register is fully edge-triggered. The state of each D
input, one set-up time before the LOW-to-HIGH clock
transition, is transferred to the corresponding flip-flop’s O
output.

All outputs will be forced LOW independently of Clock or
Data inputs by a LOW voltage level on the MR input. The
device is useful for applications where the true output only is
required and the Clock and Master Reset are common to all
storage elements.

3

D

D

Q

CP

R

D

4

D

D

Q

CP

R

D

5

D

D

Q

CP

R

D

6

D

D

Q

CP

R

D

7

D

D

Q

CP

R

D

MR

O

0

O

1

O

2

O

3

O

4

O

5

O

6

O

2558 drw 01

PIN CONFIGURATIONS

0

MR

O0
D0

D1

O1
O2
D2
D3
O3

GND

1
2
3
4

5
6
7
8
9

10

P20-1
D20-1

SO20-2

&

E20-1

20

Vcc

19

O7

18
17
16
15
14
13
12
11

D
D
O6
O5
D5
D4
O
CP

7
6

4

INDEX

D1

O1
O2
D2
D3

D

32

4
5
6
7
8

10 11 12 13

9

0

O

L20-2

O3

GND

DIP/SOIC/CERPACK

TOP VIEW

The IDT logo is a registered trademark of Integrated Device Technology, Inc.
FAST is a registered trademark of National Semiconductor Co.

LCC

TOP VIEW

MILITARY AND COMMERCIAL TEMPERATURE RANGES MAY 1992

1992 Integrated Device Technology, Inc. 7.10 DSC-4609/2

1

MR

20 19

CP

Vcc

4

O

7

O

18
17
16
15
14

4

D

D7
D6
O6
O5
D5

2558 drw 02

1

7

IDT54/74FCT273/A/C FAST CMOS
OCTAL D FLIP-FLOP WITH MASTER RESET MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN DESCRIPTION

Pin Names Description

N Data Input

D

MR

CP Clock Pulse Input (Active Rising Edge)

N Data Outputs

O

ABSOLUTE MAXIMUM RATINGS

Symbol Rating Commercial Military Unit

(2)

TERM

V

V

TERM

T

A Operating 0 to +70 –55 to +125 °C

T

BIAS Temperature –55 to +125 –65 to +135 °C

STG Storage –55 to +125 –65 to +150 ° C

T

P

T Power Dissipation 0.5 0.5 W

OUT DC Output Current 120 120 mA

I

NOTES: 2558 tbl 01

1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability. No terminal voltage
may exceed V

2. Input and V

3. Outputs and I/O terminals only.

Terminal Voltage –0.5 to +7.0 –0.5 to +7.0 V
with Respect
to GND

(3)

Terminal Voltage –0.5 to VCC –0.5 to VCC V
with Respect
to GND

Temperature

Under Bias

Temperature

CC terminals only.

Master Reset (Active LOW)

2558 tbl 05

(1)

CC by +0.5V unless otherwise noted.

FUNCTION TABLE

Inputs Outputs

Operating Mode

MR

MR

CP D

N ON

Reset (Clear) L X X L
Load “1” H ↑ hH
Load “0” H ↑ lL

NOTES: 2558 tbl 06

H = HIGH voltage level steady-state
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock

transition
L = LOW voltage level steady state
l = LOW voltage level one set-up time prior to the LOW-to-HIGH clock

transition
X = Don’t care
↑ = LOW-to-HIGH clock transition

CAPACITANCE (TA = +25°C, f = 1.0MHz)

Symbol Parameter

IN Input Capacitance VIN = 0V 6 10 pF

C

OUT Output Capacitance V OUT = 0V 8 12 pF

C

NOTE: 2558 tbl 02

1. This parameter is guaranteed by characterization data and not tested.

(1)

Conditions Typ. Max. Unit

7.10 2

IDT54/74FCT273/A/C FAST CMOS
OCTAL D FLIP-FLOP WITH MASTER RESET MILITARY AND COMMERCIAL TEMPERATURE RANGES

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE

Following Conditions Apply Unless Otherwise Specified: VLC = 0.2V; VHC = VCC – 0.2V
Commercial: TA = 0°C to +70°C, VCC = 5.0V ± 5%; Military: TA = –55°C to +125°C, VCC = 5.0V ± 10%

Symbol Parameter Test Conditions

IH Input HIGH Level Guaranteed Logic HIGH Level 2.0 — — V

V

IL Input LOW Level Guaranteed Logic LOW Level — — 0.8 V

V

IH Input HIGH Current VCC = Max. VI = VCC ——5µA

I

(1)

I = 2.7V — — 5

V

Min. Typ.

IIL Input LOW Current VI = 0.5V — — –5

VI = GND — — –5

IK Clamp Diode Voltage Vcc = Min., IN = –18mA — –0.7 –1.2 V

V

OS Short Circuit Current Vcc = Max.

I

OH Output HIGH Voltage Vcc = 3V, VIN = VLC or VHC, IOH = –32µAVHC VCC —V

V

Vcc = Min. I

IN = VIH or VIL IOH = –12mA MIL. 2.4 4.3 —

V

OL Output LOW Voltage Vcc = 3V, VIN = VLC or VHC, IOL = 300µA — GND VLC V

V

Vcc = Min. I

(3)

, VO = GND –60 –120 — mA

OH = –300µAVHC VCC —

OH = –15mA COM’L. 2.4 4.3 —

I

OL = 300µA — GND VLC

VIN = VIH or VIL IOL = 32mA MIL. — 0.3 0.5

OL = 48mA COM’L. — 0.3 0.5

I

NOTES: 2558 tbl 03

1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.

2. Typical values are at V

3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.

4. This parameter is guaranteed but not tested.

CC = 5.0V, +25°C ambient and maximum loading.

(2)

Max. Unit

(4)

(4)

(4)

7.10 3

IDT54/74FCT273/A/C FAST CMOS
OCTAL D FLIP-FLOP WITH MASTER RESET MILITARY AND COMMERCIAL TEMPERATURE RANGES

POWER SUPPLY CHARACTERISTICS

VLC = 0.2V; VHC = VCC – 0.2V

Symbol Parameter Test Conditions

I

CC Quiescent Power Supply Current Vcc = Max. — 0.2 1.5 mA

V

IN ≥ VHC; VIN ≤ VLC

∆ICC Quiescent Power Supply Current Vcc = Max. — 0.5 2.0 mA

TTL Inputs HIGH V

ICCD Dynamic Power Supply Current

IN = 3.4V

(4)

Vcc = Max. VIN ≥ VHC — 0.15 0.25 mA/MHz
Outputs Open V

MR

One Input Toggling
50% Duty Cycle

I

C Total Power Supply Current

(6)

Vcc = Max. VIN ≥ VHC — 1.7 4.0 mA
Outputs Open V
fCP = 10MHz (FCT)
50% Duty Cycle

MR

One Bit Toggling V
at f
50% Duty Cycle

Vcc = Max. V
Outputs Open VIN ≤ VLC
fCP = 10MHz (FCT)
50% Duty Cycle

MR

Eight Bits Toggling VIN = GND
f

i = 2.5MHz

50% Duty Cycle

(3)

= VCC

= V

CC VIN = 3.4V — 2.2 6.0

i = 5MHz

= V

CC VIN = 3.4V — 6.2 16.8

(1)

IN ≤ VLC

IN ≤ VLC

IN = GND

IN ≥ VHC — 4.0 7.8

Min. Typ.

(2)

Max. Unit

(5)

(5)

NOTES: 2558 tbl 04

1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.

2. Typical values are at V

3. Per TTL driven input (V

CC = 5.0V, +25°C ambient.

IN = 3.4V); all other inputs at VCC or GND.

4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.

5. Values for these conditions are examples of the I

C = IQUIESCENT + IINPUTS + IDYNAMIC

6. I

CC formula. These limits are guaranteed but not tested.

IC = ICC + ∆ICC DHNT + ICCD (fCP/2 + fiNi)

CC = Quiescent Current

I

CC = Power Supply Current for a TTL High Input (VIN = 3.4V)

∆I

H = Duty Cycle for TTL Inputs High

D
N

T = Number of TTL Inputs at DH

ICCD = Dynamic Current Caused by an Output Transition Pair (HLH or LHL)

CP = Clock Frequency for Register Devices (Zero for Non-Register Devices)

f

i = Input Frequency

f
N

i = Number of Inputs at fi

All currents are in milliamps and all frequencies are in megahertz.

7.10 4

IDT54/74FCT273/A/C FAST CMOS
OCTAL D FLIP-FLOP WITH MASTER RESET MILITARY AND COMMERCIAL TEMPERATURE RANGES

SWITCHING CHARACTERISTICS OVER OPERATING RANGE

IDT54/74FCT273 IDT54/74FCT273A IDT54/74FCT273C

Com’l. Mil. Com’l. Mil. Com’l. Mil.

Symbol Parameter Condition

PLH Propagation Delay CL = 50 pF 2.0 13.0 2.0 15.0 2.0 7.2 2.0 8.3 2.0 5.8 2.0 6.5 ns

t
t

PHL Clock to Output RL = 500Ω

t

PHL Propagation Delay 2.0 13.0 2.0 15.0 2.0 7.2 2.0 8.3 2.0 6.1 2.0 6.8 ns

MR

to Output

SU Set-up Time HIGH 3.0 — 3.5 — 2.0 — 2.0 — 2.0 — 2.0 — ns

t

(1)

or LOW Data to CP

H Hold Time HIGH 2.0 — 2.0 — 1.5 — 1.5 — 1.5 — 1.5 — ns

t

or LOW Data to CP

W Clock Pulse Width 7.0 — 7.0 — 6.0 — 6.0 — 6.0 — 6.0 — ns

t

HIGH or LOW

t

W

MR

Pulse Width 7.0 — 7.0 — 6.0 — 6.0 — 6.0 — 6.0 — ns

LOW

t

REM Recovery Time 4.0 — 5.0 — 2.0 — 2.5 — 2.0 — 2.5 — ns

MR

to CP

NOTES: 2558 tbl 07

1. See test circuit and waveforms.

2. Minimum limits are guaranteed but not tested on Propagation Delays.

Min.

(2)

Max. Min.

(2)

Max. Min.

(2)

Max. Min.

(2)

Max. Min.

(2)

Max. Min.

(2)

Max. Unit

7.10 5

IDT54/74FCT273/A/C FAST CMOS
OCTAL D FLIP-FLOP WITH MASTER RESET MILITARY AND COMMERCIAL TEMPERATURE RANGES

TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS

VCC

500Ω

Pulse

Generator

VIN

D.U.T.

RT

VOUT

50pF

CL

500Ω

7.0V

SWITCH POSITION

Test Switch

Open Drain

Disable Low Closed

Enable Low

All Other Tests Open

DEFINITIONS: 2558 tbl 08

CL = Load capacitance: includes jig and probe capacitance.

T = Termination resistance: should be equal to ZOUT of the Pulse

R

Generator.

SET-UP, HOLD AND RELEASE TIMES PULSE WIDTH

DATA

INPUT

TIMING

INPUT

ASYNCHRONOUS CONTROL

PRESET

CLEAR

ETC.

SYNCHRONOUS CONTROL

PRESET

CLOCK ENABLE

CLEAR

ETC.

t

tSU

SU

t

REM

t

t

H

H

3V

1.5V
0V

3V

1.5V
0V

3V

1.5V
0V

3V

1.5V
0V

LOW-HIGH-LOW

HIGH-LOW-HIGH

PULSE

PULSE

1.5V

t

W

1.5V

SAME PHASE

INPUT TRANSITION

OUTPUT

OPPOSITE PHASE

INPUT TRANSITION

t

t

PLH

PLH

t

t

PHL

PHL

3V

1.5V
0V

V

OH

1.5V
V

OL

3V

1.5V
0V

ENABLE AND DISABLE TIMESPROPAGATION DELAY

ENABLE DISABLE

3V

CONTROL

INPUT

OUTPUT

NORMALLY

LOW

OUTPUT

NORMALLY

HIGH

t

PZL

SWITCH
CLOSED

t

PZH

SWITCH
OPEN

3.5V

1.5V

1.5V
0V

t

PHZ

t

PLZ

NOTES 2558 drw 04

1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH.

2. Pulse Generator for All Pulses: Rate ≤ 1.0 MHz; Z
t

R ≤ 2.5ns.

1.5V
0V

3.5V

0.3V

V

OL

V

OH

0.3V
0V

O ≤ 50Ω; tF ≤ 2.5ns;

7.10 6

IDT54/74FCT273/A/C FAST CMOS
OCTAL D FLIP-FLOP WITH MASTER RESET MILITARY AND COMMERCIAL TEMPERATURE RANGES

ORDERING INFORMATION

XX

Temperature

Range

FCTIDT

X

Device

X

Package

X

Process

Type

Blank
B

P
D
SO
L
E

273
273A
273C

54
74

Commercial
MIL-STD-883, Class B

Plastic DIP
CERDIP
Small Outline IC
Leadless Chip Carrier
CERPACK

Octal D Flip-Flop w/Clear
Fast Octal D Flip-Flop w/Clear
Super Fast Octal D Flip-Flop w/Clear

–55°C to +125°C

°

C to +70°C

0

2558 drw 03

7.10 7