Datasheet IDT74FCT16H952CTPAB, IDT74FCT16H952CTPA, IDT74FCT16H952CTEB, IDT74FCT16H952CTE, IDT74FCT16H952BTPVB Datasheet (Integrated Device Technology)

Integrated Device Technology, Inc.

FEATURES:

• High-speed 16-bit bus exchange for interbus communica­tion in the following environments:
— Multi-way interleaving memory
— Multiplexed address and data busses

• Direct interface to R3051 family RISChipSet
— R3051 family of integrated RISController CPUs
— R3721 DRAM controller

• Data path for read and write operations

• Low noise 12mA TTL level outputs

• Bidirectional 3-bus architecture: X, Y, Z
— One CPU bus: X
— Two (interleaved or banked) memory busses:Y & Z
— Each bus can be independently latched

• Byte control on all three busses

• Source terminated outputs for low noise and undershoot
control

• 68-pin PLCC and 80-pin PQFP package

• High-performance CMOS technology.

16-BIT TRI-PORT
BUS EXCHANGER

COMMERCIAL TEMPERATURE RANGE AUGUST 1995

1995 Integrated Device Technology, Inc. 11.5 DSC-2046/6

IDT73720/A

DESCRIPTION:

The IDT73720/A Bus Exchanger is a high speed 16-bit bus
exchange device intended for inter-bus communication in
interleaved memory systems and high performance multi­plexed address and data busses.

The Bus Exchanger is responsible for interfacing between
the CPU A/D bus (CPU address/data bus) and multiple
memory data busses.

The 73720/A uses a three bus architecture (X, Y, Z), with
control signals suitable for simple transfer between the CPU
bus (X) and either memory bus (Y or Z). The Bus Exchanger
features independent read and write latches for each memory
bus, thus supporting a variety of memory strategies. All three
ports support byte enable to independently enable upper and
lower bytes.

RISChipSet, RISController, R305x, R3051, R3052 are trademarks and the IDT logo is a registered trademark of Integrated Device Technology, Inc.

FUNCTIONAL BLOCK DIAGRAM

NOTE:

1. Logic equations for bus control:
OEXU = T/R* .

OEU

*; OEXL = T/R* .

OEL

*; OEYU = T/R . PATH .

OEU

*

OEYL = T/R . PATH .

OEL

*; OEZU = T/R . PATH* .

OEU

*; OEZL = T/R . PATH* .

OEL

*

Figure 1. 73720 Block Diagram

1

Y-WRITE

LATCH

BUS CONTROL

PATH

LEXY

LEYX

(Even Path)

LEZX

16

8

8

OEYL

OEYU

88

M
U

X

16

OEXL

OEXU

16

OEXU

Y0:7

Y8:15

X0:7

X8:15

Y-READ

LATCH

16

88

16

OEXL

OEYU

OEYL

OEZU

OEZL

Z-READ

LATCH

88

16

T/R
OEU
OEL

Z-WRITE

LATCH

LEXZ

(Odd Path)

16

8

8

OEZL

OEZU

88

Z0:7

Z8:15

16

2527 drw 01

8

8

IDT73720/A 16-BIT TRI-PORT BUS EXCHANGER COMMERCIAL TEMPERATURE RANGE

11.5 2

PIN CONFIGURATIONS

PLCC

TOP VIEW

PQFP

TOP VIEW

10
11
12
13
14
15
16
17
18
19
20

21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

41

42

43

60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44

8

7

6

5

4

3

2

1

68 67 66 65 64 63 62 61

PQ80-1

Pin 1

Designator

GND

VCC

X7

X6X5X4

X3X2X1

X0

Z15

Z14

Z13

Z12

Z11

Z10

GND

GND

OEL

Z9
Z8
Z7
Z6
Z5
Z4

Z3
Z2
Z1
Z0

GND
VCC
LEXZ

LEXY
T/R

2527 drw 03

GND

X8
X9

X13

X15

GND

X10
X11
X12

X14

VCC

PATH

LEYX
LEZX

Y0
Y1

OEU

NC
NC

GND

9

GND

Y2

Y3

Y4Y5Y6Y7Y8

VCC

Y9

Y10

Y11

Y12

Y13

Y14

Y15

NC

NC

GND

76 75 74 73 72 71 70 6980 79 78 77

GND

NC
NC

GND

NC

NC

GND

10
11
12
13
14
15
16
17
18
19

20
21

22
23
24
25

26

27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43

60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44

9 8 7 6 5 4 3 2 1 686766 6564636261

J68-1

Pin 1

Designator

GND

VCC

X7

X6X5X4X3X2X1X0

Z15

Z14

Z13

Z12

Z11

Z10

GND

GND

Y2

Y3

Y4

Y5

Y6

Y7

Y8

GND

VCC

Y9

Y10

Y11

Y12

Y13

Y14

Y15

OEL

Z9

Z8
Z7
Z6

Z5
Z4

Z3

Z2

Z1
Z0
GND

VCC
LEXZ

LEXY

GND

T/R

GND

X8
X9

X13

X15

GND

X10
X11
X12

X14

VCC

PATH

LEYX
LEZX

Y0
Y1

OEU

2527 drw 02

IDT73720 /A16-BIT TRI-PORT BUS EXCHANGER COMMERCIAL TEMPERATURE RANGE

11.5 3

PIN DESCRIPTION

Signal I/O Description

X(0:15) I/O Bidirectional Data Port X. Usually connected to the CPU's A/D (Address/Data) bus.
Y(0:15) I/O Bidirectional Data port Y. Connected to the even path or even bank of memory.
Z(0:15) I/O Bidirectional Data port Z. Connected to the odd path or odd bank of memory.

LEXY I Latch Enable input for Y-Write Latch. The Y-Write Latch is open when LEXY is HIGH. Data from the X-port

(CPU) is latched on the HIGH-to-LOW transition of LEXY

LEXZ I Latch Enable input for Z-Write Latch. The Z-Write Latch is open when LEXZ is HIGH. Data from the X-port

(CPU) is latched on the HIGH-to-LOW transition of LEXZ.

LEYX I Latch Enable input for the Y-Read Latch. The Y-Read Latch is open when LEYX is HIGH. Data from the even

path Y is latched on the HIGH-to-LOW transition of LEYX.

LEZX I Latch Enable input for the Z-Read Latch. The Z-Read Latch is open when LEZX is HIGH. Data from the odd

path Z is latched on the HIGH-to-LOW transition of LEZX

PATH I Even/Odd Path Selection. When high, PATH enables data transfer between the X-Port and the Y-port (even

path). When LOW, PATH enables data transfer between the X-Port and the Z-Port (odd path).

T/

R

I Transmit/Receive Data. When high, Port X is an input Port and either Port Y or Z is an output Port. When LOW,

Port X is an output Port while Ports Y & Z are input Ports

OEU

I Output Enable for Upper byte. When LOW, the Upper byte of data is transfered to the port specified by PATH in

the direction specified by T/R .

OEL

I Output Enable for Lower byte. When LOW, the Lower byte of data is transfered to the port specified by PATH in

the direction specified by T/R .

2527 tbl 02

CAPACITANCE (TA = +25°C, F = 1.0MHZ)

Symbol Parameter

(1)

Conditions Max. Unit

C

IN Input Capacitance VIN = 0V 8 pF

C

OUT Output Capacitance VOUT = 0V 12 pF

NOTE: 2527 tbl 04

1. This parameter is guaranteed by device characterization, but is not prod­uction tested.

ABSOLUTE MAXIMUM RATINGS

(1)

Symbol Rating Com’l. Mil. Unit

V

TERM Terminal Voltage –0.5 to +7.0 –0.5 to +7.0 V

with Respect
to GND

TA Operating 0 to +70 –55 to +125 °C

Temperature

T

BIAS Temperature –55 to +125 –65 to +135 °C

Under Bias

T

STG Storage –55 to +125 –65 to +125 °C

Temperature

P

T Power 1.0 1.0 W

Dissipation

I

OUT DC Output 50 50 mA

Current

NOTE: 2527 tbl 03

1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.

TRUTH TABLE

Path T/

RROEU

OEU

OEL

OEL

Functionality

LLLLZ→X (16-bits)–Read Z

(1)

LHLLX→Z (16 bits)–Write Z

(1)

HLLLY→X (16-bits)–Read Y

(2)

H H L L X→Y (16 bits)–Write Y

(2)

X X H H All output buffers are

disabled

X X H L Transfer of lower 8 bits

(0:7) as per PATH & T/

R

X X L H Transfer of upper 8 bits

(8:15) as per PATH & T/

R

NOTES: 2527 tbl 01

1. For Z→X and X→Z transfers, Y-port output buffers are tristated.

2. For Y→X and X→Y transfers, Z-port output buffers are tristated.

IDT73720/A 16-BIT TRI-PORT BUS EXCHANGER COMMERCIAL TEMPERATURE RANGE

11.5 4

ARCHITECTURE OVERVIEW

The Bus Exchanger is used to service both read and write

operations between the CPU and the dual memory busses. It
includes independent data path elements for reads from and
writes to each of the memory banks (Y and Z). Data flow
control is managed by a simple set of control signals, analo­gous to a simple transceiver. In short, the Bus Exchanger
allows bidirectional communication between ports X and Y
and ports X and Z as illustrated in figure 1.

The data path elements for each port include:

Read Latch: Each of the memory ports Y and Z contains a
transparent latch to capture the contents of the memory bus.
Each latch features an independent latch enable.
Write Latch: Each memory port Y and Z contains an indepen­dent latch to capture data from the CPU bus during writes.
Each memory port write latch features an independent latch
enable, allowing write data to be directed to a specific memory
port without disrupting the other memory port.

Data Flow Control Signals

T/

RR (Transmit/

Receive

). This signal controls the direction
of data transfer. A transmit is used for CPU writes, and a
receive is used for read operations.

OEU

OEU

,

OEL

OEL

are the output enable control signals to select

upper or lower bytes of all three ports.

Path: The path control signal is used to select between the
even memory path Y and the odd memory path Z during read
or write operations. Path selects the memory port to be
connected to the CPU bus (X-port), and is independent of the
latch enable signals. Thus, it is possible to transfer data from
one memory port to the CPU bus (X) while capturing data from
the other memory port.

MEMORY READ OPERATIONS

Latch Mode

In this mode the read operation consists of two stages.
During the first stage, the data present at the memory port is
captured by the read latch for that memory port. During a
subsequent stage, data is brought from a selected memory
port to the CPU A/D port X by using output enable control.

The read operation is selected by driving T/R LOW. The
read is managed using the Path input to select the memory
port (Y or Z); the LEYX/LEZX enable the data capture into the
corresponding Read Latch.

In this way, memory interleaving can be performed. While
data from one bank is output onto the CPU bus, data on the
other bank is captured in the other memory port. In the next
cycle, the Path input is changed, enabling the next data

element onto the CPU bus, while the first bank is presented
with a new data element.

Transparent Mode

The Bus Exchanger may be used as a data transceiver by

leaving all latches open or transparent.

Memory Write Operations

Memory write operations also consist of two distinct stages.
During one stage, the write data is captured into the selected
memory port write latch. During a later stage, the memory is
presented on the memory port bus

The write operation is selected by driving T/R HIGH. Writes
are thus performed using the Path input to select the memory
port (Y or Z). The LEXY/LEXZ capture data in the correspond­ing Write Latch.

Note that it is possible to utilize the bus exchanger’s write
resources as an additional write buffer, if desired; the CPU
A/D bus can be freed up once the data has been captured by
the Bus Exchanger.

APPLICATIONS

Use as Part of the R3051 Family ChipSet

Figure 2 shows the use of the Bus Exchanger in a typical

R3051 based system.

In write transactions, the R3051 drives data on the CPU
bus. The latch enables are held open through the entire write;
thus, the bus exchanger is used like a transceiver. The
appropriate LEXY/LEXZ signal is derived from ALE (Logic
LOW- indicating that the processor is driving data) and the low
order address bit. The rising edge of Wr from the CPU, ends
the write operation.

During read transactions, the memory system is respon­sible for generating the input control signals to cause data to
be captured at the memory ports. The memory controller is
also responsible for acknowledging back to the CPU that the
data is available, and causing the appropriate path to be
selected.

The R3721 DRAM controller for the R3051 family uses the
transparent latches of the read ports. The R3721 directly
controls the inputs of the bus exchanger, during both reads
and writes. Consult the R3721 data sheet for more informa­tion on these control signals.

Use in a general 32-bit System

Figures 3 and 4 illustrate the use of the Bus Exchanger in
a 32-bit microprocessor based system. Note the reduced pin
count achieved with the Bus Exchanger.

IDT73720 /A16-BIT TRI-PORT BUS EXCHANGER COMMERCIAL TEMPERATURE RANGE

11.5 5

CPU

4 x (74FCT373)

2 x (73720)

DRAM 1 DRAM 2

Address

32

Data Bus Chip Count = 2 Pin Count = 136

4 x (74FCT373)

Address

Data Bus Chip Count = 8 Pin Count = 192

4 x (74FCT543) 4 x (74FCT543)

CPU

DRAM 1 DRAM 2

2527 drw 06

32

CPU

4 x (74FCT373)

2 x (73720)

DRAM 1 DRAM 2

Address

32

Data Bus Chip Count = 2 Pin Count = 136

4 x (74FCT373)

Address

Data Bus Chip Count = 8 Pin Count = 160

4 x (74FCT245) 4 x (74FCT245)

CPU

DRAM 1 DRAM 2

2527 drw 05

32

Figure 3. CPU System with Transparent Data Path

(2-way Interleaving)

Figure 4. CPU System with Latched Data Path

(2-way Interleaving)

Clk2xIn

IDT R3051 FAMILY

RISController

ADDRESS/DATA

CONTROL

R305x

LOCAL BUS

2527 drw 04

IDT79R3721

DRAM

CONTROLLER

IDT73720

BUS EXCHANGER

(2)

DRAM DRAM

Figure 2. Bus Exchanger Used in R3051 Family System

IDT73720/A 16-BIT TRI-PORT BUS EXCHANGER COMMERCIAL TEMPERATURE RANGE

11.5 6

NOTES:

1. For conditions shown as max. or min., use appropriate V

CC value.

2. Typical values are at V

CC = 5.0V, +25°C ambient.

3. Not more than one output should be shorted at a time. Duration of the short circuit test should not exceed one second.

4. Per TTL driven input (V

IN = 3.4V); all other inputs at VCC or GND.

5. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.

6. I

C = IQUIESCENT + IINPUTS + IDYNAMIC

IC = ICC + ∆ICC DHNT + ICCD (fCP/2 + fiNi)
I

CC = Quiescent Current

∆I

CC = Power Supply Current for a TTL High Input (VIN = 3.4V)

D

H = Duty Cycle for TTL Inputs High

N

T = Number of TTL Inputs at DH

ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
f

CP = Clock Frequency for Register Devices (Zero for Non-Register Devices)

f

i = Input Frequency

N

i = Number of Inputs at fi

All currents are in milliamps and all frequencies are in megaherz.

DC ELECTRICAL CHARACTERISTICS (VCC = 5.0V ± 5%, TA = 0°C to +70°C)

Symbol Parameter Test Conditions

(1)

Min. Typ.

(2)

Max. Unit

V

IH Input HIGH Level 2.0 — — V

V

IL Input LOW Level — — 0.8 V

I

IH Input HIGH Current VCC = Max., VIH = 2.7V Inputs only ——5.0 µA

I/O pins ——5.0

I

IL Input LOW Current VCC = Max., VIL = 0.5V Inputs only — — –5.0 µA

I/O pins — — –5.0

V

IK Clamp Diode Voltage VCC = Min., IIN = –18mA — –0.7 –1.2 V

I

OS

(3)

Short Circuit Current VCC = Max., VO = GND –60 — –200 mA

V

OH Output HIGH Voltage VCC = Min., VIN = VIH or VIL, IOH = –12mA 2.4 3.3 — V

V

OL Output LOW Voltage VCC = Min., VIN = VIH or VIL, IOL = 12mA — 0.3 0.5 V

V

H Input Hysteresis VCC = 5V — 200 — mV

All inputs

I

CC Quiescent Power VCC = Max. — 0.2 1.5 mA

Supply Current V

IN = GND or VCC

∆ICC Quiescent Power VCC = Max. — 0.5 2.0 mA/

Supply Current V

IN =3.4 V

(4)

Input

I

CCD Dynamic Power V CC = Max. — 0.25 0.5 mA/

Supply Current

(5)

VIN = VCC or GND MHz
Outputs Disabled

OE

= V

CC

One Input Toggling
50 % Duty Cycle

I

C Total Power Supply VCC = Max. — 2.7 6.5 mA

Current

(6)

VIN = VCC or GND
Outputs Disabled
50 % Duty Cycle

OE

= V

CC

fi = 10MHz
One Bit Toggling

AC TEST CONDITIONS

Input Pulse Levels GND to 3.0V
Input Rise/Fall Times 5ns
Input Timing Reference Levels 1.5V
Output Reference Levels 1.5V
Output Load See Figure 5

2527 tbl 06

2527 tbl 05

IDT73720 /A16-BIT TRI-PORT BUS EXCHANGER COMMERCIAL TEMPERATURE RANGE

11.5 7

SWITCH POSITION

Test Switch

Disable LOW Closed

Enable LOW

All Other Tests Open

DEFINITIONS: 2527 tbl 08

CL = Load capacitance: includes jig and probe capacitance.
R

T = Termination resistance: should be equal to ZOUT of the Pulse

Generator.

TEST CIRCUITS AND WAVEFORMS

Figure 5. Test Circuit for all outputs

Pulse

Generator

R T

D.U.T.

VCC

VIN

C L

V OUT

50pF

500Ω

500Ω

7.0V

2527 drw 07

AC ELECTRICAL CHARACTERISTICS (VCC = 5.0V ± 5%, TA = 0° to +70°C)

73720A 73720

Symbol Parameter Test Conditions

(1)

Min.

(2)

Max. Min.

(2)

Max. Units

t

PLH X to Y & X to Z Latches enabled CL = 50pF 2.0 6.0 2.0 7.5 ns

t

PHL RL = 500 Ohms

t

PLH Y to X & Z to X Latches enabled 2.0 6.0 2.0 7.5 ns

t

PHL

tPLH Latch Enable to Y & Z Port LEXY to Y 2.0 7.0 2.0 8.5 ns
t

PHL LEXZ to Z

t

PLH Latch Enable to X LEYX to X 2.0 7.0 2.0 8.5 ns

t

PHL LEZX to X

t

PLH Path to X Port Propagation Delay 2.0 7.0 2.0 8.5 ns

t

PHL

tHZ Y & Z Port Disable Time (T/R, PATH,

OEU, OEL

)

(3)

2.0 8.5 2.0 9.5 ns

t

LZ

tZH Y & Z Port Enable Time (T/R, PATH,

OEU, OEL

)

(3)

2.0 9.5 2.0 10.5 ns

t

ZL

tHZ X-Port DisableTime (T/R,

OEU, OEL

)

(3)

2.0 8.5 2.0 9.5 ns

t

LZ

tZH X-Port Enable Time (T/R,

OEU, OEL

)

(3)

2.0 9.5 2.0 10.5 ns

t

ZL

tSU Port to LE Set-up time 2.0 — 2.0 — ns
t

H Port to LE Hold time 1.5 — 1.5 — ns

t

W LE Pulse Width, HIGH or LOW

(2)

3—4 —ns

NOTES: 2527 tbl 07

1. All timings are referenced to 1.5 V.

2. Minimum Delay Times, Enable Times, Disable Times and Pulse Width are guaranteed by design, but not tested.

3. Bus turnaround times are guaranteed by design, but not tested. (T/R enable/disable times).

IDT73720/A 16-BIT TRI-PORT BUS EXCHANGER COMMERCIAL TEMPERATURE RANGE

11.5 8

SET-UP, HOLD AND RELEASE TIMES PULSE WIDTH

HIGH-LOW-HIGH

PULSE

LOW-HIGH-LOW

PULSE

t

W

1.5V

1.5V

2527 drw 09

DATA

INPUT

TIMING

INPUT

ASYNCHRONOUS CONTROL

PRESET

CLEAR

ETC.

SYNCHRONOUS CONTROL

3V

1.5V
0V

tSU tH

tREM

3V

1.5V

0V

3V

1.5V

0V

3V

1.5V
0V

2527 drw 08

tSU

tH

ENABLE AND DISABLE TIMES

NOTES:

1. Diagram shown for input Control Enable-LOW and input Control Disable­HIGH.

2. Pulse Generator for All Pulses: Rate ≤ 1.0 MHz; ZO ≤ 50Ω; tF ≤ 2.5ns; t

R

≤ 2.5ns.

PROPAGATION DELAY

CONTROL

INPUT

3V

1.5V
0V

3.5V

0V

OUTPUT

NORMALLY

LOW

OUTPUT

NORMALLY

HIGH

SWITCH
CLOSED

SWITCH
OPEN

V

OL

0.3V

0.3V

t

PLZ

t

PZL

t

PZH

t

PHZ

3.5V

0V

1.5V

1.5V

ENABLE DISABLE

2527 drw 11

V

OH

SAME PHASE

INPUT TRANSITION

3V

1.5V
0V

1.5V

V

OH

t

PLH

OUTPUT

OPPOSITE PHASE

INPUT TRANSITION

3V

1.5V
0V

2527 drw 10

t

PLH

t

PLH

t

PLH

V

OL

ORDERING INFORMATION

X

Package

X

Process/

Temperature

Range

Blank

Commercial Temperature Range

68-Pin PLCC
80-Pin PQFP

XXXXX

Device

Type

73720

Bus Exchanger

IDT

2527 drw 12

X

J
PQF

Blank
A

Standard Speed
High Speed

Speed