Datasheet IDT74FCT16373ETPF, IDT74FCT16373ETPA, IDT74FCT16373ETE, IDT74FCT16373CTPVB, IDT74FCT16373CTPV Datasheet (Integrated Device Technology)

MILITARY AND COMMERCIAL TEMPERATURE RANGES AUGUST 1996

1996 Integrated Device Technology, Inc. 5.7 DSC-4229/9

1

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

Integrated Device Technology, Inc.

DESCRIPTION:

The FCT16373T/AT/CT/ET and FCT162373T/AT/CT/ET
16-bit transparent D-type latches are built using advanced
dual metal CMOS technology. These high-speed, low-power
latches are ideal for temporary storage of data. They can be
used for implementing memory address latches, I/O ports,
and bus drivers. The Output Enable and Latch Enable controls
are organized to operate each device as two 8-bit latches, or
one 16-bit latch. Flow-through organization of signal pins
simplifies layout. All inputs are designed with hysteresis for
improved noise margin.

The FCT16373T/AT/CT/ET are ideally suited for driving
high-capacitance loads and low-impedance backplanes. The
output buffers are designed with power off disable capability
to allow "live insertion" of boards when used as backplane
drivers.

The FCT162373T/AT/CT/ET have balanced output drive
with current limiting resistors. This offers low ground bounce,
minimal undershoot, and controlled output fall times– reduc­ing the need for external series terminating resistors. The
FCT162373T/AT/CT/ET are plug-in replacements for the
FCT16373T/AT/CT/ET and ABT16373 for on-board interface
applications.

FAST CMOS 16-BIT
TRANSPARENT
LATCHES

IDT54/74FCT16373T/AT/CT/ET

IDT54/74FCT162373T/AT/CT/ET

FUNCTIONAL BLOCK DIAGRAM

1OE

1LE

1O1

1D1

2543 drw 01

TO 7 OTHER CHANNELS

C

D

2O1

2

OE

2

LE

2D1

2543 drw 02

TO 7 OTHER CHANNELS

C

D

FEATURES:

• Common features:

– 0.5 MICRON CMOS Technology

– High-speed, low-power CMOS replacement for

ABT functions

– Typical tSK(o) (Output Skew) < 250ps
– Low input and output leakage ≤1µA (max.)

– ESD > 2000V per MIL-STD-883, Method 3015;

> 200V using machine model (C = 200pF, R = 0)

– Packages include 25 mil pitch SSOP, 19.6 mil pitch

TSSOP,15.7 mil pitch TVSOP and 25 mil pitch Cerpack
– Extended commercial range of -40°C to +85°C
–V

CC = 5V ±10%

• Features for FCT16373T/AT/CT/ET:

– High drive outputs (-32mA IOH, 64mA IOL)
– Power off disable outputs permit “live insertion”
– Typical VOLP (Output Ground Bounce) < 1.0V at

VCC = 5V, TA = 25°C

• Features for FCT162373T/AT/CT/ET:

– Balanced Output Drivers: ±24mA (commercial),

±16mA (military)

– Reduced system switching noise
– Typical VOLP (Output Ground Bounce) < 0.6V at

VCC = 5V,TA = 25°C

5.7 2

IDT54/74FCT16373T/AT/CT/ET, 162373T/AT/CT/ET
FAST CMOS 16-BIT TRANSPARENT LATCHES MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN CONFIGURATIONS

1O1

GND

1O3

VCC

1

OE

GND

2O2

GND

V

CC

GND

1O2

1

O4

1

O5

1

O6

1

O7

1

O8

2

O1

2

O3

2

O4

2

O5

2

O7

2

O8

2

O6

2OE

1LE
1D1

1

D2

GND

1D3

1

D4

VCC

1

D5

1

D6

1

D7

1

D8

2

D1

2

D2

2

D3

2

D4

VCC

2

D5

2

D7

2

D8

2

D6

2

LE

GND

GND

GND

39

29

30

31

32

33

34

35

36

37

38

25

26

27

28

48
47

41

42

43

44

45

46

40

1
2

3
4
5
6
7
8
9
10

12
13
14
15
16
17
18
19
20

11

21
22
23
24

2543 drw 04

CERPACK
TOP VIEW

E48-1

1O1

GND

1O3

VCC

1

OE

GND

2O2

GND

V

CC

GND

1O2

1

O4

1

O5

1

O6

1

O7

1

O8

2

O1

2

O3

2

O4

2

O5

2

O7

2

O8

2

O6

2OE

1LE
1D1

1

D2

GND

1D3

1

D4

VCC

1

D5

1

D6

1

D7

1

D8

2

D1

2

D2

2

D3

2

D4

VCC

2

D5

2

D7

2

D8

2

D6

2

LE

GND

GND

GND

2543 drw 03

39

29

30

31

32

33

34

35

36

37

38

25

26

27

28

48
47

41

42

43

44

45

46

40

1
2
3
4
5
6
7
8
9
10

12
13
14
15
16
17
18
19
20

11

21
22
23
24

SSOP/

TSSOP/TVSOP

TOP VIEW

SO48-1
SO48-2
SO48-3

IDT54/74FCT16373T/AT/CT/ET, 162373T/AT/CT/ET
FAST CMOS 16-BIT TRANSPARENT LATCHES MILITARY AND COMMERCIAL TEMPERATURE RANGES

5.7 3

NOTE:

2543 tbl 02

1. H = HIGH voltage level
L = LOW voltage level
X = Don’t care
Z = High-impedance

PIN DESCRIPTION

2543 tbl 01

ABSOLUTE MAXIMUM RATINGS

(1)

FUNCTION TABLE

(1)

CAPACITANCE (TA = +25°C, f = 1.0MHz)

NOTE:

1. This parameter is measured at characterization but not tested.

2543 lnk 04

Symbol Parameter

(1)

Conditions Typ. Max. Unit

CIN Input

Capacitance

VIN = 0V 3.5 6.0 pF

COUT Output

Capacitance

VOUT = 0V 3.5 8.0 pF

Pin Names Description

xDx Data Inputs
xLE Latch Enable Input (Active HIGH)
x

OE

Output Enable Input (Active LOW)

xOx 3-State Outputs

Inputs Outputs

xDx xLE x

OE

OE

xOx

HHLH

LHLL

XXHZ

Symbol Description Max. Unit

VTERM

(2)

Terminal Voltage with Respect to
GND

–0.5 to +7.0 V

VTERM

(3)

Terminal Voltage with Respect to
GND

–0.5 to

V

CC +0.5

V

TSTG Storage Temperature –65 to +150 °C
IOUT DC Output Current –60 to +120 mA

NOTES:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT­INGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is
not

implied. Exposure to absolute maximum rating conditions for

extended periods may affect reliability.

2. All device terminals except FCT162XXXT Output and I/O terminals.

3. Output and I/O terminals for FCT162XXXT.

2543 lnk 03

5.7 4

IDT54/74FCT16373T/AT/CT/ET, 162373T/AT/CT/ET
FAST CMOS 16-BIT TRANSPARENT LATCHES MILITARY AND COMMERCIAL TEMPERATURE RANGES

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE

Following Conditions Apply Unless Otherwise Specified:
Commercial: T

A = –40°C to +85°C, VCC = 5.0V ± 10%; Military: TA = –55°C to +125°C, VCC

= 5.0V ± 10%

Symbol Parameter Test Conditions

(1)

Min. Typ.

(2)

Max. Unit

VIH Input HIGH Level Guaranteed Logic HIGH Level 2.0 — — V
VIL Input LOW Level Guaranteed Logic LOW Level — — 0.8 V
II H Input HIGH Current (Input pins)

(5)

VCC = Max. VI = VCC — — ±1 µA

Input HIGH Current (I/O pins)

(5)

— — ±1

II L Input LOW Current (Input pins)

(5)

VI = GND — — ±1

Input LOW Current (I/O pins)

(5)

— — ±1
IOZH High Impedance Output Current VCC = Max. VO = 2.7V — — ±1 µA
IOZL (3-State Output pins)

(5)

VO = 0.5V — — ±1
VIK Clamp Diode Voltage VCC = Min., IIN = –18mA — –0.7 –1.2 V
IOS Short Circuit Current VCC = Max., VO = GND

(3)

–80 –140 –225 mA
VH Input Hysteresis — — 100 — mV
ICCL

ICCH
ICCZ

Quiescent Power Supply Current VCC = Max., VIN = GND or VCC — 5 500 µA

2543 lnk 05

2543 lnk 07

NOTES:

1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.

2. Typical values are at Vcc = 5.0V, +25°C ambient.

3. Not more than one output should be tested at one time. Duration of the test should not exceed one second.

4. Duration of the condition can not exceed one second.

5. The test limit for this parameter is ± 5µA at T

A = –55°C.

Symbol Parameter Test Conditions

(1)

Min. Typ.

(2)

Max. Unit

I

ODL

Output LOW Current VCC = 5V, V

IN

= V

IH or VIL, VOUT

= 1.5V

(3)

60 115 200 mA

I

ODH

Output HIGH Current VCC = 5V, V

IN

= V

IH

or V

IL,

V

OUT

= 1.5V

(3)

–60 –115 –200 mA

V

OH

Output HIGH Voltage VCC = Min.

V

IN

= V

IH

or V

IL

IOH = –16mA MIL.
I

OH

= –24mA COM'L.

2.4 3.3 — V

V

OL

Output LOW Voltage VCC = Min.

V

IN

= V

IH

or V

IL

IOL = 16mA MIL.
I

OL

= 24mA COM'L.

— 0.3 0.55 V

Symbol Parameter Test Conditions

(1)

Min. Typ.

(2)

Max. Unit

I

O

Output Drive Current VCC = Max., VO = 2.5V

(3)

–50

—–

180 mA

V

OH

Output HIGH Voltage VCC = Min. IOH = –3mA 2.5 3.5 — V

VIN = V

IH

or V

IL

IOH = –12mA MIL.
I

OH

= –15mA COM'L.

2.4 3.5 — V

IOH = –24mA MIL.
I

OH

= –32mA COM'L.

(4)

2.0 3.0 — V

V

OL

Output LOW Voltage VCC = Min.

V

IN

= V

IH

or V

IL

I

OL

= 48mA MIL.

I

OL

= 64mA COM'L.

— 0.2 0.55 V

I

OFF

Input/Output Power Off Leakage

(5)

VCC = 0V, V

IN

or V

O

≤ 4.5V — —

±

1

µ

A

OUTPUT DRIVE CHARACTERISTICS FOR FCT16373T

2543 lnk 06

OUTPUT DRIVE CHARACTERISTICS FOR FCT162373T

IDT54/74FCT16373T/AT/CT/ET, 162373T/AT/CT/ET
FAST CMOS 16-BIT TRANSPARENT LATCHES MILITARY AND COMMERCIAL TEMPERATURE RANGES

5.7 5

POWER SUPPLY CHARACTERISTICS

2543 tbl 08

NOTES:

1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.

2. Typical values are at V

CC = 5.0V, +25°C ambient.

3. Per TTL driven input (V

IN = 3.4V). All other inputs at VCC or GND.

4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.

5. Values for these conditions are examples of the I

CC formula. These limits are guaranteed but not tested.

6. I

C = IQUIESCENT + IINPUTS + IDYNAMIC

IC = ICC + ∆ICC DHNT + ICCD (fCPNCP/2 + fiNi)
I

CC = Quiescent Current (ICCL, ICCH and ICCZ)

∆I

CC = Power Supply Current for a TTL High Input (VIN = 3.4V)

D

H = Duty Cycle for TTL Inputs High

N

T = Number of TTL Inputs at DH

ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
f

CP = Clock Frequency for Register Devices (Zero for Non-Register Devices)

N

CP = Number of Clock Inputs at fCP

fi = Input Frequency
N

i = Number of Inputs at fi

Symbol Parameter Test Conditions

(1)

Min. Typ.

(2)

Max. Unit

∆ICC Quiescent Power Supply Current

TTL Inputs HIGH

VCC = Max.
V

IN = 3.4V

(3)

— 0.5 1.5 mA

ICCD Dynamic Power Supply

Current

(4)

VCC = Max.
Outputs Open
xOE = GND
One Input Toggling
50% Duty Cycle

V

IN = VCC

V

IN = GND

— 60 100 µA/

MHz

IC Total Power Supply Current

(6)

VCC = Max.
Outputs Open
fi =10MHz

V

IN = VCC

V

IN = GND

— 0.6 1.5 mA

50% Duty Cycle
xOE = GND
xLE

= VCC

One Bit Toggling

V

IN = 3.4V

V

IN = GND

— 0.9 2.3

VCC = Max.
Outputs Open
fi = 2.5MHz

V

IN = VCC

V

IN = GND

— 2.4 4.5

(5)

50% Duty Cycle
xOE = GND
xLE = V

CC

Sixteen Bits Toggling

V

IN = 3.4V

V

IN = GND

— 6.4 16.5

(5)

5.7 6

IDT54/74FCT16373T/AT/CT/ET, 162373T/AT/CT/ET
FAST CMOS 16-BIT TRANSPARENT LATCHES MILITARY AND COMMERCIAL TEMPERATURE RANGES

SWITCHING CHARACTERISTICS OVER OPERATING RANGE

FCT16373T/162373T FCT16373AT/162373AT

Com'l. Mil. Com'l. Mil.

Symbol Parameter Condition

(1)

Min.

(2)

Max. Min.

(2)

Max. Min.

(2)

Max. Min.

(2)

Max. Unit

tPLH
tPHL

Propagation Delay
xDx to xOx

CL = 50pF

R

L = 500Ω

1.5 8.0 1.5 8.5 1.5 5.2 1.5 5.6 ns

tPLH
tPHL

Propagation Delay
xLE to xOx

2.0 13.0 2.0 15.0 2.0 8.5 2.0 9.8 ns

tPZH
tPZL

Output Enable Time 1.5 12.0 1.5 13.5 1.5 6.5 1.5 7.5 ns

tPHZ
tPLZ

Output Disable Time 1.5 7.5 1.5 10.0 1.5 5.5 1.5 6.5 ns

tSU Set-up Time HIGH or LOW,

xDx to xLE

2.0 — 2.0 — 2.0 — 2.0 — ns

tH Hold Time HIGH or LOW,

xDx to xLE

1.5 — 1.5 — 1.5 — 1.5 — ns

tW xLE Pulse Width HIGH 6.0 — 6.0 — 5.0 — 6.0 — ns
tSK(o) Output Skew

(3)

— 0.5 — 0.5 — 0.5 — 0.5 ns

2543 tbl 09

FCT16373CT/162373CT FCT16373ET/162373ET

Com'l. Mil. Com'l. Mil.

Symbol Parameter Condition

(1)

Min.

(2)

Max. Min.

(2)

Max. Min.

(2)

Max. Min.

(2)

Max. Unit

tPLH
tPHL

Propagation Delay
xDx to xOx

CL = 50pF

R

L = 500Ω

1.5 4.2 1.5 5.1 1.5 3.4 — — ns

tPLH
tPHL

Propagation Delay
xLE to xOx

2.0 5.5 2.0 8.0 1.5 3.7 — — ns

tPZH
tPZL

Output Enable Time 1.5 5.5 1.5 6.3 1.5 4.4 — — ns

tPHZ
tPLZ

Output Disable Time 1.5 5.0 1.5 5.9 1.5 3.6 — — ns

tSU Set-up Time HIGH or LOW,

xDx to xLE

2.0 — 2.0 — 1.0 — — — ns

tH Hold Time HIGH or LOW,

xDx to xLE

1.5 — 1.5 — 1.0 — — — ns

tW xLE Pulse Width HIGH 5.0 — 6.0 — 3.0

(4)

———ns

tSK(o) Output Skew

(3)

— 0.5 — 0.5 — 0.5 — — ns

NOTES:

1. See test circuit and waveforms.

2. Minimum limits are guaranteed but not tested on Propagation Delays.

3. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.

4. This limit is guaranteed but not tested.

IDT54/74FCT16373T/AT/CT/ET, 162373T/AT/CT/ET
FAST CMOS 16-BIT TRANSPARENT LATCHES MILITARY AND COMMERCIAL TEMPERATURE RANGES

5.7 7

TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS

ENABLE AND DISABLE TIMESPROPAGATION DELAY

SET-UP, HOLD AND RELEASE TIMES PULSE WIDTH

SWITCH POSITION

Pulse

Generator

R

T

D.U.T.

V

CC

V

IN

C

L

V

OUT

50pF

500

Ω

500

Ω

7.0V

3V

1.5V
0V

3V

1.5V
0V

3V

1.5V
0V

3V

1.5V

0V

DATA

INPUT

TIMING

INPUT

ASYNCHRONOUS CONTROL

PRESET

CLEAR

ETC.

SYNCHRONOUS CONTROL

t

SU

t

H

t

REM

t

SU

t

H

HIGH-LOW-HIGH

PULSE

LOW-HIGH-LOW

PULSE

t

W

1.5V

1.5V

SAME PHASE

INPUT TRANSITION

3V

1.5V
0V

1.5V

V

OH

t

PLH

OUTPUT

OPPOSITE PHASE

INPUT TRANSITION

3V

1.5V
0V

t

PLH

t

PHL

t

PHL

V

OL

CONTROL

INPUT

3V

1.5V
0V

3.5V

0V

OUTPUT

NORMALLY

LOW

OUTPUT

NORMALLY

HIGH

SWITCH
CLOSED

SWITCH
OPEN

V

OL

0.3V

0.3V

t

PLZ

t

PZL

t

PZH

t

PHZ

3.5V

0V

1.5V

1.5V

ENABLE DISABLE

V

OH

PRESET

CLEAR

CLOCK ENABLE

ETC.

Test Switch

Disable Low

Enable Low

Closed

All Other Tests

Open

Open Drain

DEFINITIONS:

C

L= Load capacitance: includes jig and probe capacitance.

R

T = Termination resistance: should be equal to ZOUT of the Pulse

Generator.

2543 lnk 10

NOTES:

1. Diagram shown for input Control Enable-LOW and input Control Disable­HIGH

2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; t

F ≤ 2.5ns; tR ≤ 2.5ns

2543 drw 09

2543 drw 07

2543 drw 05

2543 drw 06

2543 drw 08

5.7 8

IDT54/74FCT16373T/AT/CT/ET, 162373T/AT/CT/ET
FAST CMOS 16-BIT TRANSPARENT LATCHES MILITARY AND COMMERCIAL TEMPERATURE RANGES

ORDERING INFORMATION

IDT XX

Temp. Range

XXXX

Device Type

X

Package

X

Process

54
74

–55°C to +125°C
–40°C to +85°C

Blank
B

PV
PA
PF
E

16373T
16373AT
16373CT
16373ET
162373T
162373AT
162373CT
162373ET

Commercial
MIL-STD-883, Class B

Shrink Small Outline Package (SO48-1)
Thin Shrink Small Outline Package (SO48-2)
Thin Very Small Outline Package (SO48-3)
CERPACK (E48-1)

Non-Inverting 16-Bit Transparent Latch

FCT

2543 drw 10