Datasheet IDT74FCT163646PV, IDT74FCT163646PF, IDT74FCT163646PA, IDT74FCT163646CPV, IDT74FCT163646CPF Datasheet (Integrated Device Technology)

Integrated Device Technology, Inc.

3.3V CMOS
16-BIT BUS TRANSCEIVER/
REGISTERS

IDT74FCT163646/A/C

FEATURES:

• 0.5 MICRON CMOS Technology

• Typical tSK(o) (Output Skew) < 250ps

• ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)

• Packages include 25 mil pitch SSOP, 19.6 mil pitch
TSSOP and 15.7 mil pitch TVSOP

• Extended commercial range of -40°C to +85°C

•V

CC = 3.3V ±0.3V, Normal Range or

VCC = 2.7 to 3.6V, Extended Range

• CMOS power levels (0.4µW typ. static)

• Rail-to-Rail output swing for increased noise margin

• Low Ground Bounce (0.3V typ.)

• Inputs (except I/O) can be driven by 3.3V or 5V
components

FUNCTIONAL BLOCK DIAGRAM

DESCRIPTION:

The FCT163646/A/C 16-bit registered transceivers are
built using advanced dual metal CMOS technology. These
high-speed, low-power devices are organized as two inde­pendant 8-bit bus transceivers with 3-state D-type registers.
The control circuitry is organized for multiplexed transmission
of data between A bus and B bus either directly or from the
internal storage registers. Each 8-bit transceiver/register
features direction control (xDIR), over-riding Output Enable
control (xOE) and Select lines (xSAB and xSBA) to select

either real-time data or stored data. Separate clock inputs are
provided for A and B port registers. Data on the A or B data
bus, or both, can be stored in the internal registers by the
LOW-to-HIGH transitions at the appropriate clock pins. Flow­through organization of signal pins simplifies layout. All inputs
are designed with hysteresis for improved noise margin.

The FCT163646/A/C have series current limiting resistors.
This offers low ground bounce, minimal undershoot, and
controlled output fall times-reducing the need for external
series terminating resistors.

OE

1

1DIR

1CLKBA

1SBA

1CLKAB

1SAB

1

A1

A REG

D

C

TO 7 OTHER CHANNELS

B REG

D
C

2778 drw 01

2CLKBA

2CLKAB

1B1

OE

2

2DIR

2SBA

2SAB

2A1

A REG

D

C

TO 7 OTHER CHANNELS

B REG

D
C

2B1

2778 drw 02

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

COMMERCIAL TEMPERATURE RANGES AUGUST 1996

1996 Integrated Device Technology, Inc. DSC-2778/6

8.8

1

IDT74FCT163646/A/C

3.3V 16-BIT BUS TRANSCEIVER/REGISTERS COMMERCIAL TEMPERATURE RANGES

PIN CONFIGURATIONS

1DIR

1CLKAB

1SAB

GND

1A1

1

A2

VCC

A3

1

1

A4

1A5

GND

1

A6

1

A7

1

A8

2A1

2

A2
A3

2

GND

A4

2
2A5
2A6

VCC

2

A7

2A8

GND

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

SO56-1
SO56-2
SO56-3

56
55
54
53
52
51
50
49

48

47
46
45
44

43

42
41
40
39
38
37
36
35
34
33
3225

OE

1
1CLKBA

1SBA

GND

1B1

1

B2

VCC

1B3

1

B4

1

B5

GND

1

B6

1B7

1

B8
B1

2

2

B2

2B3

GND

2

B4
B5

2

B6

2

VCC

2B7

2

B8

GND

PIN DESCRIPTION

Pin Names Description

xAx Data Register A Inputs

Data Register B Outputs

xBx Data Register B Inputs

Data Register A Outputs

xCAB, xCBA Clock Pulse Inputs
xSAB, xSBA Output Data Source Select Inputs

xDIR, x

OE

ABSOLUTE MAXIMUM RATINGS

Output Enable Inputs

2778 tbl 01

(1)

Symbol Description Max. Unit

(2)

VTERM

Terminal Voltage with

–0.5 to +4.6 V

Respect to GND

(3)

VTERM

Terminal Voltage with

–0.5 to +7.0 V

Respect to GND

VTERM

(4)

Terminal Voltage with
Respect to GND

–0.5 to

CC + 0.5

V

V

TSTG Storage Temperature –65 to +150 °C
IOUT DC Output Current –60 to +60 mA

NOTES:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT­INGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for ex­tended periods may affect reliability.

2. Vcc terminals.

3. Input terminals.

4. Output and I/O terminals.

2778 lnk 03

CAPACITANCE (TA = +25°C, f = 1.0MHz)

Symbol Parameter

CIN Input

Capacitance

CI/O I/O

Capacitance

NOTE:

1. This parameter is measured at characterization but not tested.

(1)

Conditions Typ. Max. Unit

VIN = 0V 3.5 6.0 pF

VOUT = 0V 3.5 8.0 pF

2778 lnk 04

2

SAB

2

CLKAB

2DIR

26
27
28

SSOP/

TSSOP/TVSOP

TOP VIEW

31
30
29

2SBA
2CLKBA
2OE

2778 drw 03

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IDT74FCT163646/A/C

3.3V 16-BIT BUS TRANSCEIVER/REGISTERS COMMERCIAL TEMPERATURE RANGES

FUNCTION TABLE

x

OE

OE

H
H

L
L
L
L

NOTES:

1. The data output functions may be enabled or disabled by various signals at the xOE or xDIR inputs. Data
input functions are always enabled, i.e. data at the bus pins will be stored on every LOW-to-HIGH transition
on the clock inputs.

2. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
↑ =LOW-to-HIGH Transition

xDIR xCLKAB xCLKBA xSAB xSBA xAx xBx

X
X

L
L
H
H

(2)

Inputs Data I/O

H or L

↑

X
X
X

H or L

H or L

↑

X

H or L

X
X

X
X

X
X
L
H

X

Input Input Isolation

X
L

Output Input Real Time B Data to A Bus
H
X

Input Output Real Time A Data to B Bus

X

(1)

Operation or Function

Store A and B Data

Stored B Data to A Bus

Stored A Data to B Bus

2778 tbl 02

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IDT74FCT163646/A/C

3.3V 16-BIT BUS TRANSCEIVER/REGISTERS COMMERCIAL TEMPERATURE RANGES

BUS

A

xDIR xOE

xCLKAB

xCLKBA xSAB xSBA

BUS

B

2778 drw 05 2778 drw 06

LL X X XL

REAL-TIME TRANSFER

BUS B TO A

BUS

A

xDIR xOE xCLKAB xCLKBA xSAB xSBA

H

L

X

REAL-TIME TRANSFER

BUS A TO B

BUS

B

XL X

BUS

A

xDIR xOE xCLKAB xCLKBA xSAB xSBA

HL
LLX

LX

XH XX

↑

↑

STORAGE FROM

A AND/OR B

BUS

B

2778 drw 07 2778 drw 08

XX

↑

X
X

X

↑

BUS

A

(1)

x

DIR

LL
H

NOTE:

1. Cannot transfer data to A bus and B bus simultaneously.

x

OE

L

x

CLKABxCLKBA

H or L

TRANSFER STORED

DATA TO A AND/OR B

X

H or L

BUS

B

x

X

SAB

X

H

x

SBA

H
X

8.8 4

IDT74FCT163646/A/C

3.3V 16-BIT BUS TRANSCEIVER/REGISTERS COMMERCIAL TEMPERATURE RANGES

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE

Following Conditions Apply Unless Otherwise Specified:
Commercial: T

Symbol Parameter Test Conditions

V

IH

V

IL

I

I H

I

I L

I

OZH

I

OZL

V

IK

I

ODH

I

ODL

V

OH

V

OL

I

OS

V

H

I

CCL

I

CCH

I

CCZ

NOTES:

1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.

2. Typical values are at Vcc = 3.3V, +25°C ambient.

3. Not more than one output should be tested at one time. Duration of the test should not exceed one second.

4. This parameter is guaranteed but not tested.

OH = VCC –0.6V at rated current.

5. V

A = –40°C to +85°C, VCC = 2.7V to 3.6V

(1)

Min. Typ.

(2)

Max. Unit

Input HIGH Level (Input pins) Guaranteed Logic HIGH Level 2.0 — 5.5 V
Input HIGH Level (I/O pins) 2.0 — VCC+0.5
Input LOW Level Guaranteed Logic LOW Level –0.5

—

0.8 V
(Input and I/O pins)
Input HIGH Current (Input pins) VCC = Max. VI = 5.5V —
Input HIGH Current (I/O pins) VI = V

CC

—
Input LOW Current (Input pins) VI = GND —
Input LOW Current (I/O pins) VI = GND —
High Impedance Output Current VCC = Max. VO = V

CC

—
(3-State Output pins) VO = GND —
Clamp Diode Voltage VCC = Min., I
Output HIGH Current VCC = 3.3V, V
Output LOW Current VCC = 3.3V, V
Output HIGH Voltage VCC = Min. IOH = –0.1mA V

VIN = V
VCC = 3.0V

V

IN

= V

IH

IH

IN

= –18mA —

IN

= V

IH

or V

IL, VO

= 1.5V

IN

= V

IH

or V

IL, VO

= 1.5V

or V

IL

IOH = –3mA 2.4 3.0 —
IOH = –8mA 2.4

or V

IL

(3)
(3)

–36 –60 –110 mA

50 90 200 mA

CC

–

(5)

–

—
—
—
—
—
—

0.7

±

1

±

1

±

1

±

1

±

1

±

1

–

1.2 V

0.2 — — V

3.0 —

Output LOW Voltage VCC = Min. IOL = 0.1mA — — 0.2 V

VIN = V

IH

or V

IL

IOL = 16mA — 0.2 0.4
IOL = 24mA — 0.3 0.55

VCC = 3.0V
V

IN

= V

IH

or V

Short Circuit Current
Input Hysteresis

(4)

VCC = Max., VO = GND

—

Quiescent Power Supply Current VCC = Max.,

V

IN

= GND or V

IL

CC

IOL = 24mA — 0.3 0.50

(3)

–60

–

— 150

135 –240 mA

—

— 0.1 10

2778 lnk 05

µ

µ

mV

µ

A

A

A

8.8 5

IDT74FCT163646/A/C

3.3V 16-BIT BUS TRANSCEIVER/REGISTERS COMMERCIAL TEMPERATURE RANGES

POWER SUPPLY CHARACTERISTICS

Symbol Parameter Test Conditions

∆ICC Quiescent Power Supply Current

VCC = Max. VIN = VCC – 0.6V

(1)

(3)

Min. Typ.

— 2.0 30 µA

TTL Inputs HIGH

ICCD Dynamic Power Supply

(4)

Current

VCC = Max.
Outputs Open

IN = VCC

V
VIN = GND

— 60 100 µA/

xDIR = xOE= GND
50% Duty Cycle
One Input Toggling

IC Total Power Supply Current

(6)

VCC = Max.
Outputs Open

CP = 10MHz (xCLKBA)

f

IN = VCC

V
VIN = GND

— 0.6 1.0 mA

50% Duty Cycle
xDIR = xOE = GND

fi = 5MHz
50% Duty Cycle

IN = VCC –0.6V

V

IN = GND

V

— 0.6 1.0

One Bit Toggling
VCC = Max.

Outputs Open

CP = 10MHz (xCLKBA)

f

IN = VCC

V
VIN = GND

— 3.0 5.0

50% Duty Cycle
xDIR = xOE = GND
fi = 2.5MHz
50% Duty Cycle

IN = VCC –0.6V

V

IN = GND

V

— 3.0 5.3

Sixteen Bits Toggling

NOTES:

1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.

2. Typical values are at V

3. Per TTL driven input; all other inputs at V

4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.

5. Values for these conditions are examples of the I

C = IQUIESCENT + IINPUTS + IDYNAMIC

6. I
IC = ICC + ∆ICC DHNT + ICCD (fCPNCP/2 + fiNi)

CC = Quiescent Current (ICCL, ICCH and ICCZ)

I

CC = Power Supply Current for a TTL High Input

∆I

H = Duty Cycle for TTL Inputs High

D
N

T = Number of TTL Inputs at DH

ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)

CP = Clock Frequency for Register Devices (Zero for Non-Register Devices)

f

CP = Number of Clock Inputs at fCP

N
fi = Input Frequency

i = Number of Inputs at fi

N

CC = 3.3V, +25°C ambient.

CC or GND.

CC formula. These limits are guaranteed but not tested.

(2)

Max. Unit

MHz

(5)

(5)

2778 tbl 06

8.8 6

IDT74FCT163646/A/C

3.3V 16-BIT BUS TRANSCEIVER/REGISTERS COMMERCIAL TEMPERATURE RANGES

SWITCHING CHARACTERISTICS OVER OPERATING RANGE

FCT163646 FCT163646A FCT163646C

Symbol Parameter Condition

tPLH
tPHL
tPZH

tPZL

tPHZ

tPLZ
tPLH
tPHL
tPLH
tPHL

Propagation Delay
Bus to Bus
Output Enable Time
xDIR or xOE to Bus

Output Disable Time
xDIR or xOE to Bus
Propagation Delay
Clock to Bus
Propagation Delay
xSBA or xSAB to Bus

CL = 50pF

L = 500Ω

R

tSU Set-up Time HIGH or

(1)

(2)

Min.

Max. Min.

2.0 9.0 2.0 6.3 1.5 5.4 ns

2.0 14.0 2.0 9.8 1.5 7.8 ns

2.0 9.0 2.0 6.3 1.5 6.3 ns

2.0 9.0 2.0 6.3 1.5 5.7 ns

2.0 11.0 2.0 7.7 1.5 6.2 ns

4.0 — 2.0 — 2.0 — ns

(4)

(2)

Max. Min.

(2)

LOW Bus to Clock

tH Hold Time HIGH or

2.0 — 1.5 — 1.5 — ns

LOW Bus to Clock

tW Clock Pulse Width

6.0 — 5.0 — 5.0 — ns

HIGH or LOW

tSK(o) Output Skew

NOTES:

1. See test circuit and waveforms.

2. Minimum limits are guaranteed but not tested on Propagation Delays.

3. Skew between any two outputs, of the same package, switching in the same direction. This parameter is guaranteed by design.

4. Propagation Delays and Enable/Disable times are with V
and Enable/Disable times should be degraded by 20%.

(3)

— 0.5 — 0.5 — 0.5 ns

CC = 3.3V ±0.3V, Normal Range. For VCC = 2.7V to 3.6V, Extended Range, all Propagation Delays

Max. Unit

2778 tbl 07

8.8 7

IDT74FCT163646/A/C

3.3V 16-BIT BUS TRANSCEIVER/REGISTERS COMMERCIAL TEMPERATURE RANGES

TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS

V

CC

V

OUT

50pF

C

L

Pulse

Generator

V

IN

D.U.T.

R

T

500

500

←

Open

GND

Ω

Ω

2778 drw 09

SWITCH POSITION

6V

Open Drain

Disable Low

Enable Low

Disable High

Enable High

All Other tests Open

DEFINITIONS:

L= Load capacitance: includes jig and probe capacitance.

C

T = Termination resistance: should be equal to ZOUT of the Pulse

R

Generator.

Test Switch

SET-UP, HOLD AND RELEASE TIMES PULSE WIDTH

DATA

INPUT

TIMING

INPUT

ASYNCHRONOUS CONTROL

PRESET

CLEAR

ETC.

SYNCHRONOUS CONTROL

PRESET

CLEAR

CLOCK ENABLE

ETC.

t

t

REM

H

t

H

t

SU

t

SU

3V

1.5V
0V

3V

1.5V
0V

3V

1.5V

0V

3V

1.5V
0V

LOW-HIGH-LOW

PULSE

HIGH-LOW-HIGH

PULSE

6V

GND

2778 lnk 08

1.5V

t

W

1.5V

2778 drw 11

SAME PHASE

INPUT TRANSITION

OUTPUT

OPPOSITE PHASE

INPUT TRANSITION

t

PLH

t

PLH

t

PHL

t

PHL

2778 drw 10

3V

1.5V
0V

OH

V

1.5V

V

OL

3V

1.5V
0V

2778 drw 12

ENABLE AND DISABLE TIMESPROPAGATION DELAY

ENABLE DISABLE

3V

CONTROL

INPUT

t

PHZ

PLZ

t

0.3V

0.3V

F ≤ 2.5ns; tR ≤ 2.5ns.

t

PZL

OUTPUT

NORMALLY

OUTPUT

NORMALLY

HIGH

NOTES:

1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH.

2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; t

CC is below 3V, input voltage swings should be adjusted not to

3. If V
exceed V

LOW

CC.

SWITCH
6V

t

PZH

SWITCH
GND

3V

1.5V

1.5V
0V

1.5V
0V

3V

V

OL

V

OH

0V

2778 drw 13

8.8 8

IDT74FCT163646/A/C

3.3V 16-BIT BUS TRANSCEIVER/REGISTERS COMMERCIAL TEMPERATURE RANGES

ORDERING INFORMATION

IDT XX

Temp. Range

XXXX

FCT

Device Type

X

Package

PV
PA
PF

163646

Shrink Small Outline Package (SO56-1)
Thin Shrink Small Outline Package (SO56-2)
Thin Very Small Outline Package (SO56-3)

Non-Inverting 16-Bit Transceiver/ Register
163646A
163646C

74 –40°C to +85°C

2778 drw 14

8.8 9