Datasheet IDT74FCT163601PV, IDT74FCT163601PF, IDT74FCT163601PA, IDT74FCT163601APV, IDT74FCT163601APF Datasheet (Integrated Device Technology)



Integrated Device Technology, Inc.

3.3V CMOS
18-BIT UNIVERSAL BUS
TRANSCEIVER
WITH 3-STATE OUTPUTS

IDT74FCT163601/A

ADVANCE INFORMATION

FEATURES:

• 0.5 MICRON CMOS Technology

• Typical tSK(o) (Output Skew) < 250ps

• ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)

• Packages include 25 mil pitch SSOP, 19.6 mil pitch
TSSOP and 15.7 mil pitch TVSOP

• Extended commercial range of -40°C to +85°C

•V

CC = 3.3V ±0.3V, Normal Range or

VCC = 2.7 to 3.6V, Extended Range

• CMOS power levels (0.4µW typ. static)

• Rail-to-Rail output swing for increased noise margin

• Low Ground Bounce (0.3V typ.)

• Inputs (except I/O) can be driven by 3.3V or 5V
components

DESCRIPTION:

The FCT163601/A 18-bit registered transceiver is built

using advanced dual metal CMOS technology. These 18-bit

FUNCTIONAL BLOCK DIAGRAM

OEAB

CLKENAB

CLKAB

LEAB
LEBA

CLKBA

1

56

55

2

28

30

universal bus transceivers combine D-type latches and D­type flip-flops to allow data flow in transparent, latched and
clocked modes.

Data flow in each direction is controlled by output-enable

(

OEAB

and

OEBA

), latch-enable (LEAB and LEBA), and clock
(CLKAB and CLKBA) inputs. The clock can be controlled by
the clock-enable (

CLKENAB

and

CLKENBA

) inputs. For A-to­B data flow, the device operates in the transparent mode when
LEAB is high. When LEAB is low, the A data is latched if
CLKAB is held at a high or low logic level. If LEAB is low, the
A-bus data is stored in the latch/flip-flop on the low-to-high
transition of CLKAB. Output enable
When

OEAB

is low, the outputs are active. When

OEAB

is active low.

OEAB

is

high, the outputs are in the high-impedance state.

Data flow for B to A is similar to that of A to B but uses

LEBA, CLKBA and

CLKENBA

.

OEBA

The FCT163601 has series current limiting resistors. These
offer low ground bounce, minimal undershoot, and controlled
output fall times-reducing the need for external series termi­nating resistors.

,

A1

29

27

3

CE

1D
C1

CLK

TO 17 OTHER CHANNELS

CE
1D
C1

CLK

54

B1

3251 drw 01

CLKENBA

OEBA

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

COMMERCIAL TEMPERATURE RANGE AUGUST 1996

1996 Integrated Device Technology, Inc. 5.9 DSC-3251/1

1

IDT74FCT163601/A

3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVERS COMMERCIAL TEMPERATURE RANGE

PIN CONFIGURATIONS

OEAB

LEAB

A

GND

A
A

V

CC

A
A
A

GND

A
A

A
A
A
A

GND

A
A
A

V

CC

A
A

GND

A

OEBA

LEBA

1
2

1

3
4

2

5

3

6
7

4

8

5

9

6

10
11

7

12

8

13

9

14

SO56-1

10

11

12

15
16
17

SO56-2
SO56-3

18

13

14

15

19
20
21
22

16

17

23
24

56
55
54
53
52
51
50
49

48

47
46
45
44

43

42
41
40
39
38
37
36
35
34
33
3225

18

26
27
28

31
30
29

SSOP

TSSOP/TVSOP

TOP VIEW

CLKENAB
CLKAB
B

1

GND

2

B
B

3

V

CC

B

4

B

5

B

6

GND
B

7

B

8

B

9

B

10

B

11

B

12

GND
B

13

B

14

B

15

V

CC

16

B
B

17

GND
B

18

CLKBA
CLKENBA

3251 drw 02

PIN DESCRIPTION

Pin Names Description

OEAB
OEBA

LEAB A-to-B Latch Enable Input
LEBA B-to-A Latch Enable Input
CLKAB A-to-B Clock Input
CLKBA B-to-A Clock Input
Ax A-to-B Data Inputs or B-to-A 3-State Outputs
Bx B-to-A Data Inputs or A-to-B 3-State Outputs

CLKENAB
CLKENBA

A-to-B Output Enable Input (Active LOW)
B-to-A Output Enable Input (Active LOW)

A to B Clock Enable Input (Active LOW)
B to A Clock Enable Input (Active LOW)

3251 tbl 01

CAPACITANCE (TA = +25°C, f = 1.0MHz)

Symbol Parameter

CIN Input

Capacitance

CI/O I/O

Capacitance

NOTE:

1. This parameter is measured at characterization but not tested.

ABSOLUTE MAXIMUM RATINGS

Symbol Description Max. Unit

(2)

VTERM

Terminal Voltage with
Respect to GND

(3)

VTERM

Terminal Voltage with
Respect to GND

(4)

VTERM

Terminal Voltage with
Respect to GND

TSTG Storage Temperature –65 to +150 °C
IOUT DC Output Current –60 to +60 mA

NOTES:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT­INGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.

2. Vcc terminals.

3. Input terminals.

4. Output and I/O terminals.

FUNCTION TABLE

CLKENAB

CLKENAB

XHXXXZ
XLHXLL
XLHXHH
HLLXXB0
LLL↑LL
LLL↑HH
L LLLXB0
LLLHXB0

NOTES: 3251 tbl 02

1. A-to-B data flow is shown. B-to-A data flow is similar but uses
LEBA, CLKBA and

2. Output level before the indicated steady-state input conditions were
established.

3. Output level before the indicated steady-state input conditions were
established, provided that CLKAB was HIGH before LEAB went LOW.

4. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
Z = High-impedance
↑ = LOW-to-HIGH Transition

OEAB

OEAB

(1)

Conditions Typ. Max. Unit

VIN = 0V 3.5 6.0 pF

VOUT = 0V 3.5 8.0 pF

3251 lnk 04

(1)

–0.5 to +4.6 V

–0.5 to +7.0 V

–0.5 to

CC + 0.5

V

V

3251 lnk 03

(1,4)

Inputs Outputs

LEAB CLKAB A B

(2)

(2)

(3)

CLKENBA

.

OEBA

,

5.9 2

IDT74FCT163601/A

3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVERS COMMERCIAL TEMPERATURE RANGE

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE

Following Conditions Apply Unless Otherwise Specified:
Commercial: TA = –40°C to +85°C, VCC = 2.7V to 3.6V

Symbol Parameter Test Conditions

(1)

Min. Typ.

VIH Input HIGH Level (Input pins) Guaranteed Logic HIGH Level 2.0 — 5.5 V

Input HIGH Level (I/O pins) 2.0 — VCC+0.5

VIL Input LOW Level Guaranteed Logic LOW Level –0.5 — 0.8 V

(Input and I/O pins)

II H Input HIGH Current (Input pins) VCC = Max. VI = 5.5V — — ±1 µA

Input HIGH Current (I/O pins) VI = VCC — — ±1

II L Input LOW Current (Input pins) VI = GND — — ±1

Input LOW Current (I/O pins) VI = GND — — ±1
IOZH High Impedance Output Current VCC = Max. VO = VCC — — ±1 µA
IOZL (3-State Output pins) VO = GND — — ±1
VIK Clamp Diode Voltage VCC = Min., IIN = –18mA — –0.7 –1.2 V
IODH Output HIGH Current VCC = 3.3V, VIN = VIH or VIL, VO = 1.5V
IODL Output LOW Current VCC = 3.3V, VIN = VIH or VIL, VO = 1.5V

(3)
(3)

–36 –60 –110 mA

50 90 200 mA

VOH Output HIGH Voltage VCC = Min. IOH = –0.1mA VCC–0.2 — — V

VIN = VIH or VIL IOH = –3mA 2.4 3.0 —
VCC = 3.0V

V

IN = VIH or VIL

IOH = –8mA 2.4

(5)

VOL Output LOW Voltage VCC = Min. IOL = 0.1mA — — 0.2 V

VIN = VIH or VIL IOL = 16mA — 0.2 0.4

IOL = 24mA — 0.3 0.55

IOS Short Circuit Current

(4)

VCC = 3.0V
V

IN = VIH or VIL

VCC = Max., VO = GND

IOL = 24mA — 0.3 0.50

(3)

–60 –135 –240 mA
VH Input Hysteresis — — 150 — mV
ICCL

ICCH

Quiescent Power Supply Current VCC = Max.,

V

IN = GND or VCC

— 0.1 10 µA

ICCZ

NOTES:

1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.

2. Typical values are at Vcc = 3.3V, +25°C ambient.

3. Not more than one output should be tested at one time. Duration of the test should not exceed one second.

4. This parameter is guaranteed but not tested.

OH = VCC –0.6V at rated current.

5. V

(2)

Max. Unit

3.0 —

3251 lnk 05

5.9 3

IDT74FCT163601/A

3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVERS COMMERCIAL TEMPERATURE RANGE

POWER SUPPLY CHARACTERISTICS

Symbol Parameter Test Conditions

CC Quiescent Power Supply VCC = Max. — 2.0 30 µA

∆I

Current TTL Inputs HIGH V

ICCD Dynamic Power Supply Current

IN = VCC –0.6V

(4)

VCC = Max., Outputs Open VIN = VCC — 60 100 µA/

OEAB

= V

CC

(3

OEBA

(1)

Min. Typ.

= GND V IN = GND MHz
One Input Toggling
50% Duty Cycle

I

C Total Power Supply Current

(6)

VCC = Max., Outputs Open VIN = VCC — 0.6 1.0 mA
f

CP = 10MHz (CLKBA) VIN = GND

50% Duty Cycle

OEAB

= V

CC

OEBA

= GND

LEBA = GND V

CLKENBA

= GND V

IN = VCC –0.6 — 0.6 1.0
IN = GND

One Bit Toggling
f

i = 5MHz

50% Duty Cycle
V

CC = Max., Outputs Open VIN = VCC — 3.0 5.0

fCP = 10MHz (CLKBA) VIN = GND
50% Duty Cycle

OEAB

= V

CC

OEBA

= GND

LEBA = GND V

CLKENBA

= GND VIN = GND

IN = VCC –0.6 — 3.0 5.3

Eighteen Bits Toggling
f

i = 2.5MHz

50% Duty Cycle

NOTES:

1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.

2. Typical values are at V

3. Per TTL driven input; all other inputs at V

4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.

5. Values for these conditions are examples of the I

C = IQUIESCENT + IINPUTS + IDYNAMIC

6. I
IC = ICC + ∆ICC DHNT + ICCD (fCPNCP/2 + fiNi)
I

CC = Quiescent Current (ICCL, ICCH and ICCZ)

CC = Power Supply Current for a TTL High Input

∆I

H = Duty Cycle for TTL Inputs High

D

T = Number of TTL Inputs at DH

N
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)

CP = Clock Frequency for Register Devices (Zero for Non-Register Devices)

f

CP = Number of Clock Inputs at fCP

N
fi = Input Frequency

i = Number of Inputs at fi

N

CC = 3.3V, +25°C ambient.

CC or GND.

CC formula. These limits are guaranteed but not tested.

(2)

Max. Unit

(5)

(5)

3251 tbl 06

5.9 4

IDT74FCT163601/A

3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVERS COMMERCIAL TEMPERATURE RANGE

SWITCHING CHARACTERISTICS OVER OPERATING RANGE

FCT163601 FCT163601A

Symbol Parameter Condition

fMAX CLKAB or CLKBA frequency

tPLH

Propagation Delay
Ax to Bx or Bx to Ax

tPHL
tPLH

Propagation Delay
LEBA to Ax, LEAB to Bx

tPHL
tPLH

Propagation Delay
CLKBA to Ax, CLKAB to Bx

tPHL
tPZH

Output Enable Time

OEBA

to Ax,

OEAB

OEAB

to Bx

to Bx

tPZL

tPHZ

Output Disable Time

OEBA

tPLZ

to Ax,

(4)

CL = 50pF — 100 — 150 MHz

RL = 500Ω 1.5 6.5 1.5 5.5 ns

(1)

tSU Set-up Time, HIGH or LOW

Ax to CLKAB, Bx to CLKBA

tH Hold Time HIGH or LOW

Ax to CLKAB, Bx to CLKBA

tSU Set-up Time

HIGH or LOW
Ax to LEAB,
Bx to LEBA

tSU Set-up Time,

CLKEN

Clock
LOW
Clock
HIGH

to CLK 3.0 — 2.5 — ns

tH Hold Time, HIGH or LOW

Ax to LEAB, Bx to LEBA

tH Hold Time,

CKLEN

after CLK 0 — 0 — ns

tW LEAB or LEBA Pulse Width

(4)

HIGH

tW CLKAB or CLKBA Pulse Width

HIGH or LOW

tSK(o) Output Skew

NOTES: 3251 tbl 07

1. See test circuit and waveforms.

2. Minimum limits are guaranteed but not tested on Propagation Delays.

3. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.

4. This parameter is guaranteed but not tested.

(4)

(3)

Min.

(2)

Max. Min.

(2)

Max. Unit

1.5 7.2 1.5 6.2 ns

1.5 7.3 1.5 6.3 ns

1.5 7.5 1.5 6.5 ns

1.5 6.5 1.5 5.2 ns

4.0 — 3.0 — ns

0—0—ns

2.5 — 2.5 — ns

2.0 — 2.0 — ns

1.5 — 1.0 — ns

3.0 — 2.5 — ns

3.0 — 3.0 — ns

— 0.5 — 0.5 ns

5.9 5

IDT74FCT163601/A

3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVERS COMMERCIAL TEMPERATURE RANGE

TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS

V

CC

V

OUT

50pF

C

L

Pulse

Generator

V IN

D.U.T.

R T

←

500Ω

500Ω

3251 lnk 04

SWITCH POSITION

6V

Open

GND

Disable High

All Other tests Open

DEFINITIONS:

L= Load capacitance: includes jig and probe capacitance.

C
R

T = Termination resistance: should be equal to ZOUT of the Pulse

Generator.

Test Switch

Open Drain

Disable Low

Enable Low

Enable High

SET-UP, HOLD AND RELEASE TIMES PULSE WIDTH

3V

1.5V
0V

3251 lnk 05

3V

1.5V
0V

3V

1.5V
0V

3V

1.5V

0V

LOW-HIGH-LOW

PULSE

HIGH-LOW-HIGH

PULSE

DATA

INPUT

TIMING

INPUT

ASYNCHRONOUS CONTROL

PRESET

CLEAR

ETC.

SYNCHRONOUS CONTROL

PRESET

CLEAR

CLOCK ENABLE

ETC.

tSU

tSU

tH

tREM

tH

6V

GND

3251 tbl 08

1.5V

tW

1.5V

3251 lnk 06

SAME PHASE

INPUT TRANSITION

OUTPUT

OPPOSITE PHASE

INPUT TRANSITION

tPLH

tPHL

tPLH tPHL

3V

1.5V
0V

V

OH

1.5V

VOL

3V

1.5V
0V

3251 lnk 07

ENABLE AND DISABLE TIMESPROPAGATION DELAY

ENABLE DISABLE

CONTROL

INPUT

PLZtPZL

t

OUTPUT

NORMALLY

LOW

SWITCH
6V

tPZH tPHZ

OUTPUT

NORMALLY

HIGH

NOTES:

1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH.

2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; t

3. If V

CC is below 3V, input voltage swings should be adjusted not to

exceed V

CC.

SWITCH
GND

3V

1.5V

1.5V
0V

0.3V

0.3V

F ≤ 2.5ns; tR ≤ 2.5ns.

3V

1.5V
0V

3V

VOL

VOH

0V

3251 lnk 08

5.9 6

IDT74FCT163601/A

3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVERS COMMERCIAL TEMPERATURE RANGE

ORDERING INFORMATION

IDT XX

Temp. Range

FCT

XXXX

Device Type

X

Package

PV
PA
PF

163601
163601A

74

Shrink Small Outline Package (SO56-1)
Thin Shrink Small Outline Package (SO56-2)
Thin Very Small Outline Package (SO56-3)

Non-Inverting 18-Bit Registered Transceiver

–40°C to +85°C

5.9 7