Datasheet IDT74FCT163543PV, IDT74FCT163543PF, IDT74FCT163543PA, IDT74FCT163543CPV, IDT74FCT163543CPF Datasheet (Integrated Device Technology)
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Integrated Device Technology, Inc.
3.3V CMOS
16-BIT LATCHED
TRANSCEIVER
IDT74FCT163543/A/C
ADVANCE INFORMATION
FEATURES:
• 0.5 MICRON CMOS Technology
• Typical tSK(o) (Output Skew) < 250ps
• ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
• Packages include 25 mil pitch SSOP, 19.6 mil pitch
TSSOP and 15.7 mil pitch TVSOP
• Extended commercial range of -40°C to +85°C
•V
CC = 3.3V ±0.3V, Normal Range or
VCC = 2.7 to 3.6V, Extended Range
• CMOS power levels (0.4µW typ. static)
• Rail-to-Rail output swing for increased noise margin
• Low Ground Bounce (0.3V typ.)
• Inputs (except I/O) can be driven by 3.3V or 5V
components
FUNCTIONAL BLOCK DIAGRAM
DESCRIPTION:
The FCT163543/A/C 16-bit latched transceivers are built
using advanced dual metal CMOS technology. These highspeed, low-power devices are organized as two independent 8bit D-type latched transceivers with separate input and output
control to permit independent control of data flow in either
direction. For example, the A-to-B Enable (x
LOW in order to enter data from the A port or to output data from
the B port. x
LEAB
controls the latch function. When x
LOW, the latches are transparent. A subsequent LOW-toHIGH transition of x
storage mode. x
LEAB
signal puts the A latches in the
OEAB
performs output enable function on the
B port. Data flow from the B port to the A port is similar but
requires using x
CEBA
, x
LEBA
, and x
OEBA
organization of signal pins simplifies layout. All inputs are
designed with hysteresis for improved noise margin.
The FCT163543/A/C have series current limiting resistors.
These offer low ground bounce, minimal undershoot, and
controlled output fall times–reducing the need for external
series terminating resistors.
CEAB
) must be
LEAB
is
inputs. Flow-through
1
OEBA
1
CEBA
1
LEBA
1
OEAB
1
CEAB
1
LEAB
1A1
C
D
C
D
TO 7 OTHER CHANNELS
1B1
3250 drw 01
2OEBA
2CEBA
2LEBA
2OEAB
2CEAB
2
LEAB
2A1
C
D
C
D
TO 7 OTHER CHANNELS
B1
2
3250 drw 02
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE SEPTEMBER 1996
1996 Integrated Device Technology, Inc. 8.7 DSC-3250/2
1
IDT74FCT163543/A/C
3.3V CMOS 16-BIT LATCHED TRANSCEIVER COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATIONS
1OEAB
1LEAB
1CEAB
GND
1A1
A2
1
VCC
A3
1
A4
1
1A5
GND
A6
1
A7
1
A8
1
2A1
A2
2
2
A3
GND
2
A4
A5
2
2
A6
VCC
A7
2
2A8
GND
2CEAB
2LEAB
OEAB
2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
SO56-1
SO56-2
15
SO56-3
16
17
18
19
20
21
22
23
24
26
27
28
SSOP/
TSSOP/TVSOP
TOP VIEW
48
43
56
55
54
53
52
51
50
49
47
46
45
44
42
41
40
39
38
37
36
35
34
33
3225
31
30
29
1
OEBA
1LEBA
1CEBA
GND
1B1
B2
1
VCC
1B3
B4
1
B5
1
GND
B6
1
1B7
B8
1
B1
2
B2
2
2B3
GND
B4
2
B5
2
2
B6
VCC
2B7
B8
2
GND
2CEBA
2LEBA
2OEBA
3250 drw 03
CAPACITANCE (TA = +25°C, f = 1.0MHz)
Symbol Parameter
C
IN
Input
Capacitance
C
I/O
I/O
Capacitance
NOTE:
1. This parameter is measured at characterization but not tested.
(1)
Conditions Typ. Max. Unit
VIN = 0V 3.5 6.0 pF
V
OUT
= 0V 3.5 8.0 pF
3250 lnk 04
PIN DESCRIPTION
Pin Names Description
x
OEAB
x
OEBA
x
CEAB
x
CEBA
x
LEAB
x
LEBA
xAx A-to-B Data Inputs or B-to-A 3-State Outputs
xBx B-to-A Data Inputs or A-to-B 3-State Outputs
ABSOLUTE MAXIMUM RATINGS
Symbol Description Max. Unit
(2)
VTERM
(3)
VTERM
(4)
VTERM
TSTG Storage Temperature –65 to +150 °C
IOUT DC Output Current –60 to +60 mA
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. Vcc terminals.
3. Input terminals.
4. Output and I/O terminals.
FUNCTION TABLE
For A-to-B (Symmetric with B-to-A)
x
CEAB
CEAB
H X X Storing High Z
X H X Storing X
L L L Transparent Current A Inputs
L H L Storing Previous
L L H Transparent High Z
L H H Storing High Z
NOTES: 3250 tbl 02
1. A-to-B data flow shown; B-to-A flow control is the same, except using
x
CEBA
2. Before x
3. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
A-to-B Output Enable Input (Active LOW)
B-to-A Output Enable Input (Active LOW)
A-to-B Enable Input (Active LOW)
B-to-A Enable Input (Active LOW)
A-to-B Latch Enable Input (Active LOW)
B-to-A Latch Enable Input (Active LOW)
(1)
Terminal Voltage with
–0.5 to +4.6 V
Respect to GND
Terminal Voltage with
–0.5 to +7.0 V
Respect to GND
Terminal Voltage with
Respect to GND
–0.5 to
CC + 0.5
V
(1, 3)
Latch Output
Inputs Status Buffers
x
, x
LEAB
LEAB
LEAB
x
OEAB
OEAB
LEBA
and x
OEBA
LOW-to-HIGH Transition
.
xAx to xBx xBx
3250 tbl 01
3250 lnk 03
(2)
A Inputs
V
8.7 2
IDT74FCT163543/A/C
3.3V CMOS 16-BIT LATCHED TRANSCEIVER COMMERCIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: TA = –40°C to +85°C, VCC = 2.7V to 3.6V
Symbol Parameter Test Conditions
V
IH
Input HIGH Level (Input pins) Guaranteed Logic HIGH Level 2.0 — 5.5 V
(1)
Min. Typ.
Input HIGH Level (I/O pins) 2.0 — VCC+0.5
V
IL
Input LOW Level Guaranteed Logic LOW Level –0.5
(Input and I/O pins)
I
I H
I
I L
Input HIGH Current (Input pins) VCC = Max. VI = 5.5V —
Input HIGH Current (I/O pins) VI = V
CC
—
Input LOW Current (Input pins) VI = GND —
Input LOW Current (I/O pins) VI = GND —
I
OZH
I
OZL
V
I
ODH
I
ODL
V
V
IK
OH
OL
High Impedance Output Current VCC = Max. VO = V
CC
—
(3-State Output pins) VO = GND —
Clamp Diode Voltage VCC = Min., I
Output HIGH Current VCC = 3.3V, V
Output LOW Current VCC = 3.3V, V
Output HIGH Voltage VCC = Min. IOH = –0.1mA V
VIN = V
VCC = 3.0V
V
IN
= V
IH
IH
IN
= –18mA —
IN
= V
IH
or V
IL, VO
= 1.5V
IN
= V
IH
or V
IL, VO
= 1.5V
or V
IL
IOH = –3mA 2.4 3.0 —
IOH = –8mA 2.4
or V
IL
(3)
(3)
–36 –60 –110 mA
50 90 200 mA
CC
–
0.2 — — V
(5)
Output LOW Voltage VCC = Min. IOL = 0.1mA — — 0.2 V
VIN = V
IH
or V
IL
IOL = 16mA — 0.2 0.4
IOL = 24mA — 0.3 0.55
VCC = 3.0V
V
IN
= V
IH
or V
IL
I
OS
V
H
I
CCL
I
CCH
I
CCZ
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 3.3V, +25°C ambient.
3. Not more than one output should be tested at one time. Duration of the test should not exceed one second.
4. This parameter is guaranteed but not tested.
5. V
OH = VCC –0.6V at rated current.
Short Circuit Current
Input Hysteresis
Quiescent Power Supply Current VCC = Max.,
(4)
VCC = Max., VO = GND
—
V
IN
= GND or V
CC
IOL = 24mA — 0.3 0.50
(3)
–60
— 150
— 0.1 10
(2)
Max. Unit
–
—
—
—
—
—
—
—
0.7
0.8 V
±
1
±
1
±
1
±
1
±
1
±
1
–
1.2 V
3.0 —
–
135 –240 mA
—
3250 lnk 05
µ
µ
mV
µ
A
A
A
8.7 3
IDT74FCT163543/A/C
3.3V CMOS 16-BIT LATCHED TRANSCEIVER COMMERCIAL TEMPERATURE RANGE
POWER SUPPLY CHARACTERISTICS
Symbol Parameter Test Conditions
∆I
CC Quiescent Power Supply VCC = Max. — 2.0 30 µA
Current TTL Inputs HIGH V
ICCD Dynamic Power Supply Current
(4)
IN = VCC –0.6V
VCC = Max., Outputs Open VIN = VCC — 60 100 µA/
x
CEAB
and x
x
CEBA
= V
CC
(3)
OEAB
= GND V
(1)
IN = GND MHz
Min. Typ.
One Input Toggling
50% Duty Cycle
C Total Power Supply Current
I
(6)
VCC = Max., Outputs Open VIN = VCC — 0.6 1.0 mA
i = 10MHz VIN = GND
f
50% Duty Cycle
x
LEAB
, x
CEAB
and
x
OEAB
x
CEBA
= GND V
= V
CC VIN = GND
IN = VCC –0.6V — 0.6 1.0
One Bit Toggling
(2)
Max. Unit
CC = Max., Outputs Open VIN = VCC — 2.4 4.0
V
fi = 2.5MHz VIN = GND
50% Duty Cycle
x
LEAB
, x
CEAB
and
x
OEAB
= GND V
x
CEBA
= VCC VIN = GND
IN = VCC –0.6V — 2.4 4.3
Sixteen Bits Toggling
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
3. Per TTL driven input; all other inputs at V
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the I
C = IQUIESCENT + IINPUTS + IDYNAMIC
6. I
IC = ICC + ∆ICC DHNT + ICCD (fCPNCP/2 + fiNi)
I
CC = Quiescent Current (ICCL, ICCH and ICCZ)
CC = Power Supply Current for a TTL High Input
∆I
H = Duty Cycle for TTL Inputs High
D
T = Number of TTL Inputs at DH
N
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
CP = Clock Frequency for Register Devices (Zero for Non-Register Devices)
f
CP = Number of Clock Inputs at fCP
N
fi = Input Frequency
N
i = Number of Inputs at fi
CC = 3.3V, +25°C ambient.
CC or GND.
CC formula. These limits are guaranteed but not tested.
(5)
(5)
3250 tbl 06
8.7 4
IDT74FCT163543/A/C
3.3V CMOS 16-BIT LATCHED TRANSCEIVER COMMERCIAL TEMPERATURE RANGE
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
FCT163543 FCT163543A FCT163543C
Symbol Parameter Condition
tPLH
Propagation Delay
tPHL
Transparent Mode
CL = 50pF
L = 500Ω
R
(1)
(2)
Min.
Max. Min.
1.5 8.5 1.5 6.5 1.5 5.3 ns
(4)
(2)
Max. Min.
(2)
Max. Unit
xAx to xBx or xBx to xAx
tPLH
Propagation Delay
tPHL
x
LEBA
tPZH
Output Enable Time
tPZL
x
OEBA
x
CEBA
tPHZ
Output Disable Time
tPLZ
x
OEBA
x
CEBA
to xAx, x
or x
or x
or x
or x
LEAB
OEAB
CEAB
to xAx or xBx
OEAB
CEAB
to xAx or xBx
to xBx
to xAx or xBx
to xAx or xBx
tSU Set-up Time HIGH or LOW
xAx or xBx to x
LEAB
or x
tH Hold Time HIGH or LOW
xAx or xBx to x
tW x
LEBA
or x
LEAB
LEAB
or x
Pulse Width
LEBA
LEBA
1.5 12.5 1.5 8.0 1.5 7.0 ns
1.5 12.0 1.5 9.0 1.5 8.0 ns
1.5 9.0 1.5 7.5 1.5 6.5 ns
3.0 — 2.0 — 2.0 — ns
2.0 — 2.0 — 2.0 — ns
5.0 — 5.0 — 5.0 — ns
LOW
tSK(o) Output Skew
NOTES: 3250 tbl 07
1. See test circuits and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
4. Propagation Delays and Enable/Disable times are with V
and Enable/Disable times should be degraded by 20%.
(3)
— 0.5 — 0.5 — 0.5 ns
CC = 3.3V ±0.3V, Normal Range. For VCC = 2.7V to 3.6V, Extended Range, all Propagation Delays
8.7 5
IDT74FCT163543/A/C
3.3V CMOS 16-BIT LATCHED TRANSCEIVER COMMERCIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS
V
CC
V
OUT
50pF
C
L
Pulse
Generator
V IN
D.U.T.
R T
500Ω
500Ω
←
Open
GND
3250 drw 05
SWITCH POSITION
6V
DEFINITIONS:
C
L= Load capacitance: includes jig and probe capacitance.
T = Termination resistance: should be equal to ZOUT of the Pulse
R
Generator.
Test Switch
Open Drain
Disable Low
Enable Low
Disable High
Enable High
All Other tests Open
SET-UP, HOLD AND RELEASE TIMES PULSE WIDTH
DATA
INPUT
TIMING
INPUT
ASYNCHRONOUS CONTROL
PRESET
CLEAR
ETC.
SYNCHRONOUS CONTROL
PRESET
CLEAR
CLOCK ENABLE
ETC.
tSU
tSU
tH
tREM
tH
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
3250 drw 06
LOW-HIGH-LOW
PULSE
HIGH-LOW-HIGH
PULSE
6V
GND
3250 lnk 08
1.5V
tW
1.5V
3250 drw 07
SAME PHASE
INPUT TRANSITION
OUTPUT
OPPOSITE PHASE
INPUT TRANSITION
tPLH
tPHL
tPLH tPHL
3V
1.5V
0V
V
OH
1.5V
VOL
3V
1.5V
0V
3250 drw 08
ENABLE AND DISABLE TIMESPROPAGATION DELAY
ENABLE DISABLE
CONTROL
INPUT
t
PLZtPZL
OUTPUT
NORMALLY
LOW
SWITCH
6V
tPZH tPHZ
OUTPUT
NORMALLY
HIGH
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH.
2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; t
CC is below 3V, input voltage swings should be adjusted not to
3. If V
exceed V
SWITCH
GND
CC.
3V
1.5V
1.5V
0V
0.3V
VOL
VOH
0.3V
3250 drw 09
F ≤ 2.5ns; tR ≤ 2.5ns.
3V
1.5V
0V
3V
0V
8.7 6
IDT74FCT163543/A/C
3.3V CMOS 16-BIT LATCHED TRANSCEIVER COMMERCIAL TEMPERATURE RANGE
ORDERING INFORMATION
IDT
Temperature
Range
FCT
X
XXXX
Device
X
Package
Type
PV
PA
PF
163543
Shrink Small Outline Package (SO56-1)
Thin Shrink Small Outline Package (SO56-2)
Thin Very Small Outline Package (SO56-3)
16-Bit Latched Transceiver
163543A
163543C
–40°C to +85°C74
3250 drw 10
8.7 7
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