Datasheet IDT74FCT163501PA, IDT74FCT163501APV, IDT74FCT163501APF, IDT74FCT163501APA, IDT74FCT163501PV Datasheet (Integrated Device Technology)
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Integrated Device Technology, Inc.
3.3V CMOS
18-BIT REGISTERED
TRANSCEIVER
IDT74FCT163501/A/C
FEATURES:
• 0.5 MICRON CMOS Technology
• Typical tSK(o) (Output Skew) < 250ps
• ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
• Packages include 25 mil pitch SSOP, 19.6 mil pitch
TSSOP and 15.7 mil pitch TVSOP
• Extended commercial range of -40°C to +85°C
•V
CC = 3.3V ±0.3V, Normal Range or
VCC = 2.7 to 3.6V, Extended Range
• CMOS power levels (0.4µW typ. static)
• Rail-to-Rail output swing for increased noise margin
• Low Ground Bounce (0.3V typ.)
• Inputs (except I/O) can be driven by 3.3V or 5V
components
DESCRIPTION:
The FCT163501/A/C 18-bit registered transceivers are
built using advanced dual metal CMOS technology. These
FUNCTIONAL BLOCK DIAGRAM
high-speed, low-power 18-bit registered bus transceivers
combine D-type latches and D-type flip-flops to allow data flow
in transparent, latched and clocked modes. Data flow in each
direction is controlled by output-enable (OEAB and
OEBA
latch enable (LEAB and LEBA) and clock (CLKAB and CLKBA)
inputs. For A-to-B data flow, the device operates in transparent mode when LEAB is HIGH. When LEAB is LOW, the A
data is latched if CLKAB is held at a HIGH or LOW logic level.
If LEAB is LOW, the A bus data is stored in the latch/flip-flop
on the LOW-to-HIGH transition of CLKAB. OEAB performs
the output enable function on the B port. Data flow from B port
to A port is similiar but requires using
OEBA
, LEBA and
CLKBA. Flow-through organization of signal pins simplifies
layout. All inputs are designed with hysteresis for improved
noise margin.
The FCT163501/A/C have series current limiting resistors.
These offer low ground bounce, minimal undershoot, and
controlled output fall times-reducing the need for external
series terminating resistors.
),
OEAB
CLKBA
LEBA
OEBA
CLKAB
LEAB
A1
C
D
C
D
TO 17 OTHER CHANNELS
C
D
C
D
1
B
2776 drw 01
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE AUGUST 1996
1996 Integrated Device Technology, Inc. 8.6 DSC-2776/4
1
IDT74FCT163501/A/C
3.3V 18-BIT REGISTERED TRANSCEIVER COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATIONS
OEAB
LEAB
A
GND
A
A3
VCC
A4
A5
A
GND
A7
A8
A9
A
A11
A12
GND
A13
A14
A
VCC
A16
1
2
3
1
4
5
2
6
7
8
9
10
6
11
12
13
14
SO56-1
SO56-2
10
15
SO56-3
16
17
18
19
20
15
21
22
23
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
GND
CLKAB
B1
GND
2
B
B3
VCC
4
B
B5
B6
GND
B7
B8
B9
B10
B11
12
B
GND
B13
B14
B15
VCC
16
B
PIN DESCRIPTION
Pin Names Description
OEAB A-to-B Output Enable Input
OEBA
LEAB A-to-B Latch Enable Input
LEBA B-to-A Latch Enable Input
CLKAB A-to-B Clock Input
CLKBA B-to-A Clock Input
Ax A-to-B Data Inputs or B-to-A 3-State Outputs
Bx B-to-A Data Inputs or A-to-B 3-State Outputs
ABSOLUTE MAXIMUM RATINGS
Symbol Description Max. Unit
(2)
V
TERM
(3)
V
TERM
(4)
V
TERM
T
STG
I
OUT
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. Vcc terminals.
3. Input terminals.
4. Output and I/O terminals.
FUNCTION TABLE
B-to-A Output Enable Input (Active LOW)
2776 tbl 01
(1)
Terminal Voltage with
–0.5 to +4.6 V
Respect to GND
Terminal Voltage with
–0.5 to +7.0 V
Respect to GND
Terminal Voltage with
Respect to GND
–0.5 to
CC
+ 0.5
V
Storage Temperature –65 to +150
V
°
C
DC Output Current –60 to +60 mA
2776 lnk 03
(1,4)
A
GND
A18
OEBA
LEBA
17
24
26
27
28
33
3225
31
30
29
B17
GND
18
B
CLKBA
GND
SSOP/
TSSOP/TVSOP
TOP VIEW
2776 drw 02
CAPACITANCE (TA = +25°C, f = 1.0MHz)
Symbol Parameter
CIN Input
Capacitance
CI/O I/O
Capacitance
NOTE:
1. This parameter is measured at characterization but not tested.
(1)
Conditions Typ. Max. Unit
VIN = 0V 3.5 6.0 pF
VOUT = 0V 3.5 8.0 pF
2776 lnk 04
Inputs Outputs
OEAB LEAB CLKAB Ax Bx
LXX XZ
HHX LL
HHX HH
HL↑ LL
HL↑ HH
HLL XB
HLH XB
NOTES: 2776 tbl 02
1. A-to-B data flow is shown. B-to-A data flow is similar but uses
LEBA, and CLKBA.
2. Output level before the indicated steady-state input conditions were
established.
3. Output level before the indicated steady-state input conditions were
established, provided that CLKAB was HIGH before LEAB went LOW.
4. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
Z = High Impedance
↑ = LOW-to-HIGH Transition
8.6 2
(2)
(3)
OEBA
,
IDT74FCT163501/A/C
3.3V 18-BIT REGISTERED TRANSCEIVER COMMERCIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: T
Symbol Parameter Test Conditions
V
IH
V
IL
I
I H
I
I L
I
OZH
I
OZL
V
IK
I
ODH
I
ODL
V
OH
V
OL
I
OS
V
H
I
CCL
I
CCH
I
CCZ
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 3.3V, +25°C ambient.
3. Not more than one output should be tested at one time. Duration of the test should not exceed one second.
4. This parameter is guaranteed but not tested.
5. V
OH = VCC –0.6V at rated current.
A = –40°C to +85°C, VCC = 2.7V to 3.6V
(1)
Min. Typ.
(2)
Max. Unit
Input HIGH Level (Input pins) Guaranteed Logic HIGH Level 2.0 — 5.5 V
Input HIGH Level (I/O pins) 2.0 — VCC+0.5
Input LOW Level Guaranteed Logic LOW Level –0.5
—
0.8 V
(Input and I/O pins)
Input HIGH Current (Input pins) VCC = Max. VI = 5.5V —
Input HIGH Current (I/O pins) VI = V
CC
—
Input LOW Current (Input pins) VI = GND —
Input LOW Current (I/O pins) VI = GND —
High Impedance Output Current VCC = Max. VO = V
CC
—
(3-State Output pins) VO = GND —
Clamp Diode Voltage VCC = Min., I
Output HIGH Current VCC = 3.3V, V
Output LOW Current VCC = 3.3V, V
Output HIGH Voltage VCC = Min. IOH = –0.1mA V
VIN = V
VCC = 3.0V
V
IN
= V
IH
IH
IN
= –18mA —
IN
= V
IH
or V
IL, VO
= 1.5V
IN
= V
IH
or V
IL, VO
= 1.5V
or V
IL
IOH = –3mA 2.4 3.0 —
IOH = –8mA 2.4
or V
IL
(3)
(3)
–36 –60 –110 mA
50 90 200 mA
CC
–
(5)
–
—
—
—
—
—
—
0.7
±
1
±
1
±
1
±
1
±
1
±
1
–
1.2 V
0.2 — — V
3.0 —
Output LOW Voltage VCC = Min. IOL = 0.1mA — — 0.2 V
VIN = V
IH
or V
IL
IOL = 16mA — 0.2 0.4
IOL = 24mA — 0.3 0.55
VCC = 3.0V
V
IN
= V
IH
or V
Short Circuit Current
Input Hysteresis
(4)
VCC = Max., VO = GND
—
Quiescent Power Supply Current VCC = Max.,
V
IN
= GND or V
IL
CC
IOL = 24mA — 0.3 0.50
(3)
–60
–
— 150
135 –240 mA
—
— 0.1 10
2776 lnk 05
µ
µ
mV
µ
A
A
A
8.6 3
IDT74FCT163501/A/C
3.3V 18-BIT REGISTERED TRANSCEIVER COMMERCIAL TEMPERATURE RANGE
POWER SUPPLY CHARACTERISTICS
Symbol Parameter Test Conditions
∆ICC Quiescent Power Supply Current
VCC = Max. VIN = VCC – 0.6V
(1)
(3)
Min. Typ.
— 2.0 30 µA
TTL Inputs HIGH
ICCD Dynamic Power Supply
(4)
Current
VCC = Max.
Outputs Open
OEAB =
OEBA
CC
= V
IN = VCC
V
IN = GND
V
— 60 100 µA/
or GND
50% Duty Cycle
One Input Toggling
IC Total Power Supply Current
(6)
VCC = Max. VIN = VCC — 0.6 1.0 mA
Outputs Open
CP = 10MHz (CLKAB)
f
IN = GND
V
50% Duty Cycle
OEAB =
OEBA
LEAB = GND
fi = 5MHz
= V
CC
VIN = VCC –0.6V
IN = GND
V
— 0.6 1.0
50% Duty Cycle
One Bit Toggling
VCC = Max.
Outputs Open
CP = 10MHz (CLKAB)
f
IN = VCC
V
VIN = GND
— 3.0 5.0
50% Duty Cycle
OEAB =
OEBA
LEAB = GND
fi = 2.5MHz
= V
CC
IN = VCC –0.6V
V
IN = GND
V
— 3.0 5.3
50% Duty Cycle
Eighteen Bits Toggling
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
3. Per TTL driven input; all other inputs at V
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the I
C = IQUIESCENT + IINPUTS + IDYNAMIC
6. I
IC = ICC + ∆ICC DHNT + ICCD (fCPNCP/2 + fiNi)
CC = Quiescent Current (ICCL, ICCH and ICCZ)
I
CC = Power Supply Current for a TTL High Input
∆I
D
H = Duty Cycle for TTL Inputs High
T = Number of TTL Inputs at DH
N
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
CP = Clock Frequency for Register Devices (Zero for Non-Register Devices)
f
N
CP = Number of Clock Inputs at fCP
fi = Input Frequency
i = Number of Inputs at fi
N
CC = 3.3V, +25°C ambient.
CC or GND.
CC formula. These limits are guaranteed but not tested.
(2)
Max. Unit
MHz
(5)
(5)
2776 tbl 08
8.6 4
IDT74FCT163501/A/C
3.3V 18-BIT REGISTERED TRANSCEIVER COMMERCIAL TEMPERATURE RANGE
(2)
(4)
Max. Min.
(2)
Max. Unit
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
FCT163501 FCT163501A FCT163501C
Symbol Parameter Condition
(1)
Min.
(2)
Max. Min.
fMAX CLKAB or CLKBA frequency CL = 50pF — 100 — 150 — 150 MHz
tPLH
Propagation Delay
Ax to Bx or Bx to Ax
tPHL
tPLH
Propagation Delay
LEBA to Ax, LEAB to Bx
tPHL
tPLH
Propagation Delay
CLKBA to Ax, CLKAB to Bx
tPHL
tPZH
Output Enable Time
OEBA
tPZL
tPHZ
tPLZ
to Ax, OEAB to Bx
Output Disable Time
OEBA
to Ax, OEAB to Bx
tSU Set-up Time, HIGH or LOW
RL = 500Ω 1.5 6.5 1.5 5.1 1.5 4.6 ns
1.5 7.5 1.5 5.6 1.5 5.3 ns
1.5 8.0 1.5 5.6 1.5 5.3 ns
1.5 8.0 1.5 6.0 1.5 5.6 ns
1.5 7.5 1.5 5.6 1.5 5.2 ns
4.0 — 3.0 — 3.0 — ns
Ax to CLKAB, Bx to CLKBA
tH Hold Time, HIGH or LOW
0—0—0—ns
Ax to CLKAB, Bx to CLKBA
tSU Set-up Time
HIGH or LOW
Ax to LEAB,
Bx to LEBA
tH Hold Time HIGH or LOW
Clock
LOW
Clock
HIGH
4.0 — 3.0 — 3.0 — ns
1.5 — 1.5 — 1.5 — ns
1.5 — 1.5 — 1.5 — ns
Ax to LEAB, Bx to LEBA
tW LEAB or LEBA Pulse Width
(5)
HIGH
tW CLKAB or CLKBA Pulse
Width HIGH or LOW
tSK(o) Output Skew
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. Skew between any two outputs, of the same package, switching in the same direction. This parameter is guaranteed by design.
4. Propagation Delays and Enable/Disable times are with V
and Enable/Disable times should be degraded by 20%.
5. This parameter is guaranteed but not tested.
(5)
(3)
3.0 — 3.0 — 3.0 — ns
3.0 — 3.0 — 3.0 — ns
— 0.5 — 0.5 — 0.5 ns
2776 tbl 07
CC = 3.3V ±0.3V, Normal Range. For VCC = 2.7V to 3.6V, Extended Range, all Propagation Delays
8.6 5
IDT74FCT163501/A/C
3.3V 18-BIT REGISTERED TRANSCEIVER COMMERCIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS
V
CC
V
OUT
50pF
C
L
Pulse
Generator
V
IN
D.U.T.
R
T
500
500
←
Open
GND
Ω
Ω
2776 drw 05
SWITCH POSITION
6V
Open Drain
Disable Low
Enable Low
Disable High
Enable High
All Other tests Open
DEFINITIONS:
L= Load capacitance: includes jig and probe capacitance.
C
T = Termination resistance: should be equal to ZOUT of the Pulse
R
Generator.
Test Switch
SET-UP, HOLD AND RELEASE TIMES PULSE WIDTH
DATA
INPUT
TIMING
INPUT
ASYNCHRONOUS CONTROL
PRESET
CLEAR
ETC.
SYNCHRONOUS CONTROL
PRESET
CLEAR
CLOCK ENABLE
ETC.
t
t
REM
H
t
H
t
SU
t
SU
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
LOW-HIGH-LOW
PULSE
HIGH-LOW-HIGH
PULSE
6V
GND
2776 lnk 08
1.5V
t
W
1.5V
2776 drw 07
SAME PHASE
INPUT TRANSITION
OUTPUT
OPPOSITE PHASE
INPUT TRANSITION
t
PLH
t
PLH
t
t
PHL
PHL
2776 drw 06
3V
1.5V
0V
OH
V
1.5V
V
OL
3V
1.5V
0V
2776 drw 08
ENABLE AND DISABLE TIMESPROPAGATION DELAY
ENABLE DISABLE
3V
CONTROL
INPUT
t
PHZ
PLZ
t
0.3V
0.3V
F ≤ 2.5ns; tR ≤ 2.5ns.
t
PZL
OUTPUT
NORMALLY
OUTPUT
NORMALLY
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH.
2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; t
CC is below 3V, input voltage swings should be adjusted not to
3. If V
exceed V
LOW
HIGH
CC.
SWITCH
6V
t
PZH
SWITCH
GND
3V
1.5V
1.5V
0V
1.5V
0V
3V
V
V
0V
2776 drw 09
OL
OH
8.6 6
IDT74FCT163501/A/C
3.3V 18-BIT REGISTERED TRANSCEIVER COMMERCIAL TEMPERATURE RANGE
ORDERING INFORMATION
IDT
Temperature
Range
FCT
X
XXXX
Device
X
Package
Type
PV
PA
PF
163501
163501A
Shrink Small Outline Package (SO56-1)
Thin Shrink Small Outline Package (SO56-2)
Thin Very Small Outline Package (SO56-3)
Non-Inverting 18-Bit Registered Transceiver
Fast Non-Inverting 18-Bit Registered Transceiver
-40°C to +85°C74
2776 drw 10
8.6 7
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