Datasheet IDT74FCT163374APV, IDT74FCT163374APF, IDT74FCT163374APA, IDT74FCT163374PV, IDT74FCT163374CPV Datasheet (Integrated Device Technology)

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Page 1
Integrated Device Technology, Inc.
DESCRIPTION:
The FCT163374/A/C 16-bit edge-triggered D-type regis­ters are built using advanced dual metal CMOS technology. These high-speed, low-power registers are ideal for use as buffer registers for data synchronization and storage. The Output Enable (xOE) and clock (xCLK) controls are organized
to operate each device as two 8-bit registers or one 16-bit register with common clock. Flow-through organization of signal pins facilitates ease of layout. All inputs are designed with hysteresis for improved noise margin.
The inputs of FCT163374/A/C can be driven from either
3.3V or 5V devices. This feature allows the use of these devices as translators in a mixed 3.3V/5V supply system.
3.3V CMOS 16-BIT REGISTER (3-STATE)
IDT74FCT163374/A/C
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE AUGUST 1996
1
FEATURES:
• 0.5 MICRON CMOS Technology
Typical tSK(o) (Output Skew) < 250ps
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0)
• Packages include 25 mil pitch SSOP, 19.6 mil pitch TSSOP and 15.7 mil pitch TVSOP
• Extended commercial range of -40°C to +85°C
•V
CC = 3.3V ±0.3V, Normal Range or
VCC = 2.7 to 3.6V, Extended Range
• CMOS power levels (0.4µW typ. static)
• Rail-to-Rail output swing for increased noise margin
• Low Ground Bounce (0.3V typ.)
• Inputs (except I/O) can be driven by 3.3V or 5V components
1O1
1
OE
1CLK
1D1
2775 drw 01
TO 7 OTHER CHANNELS
C
D
2O1
2
OE
2CLK
2D1
TO 7 OTHER CHANNELS
C
D
2775 drw 02
FUNCTIONAL BLOCK DIAGRAM
8.5
1996 Integrated Device Technology, Inc. DSC-4637/5
Page 2
8.5 2
IDT74FCT163374/A/C
3.3V 16-BIT REGISTER (3-STATE) COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATIONS
1O1
GND
1O3
VCC
1
OE
GND
2O2
GND
V
CC
GND
1O2
1
O4
1
O5
1
O6
1
O7
1
O8
2
O1
2
O3
2
O4
2
O5
2
O7
2
O8
2
O6
2OE
1CLK 1D1
1
D2
GND
1D3
1
D4
VCC
1
D5
1
D6
1
D7
1
D8
2
D1
2
D2
2
D3
2
D4
VCC
2
D5
2
D7
2
D8
2
D6
2
CLK
GND
GND
GND
2775 drw 03
39
29
30
31
32
33
34
35
36
37
38
25
26
27
28
48 47
41
42
43
44
45
46
40
1 2 3 4 5 6 7 8 9 10
12 13 14 15 16 17 18 19 20
11
21 22 23 24
SSOP/
TSSOP/TVSOP
TOP VIEW
SO48-1 SO48-2 SO48-3
PIN DESCRIPTION
2775 tbl 01
Pin Names Description
xDx Data Inputs
xCLK Clock Inputs
xOx 3-State Outputs. x
OE
3-State Output Enable Input (Active LOW)
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol Description Max. Unit
VTERM
(2)
Terminal Voltage with Respect to GND
–0.5 to +4.6 V
VTERM
(3)
Terminal Voltage with Respect to GND
–0.5 to +7.0 V
VTERM
(4)
Terminal Voltage with Respect to GND
–0.5 to
V
CC + 0.5
V
TSTG Storage Temperature –65 to +150 °C IOUT DC Output Current –60 to +60 mA
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT­INGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for ex­tended periods may affect reliability.
2. Vcc terminals.
3. Input terminals.
4. Output and I/O terminals.
2775 lnk 03
FUNCTION TABLE
(1)
NOTE: 2775 tbl 02
1. H = HIGH Voltage Level
L = LOW Voltage Level X = Don’t Care Z = High Impedance = LOW-to-HIGH transition
Inputs Outputs
Function xDx xCLK x
OE
OE
xOx
Hi-Z X L H Z
XHHZ
Load L LL Register H LH
L↑HZ
H↑HZ
CAPACITANCE (TA = +25°C, f = 1.0MHz)
Symbol Parameter
(1)
Conditions Typ. Max. Unit
CIN Input
Capacitance
VIN = 0V 3.5 6.0 pF
COUT Output
Capacitance
VOUT = 0V 3.5 8.0 pF
NOTE:
1. This parameter is measured at characterization but not tested.
2775 lnk 04
Page 3
8.5 3
IDT74FCT163374/A/C
3.3V 16-BIT REGISTER (3-STATE) COMMERCIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Commercial: T
A = –40°C to +85°C, VCC = 2.7V to 3.6V
2775 lnk 05
Symbol Parameter Test Conditions
(1)
Min. Typ.
(2)
Max. Unit
V
IH
Input HIGH Level (Input pins) Guaranteed Logic HIGH Level 2.0 5.5 V Input HIGH Level (I/O pins) 2.0 VCC+0.5
V
IL
Input LOW Level Guaranteed Logic LOW Level –0.5
0.8 V
(Input and I/O pins)
I
I H
Input HIGH Current (Input pins) VCC = Max. VI = 5.5V
±
1
µ
A
Input HIGH Current (I/O pins) VI = V
CC
±
1
I
I L
Input LOW Current (Input pins) VI = GND
±
1
Input LOW Current (I/O pins) VI = GND
±
1
I
OZH
High Impedance Output Current VCC = Max. VO = V
CC
±
1
µ
A
I
OZL
(3-State Output pins) VO = GND
±
1
V
IK
Clamp Diode Voltage VCC = Min., I
IN
= –18mA
0.7
1.2 V
I
ODH
Output HIGH Current VCC = 3.3V, V
IN
= V
IH
or V
IL, VO
= 1.5V
(3)
–36 –60 –110 mA
I
ODL
Output LOW Current VCC = 3.3V, V
IN
= V
IH
or V
IL, VO
= 1.5V
(3)
50 90 200 mA
V
OH
Output HIGH Voltage VCC = Min. IOH = –0.1mA V
CC
0.2 V
VIN = V
IH
or V
IL
IOH = –3mA 2.4 3.0
VCC = 3.0V V
IN
= V
IH
or V
IL
IOH = –8mA 2.4
(5)
3.0
V
OL
Output LOW Voltage VCC = Min. IOL = 0.1mA 0.2 V
VIN = V
IH
or V
IL
IOL = 16mA 0.2 0.4 IOL = 24mA 0.3 0.55
VCC = 3.0V V
IN
= V
IH
or V
IL
IOL = 24mA 0.3 0.50
I
OS
Short Circuit Current
(4)
VCC = Max., VO = GND
(3)
–60
135 –240 mA
V
H
Input Hysteresis
150
mV
I
CCL
I
CCH
Quiescent Power Supply Current VCC = Max.,
V
IN
= GND or V
CC
0.1 10
µ
A
I
CCZ
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 3.3V, +25°C ambient.
3. Not more than one output should be tested at one time. Duration of the test should not exceed one second.
4. This parameter is guaranteed but not tested.
5. V
OH = VCC –0.6V at rated current.
Page 4
8.5 4
IDT74FCT163374/A/C
3.3V 16-BIT REGISTER (3-STATE) COMMERCIAL TEMPERATURE RANGE
POWER SUPPLY CHARACTERISTICS
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC = 3.3V, +25°C ambient.
3. Per TTL driven input; all other inputs at V
CC or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the I
CC formula. These limits are guaranteed but not tested.
6. I
C = IQUIESCENT + IINPUTS + IDYNAMIC
IC = ICC + ICC DHNT + ICCD (fCPNCP/2 + fiNi) I
CC = Quiescent Current (ICCL, ICCH and ICCZ)
I
CC = Power Supply Current for a TTL High Input
D
H = Duty Cycle for TTL Inputs High
N
T = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL) f
CP = Clock Frequency for Register Devices (Zero for Non-Register Devices)
N
CP = Number of Clock Inputs at fCP
fi = Input Frequency N
i = Number of Inputs at fi
2775 tbl 07
Symbol Parameter Test Conditions
(1)
Min. Typ.
(2)
Max. Unit
I
CC
Quiescent Power Supply Current VCC = Max. VIN = V
CC
– 0.6V
(3)
2.0 30
µ
A
I
CCD
Dynamic Power Supply Current
(4)
VCC = Max. Outputs Open xOE = GND 50% Duty Cycle One Input Toggling
VIN = VCC V
IN
= GND
—5075
µ
A/
MHz
I
C
Total Power Supply Current
(6)
VCC = Max. Outputs Open f
CP
= 10MHz
50% Duty Cycle
V
IN
= V
CC
V
IN
= GND
0.5 0.8 mA
xOE = GND fi = 5MHz 50% Duty Cycle One Bit Toggling
VIN = V
CC
–0.6V
V
IN
= GND
0.5 0.8
VCC = Max. Outputs Open f
CP
= 10MHz
50% Duty Cycle
V
IN
= V
CC
V
IN
= GND
2.5 3.8
(5)
xOE = GND fi = 2.5MHz 50% Duty Cycle Sixteen Bits Toggling
VIN = V
CC
–0.6V
V
IN
= GND
2.5 4.0
(5)
Page 5
8.5 5
IDT74FCT163374/A/C
3.3V 16-BIT REGISTER (3-STATE) COMMERCIAL TEMPERATURE RANGE
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
(4)
FCT163374 FCT163374A FCT163374C
Symbol Parameter Condition
(1)
Min.
(2)
Max. Min.
(2)
Max. Min.
(2)
Max. Unit
tPLH tPHL
Propagation Delay xCLK to xOx
CL = 50pF
R
L = 500
2.0 10.0 2.0 6.5 2.0 5.2 ns
tPZH tPZL
Output Enable Time 1.5 12.5 1.5 6.5 1.5 5.5 ns
tPHZ tPLZ
Output Disable Time 1.5 8.0 1.5 5.5 1.5 5.0 ns
tSU Set-up Time HIGH
or LOW, xDx to xCLK
2.0 2.0 2.0 ns
tH Hold Time HIGH
or LOW, xDx to xCLK
1.5 1.5 1.5 ns
tW xCLK Pulse Width
HIGH or LOW
7.0 5.0 5.0 ns
tSK(o) Output Skew
(3)
0.5 0.5 0.5 ns
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. Skew between any two outputs, of the same package, switching in the same direction. This parameter is guaranteed by design.
4. Propagation Delay and Enable/Disable times are with V
CC = 3.3V ±0.3V, Normal Range. For VCC = 2.7V to 3.6V, Extended Range, all Propagation Delays
and Enable/Disable times should be degraded by 20%.
2775 tbl 08
Page 6
8.5 6
IDT74FCT163374/A/C
3.3V 16-BIT REGISTER (3-STATE) COMMERCIAL TEMPERATURE RANGE
DEFINITIONS:
C
L= Load capacitance: includes jig and probe capacitance.
R
T = Termination resistance: should be equal to ZOUT of the Pulse
Generator.
3V
1.5V 0V
3V
1.5V 0V
3V
1.5V 0V
3V
1.5V
0V
DATA
INPUT
TIMING
INPUT
ASYNCHRONOUS CONTROL
PRESET
CLEAR
ETC.
SYNCHRONOUS CONTROL
t
SU
t
H
t
REM
t
SU
t
H
HIGH-LOW-HIGH
PULSE
LOW-HIGH-LOW
PULSE
t
W
1.5V
1.5V
SAME PHASE
INPUT TRANSITION
3V
1.5V 0V
1.5V
V
OH
t
PLH
OUTPUT
OPPOSITE PHASE
INPUT TRANSITION
3V
1.5V 0V
t
PLH
t
PHL
t
PHL
V
OL
CONTROL
INPUT
3V
1.5V 0V
3V
0V
OUTPUT
NORMALLY
LOW
OUTPUT
NORMALLY
HIGH
SWITCH 6V
SWITCH GND
V
OL
0.3V
0.3V
t
PLZ
t
PZL
t
PZH
t
PHZ
3V
0V
1.5V
1.5V
ENABLE DISABLE
V
OH
PRESET
CLEAR
CLOCK ENABLE
ETC.
Pulse
Generator
R
T
D.U.T.
V
CC
V
IN
C
L
V
OUT
50pF
500
500
GND
6V
Open
TEST CIRCUITS AND WAVEFORMS TEST CIRCUITS FOR ALL OUTPUTS
ENABLE AND DISABLE TIMESPROPAGATION DELAY
SET-UP, HOLD AND RELEASE TIMES PULSE WIDTH
SWITCH POSITION
2775 drw 09
2775 drw 07
2775 drw 05
2775 drw 06
2775 drw 08
Test Switch
Open Drain
Disable Low
Enable Low
6V
Disable High
Enable High
GND
All Other tests Open
2775 lnk 09
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
2. Pulse Generator for All Pulses: Rate 1.0MHz; t
F ≤ 2.5ns; tR 2.5ns.
3. If V
CC is below 3V, input voltage swings should be adjusted not to
exceed V
CC.
Page 7
8.5 7
IDT74FCT163374/A/C
3.3V 16-BIT REGISTER (3-STATE) COMMERCIAL TEMPERATURE RANGE
ORDERING INFORMATION
IDT XX
Temp. Range
XXXX
Device TypeXPackage
PV PA PF
374 374A 374C
Shrink Small Outline Package (SO48-1) Thin Shrink Small Outline Package (SO48-2) Thin Very Small Outline Package (SO48-3)
Non-Inverting 16-Bit Register
74
–40°C to +85°C
2775 drw 10
FCT
163
16-Bit 3.3 Volt
X
Family
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