Datasheet IDT74FCT16H501CTPFB, IDT74FCT16H501CTPF, IDT74FCT16H501CTPAB, IDT74FCT16H501CTPA, IDT74FCT16H501CTEB Datasheet (Integrated Device Technology)
...
Integrated Device Technology, Inc.
FAST CMOS
18-BIT REGISTERED
TRANSCEIVER
IDT54/74FCT16501AT/CT/ET
IDT54/74FCT162501AT/CT/ET
IDT54/74FCT162H501AT/CT/ET
FEATURES:
• Common features:
– 0.5 MICRON CMOS Technology
– High-speed, low-power CMOS replacement for
ABT functions
– Typical tSK(o) (Output Skew) < 250ps
– Low input and output leakage ≤ 1µA (max.)
– ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
– Packages include 25 mil pitch SSOP, 19.6 mil pitch
TSSOP, 15.7 mil pitch TVSOP and 25 mil pitch Cerpack
– Extended commercial range of -40°C to +85°C
• Features for FCT16501AT/CT/ET:
– High drive outputs (-32mA I
OH, 64mA IOL)
– Power off disable outputs permit “live insertion”
– Typical VOLP (Output Ground Bounce) < 1.0V at
VCC = 5V, TA = 25°C
• Features for FCT162501AT/CT/ET:
– Balanced Output Drivers: ±24mA (commercial),
±16mA (military)
– Reduced system switching noise
– Typical VOLP (Output Ground Bounce) < 0.6V at
VCC = 5V,TA = 25°C
• Features for FCT162H501AT/CT/ET:
– Bus Hold retains last active bus state during 3-state
– Eliminates the need for external pull up resistors
DESCRIPTION:
The FCT16501AT/CT/ET and FCT162501AT/CT/ET 18-
bit registered transceivers are built using advanced dual metal
FUNCTIONAL BLOCK DIAGRAM
OEAB
CLKBA
LEBA
CMOS technology. These high-speed, low-power 18-bit registered bus transceivers combine D-type latches and D-type
flip-flops to allow data flow in transparent, latched and clocked
modes. Data flow in each direction is controlled by outputenable (OEAB and
OEBA
), latch enable (LEAB and LEBA)
and clock (CLKAB and CLKBA) inputs. For A-to-B data flow,
the device operates in transparent mode when LEAB is HIGH.
When LEAB is LOW, the A data is latched if CLKAB is held at
a HIGH or LOW logic level. If LEAB is LOW, the A bus data
is stored in the latch/flip-flop on the LOW-to-HIGH transition of
CLKAB. OEAB is the output enable for the B port. Data flow
from the B port to the A port is similar but requires using
OEBA
LEBA and CLKBA. Flow-through organization of signal pins
simplifies layout. All inputs are designed with hysteresis for
improved noise margin.
The FCT16501AT/CT/ET are ideally suited for driving
high-capacitance loads and low-impedance backplanes. The
output buffers are designed with power off disable capability
to allow "live insertion" of boards when used as backplane
drivers.
The FCT162501AT/CT/ET have balanced output drive
with current limiting resistors. This offers low ground bounce,
minimal undershoot, and controlled output fall times–reducing
the need for external series terminating resistors. The
FCT162501AT/CT/ET are plug-in replacements for the
FCT16501AT/CT/ET and ABT16501 for on-board bus interface applications.
The FCT162H501AT/CT/ET have "Bus Hold" which retains the input's last state whenever the input goes to high
impedance. This prevents "floating" inputs and eliminates the
need for pull-up/down resistors.
,
OEBA
CLKAB
LEAB
C
D
C
D
2547 drw 01
1
B
A1
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
C
D
C
D
TO 17 OTHER CHANNELS
MILITARY AND COMMERCIAL TEMPERATURE RANGES AUGUST 1996
1996 Integrated Device Technology, Inc. 5.10 DSC-2547/8
1
IDT54/74FCT16501AT/CT/ET, 162501AT/CT/ET, 162H501AT/CT/ET
FAST CMOS 18-BIT REGISTERED TRANSCEIVER MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
OEAB
LEAB
A
GND
A
A3
VCC
A4
A5
A
GND
A7
A8
A9
A
A11
A12
GND
A13
A14
A
VCC
A16
A
GND
A18
OEBA
LEBA
1
2
3
1
4
5
2
6
7
8
9
10
6
11
12
13
14
SO56-1
SO56-2
10
15
SO56-3
16
17
18
19
20
15
21
22
23
17
24
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
3225
31
30
29
GND
CLKAB
B1
GND
B
2
B3
VCC
B
4
B5
B6
GND
B7
B8
B9
B10
B11
12
B
GND
B13
B14
B15
VCC
16
B
B17
GND
B
18
CLKBA
GND
OEAB
LEAB
A
GND
A
A3
VCC
A4
A5
A
GND
A7
A8
A9
A
A11
A12
GND
A13
A14
A
VCC
A16
A
GND
A18
OEBA
LEBA
1
2
6
10
15
17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
26
27
28
E56-1
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
3225
31
30
29
GND
CLKAB
B1
GND
B
2
B3
VCC
B
4
B5
B6
GND
B7
B8
B9
B10
B11
B
12
GND
B13
B14
B15
VCC
B
16
B17
GND
18
B
CLKBA
GND
SSOP/
TSSOP/TVSOP
TOP VIEW
2547 drw 02
CERPACK
2547 drw 03
TOP VIEW
5.10 2
IDT54/74FCT16501AT/CT/ET, 162501AT/CT/ET, 162H501AT/CT/ET
FAST CMOS 18-BIT REGISTERED TRANSCEIVER MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN DESCRIPTION
Pin Names Description
OEAB A-to-B Output Enable Input
OEBA
LEAB A-to-B Latch Enable Input
LEBA B-to-A Latch Enable Input
CLKAB A-to-B Clock Input
CLKBA B-to-A Clock Input
Ax A-to-B Data Inputs or B-to-A 3-State Outputs
Bx B-to-A Data Inputs or A-to-B 3-State Outputs
NOTE:
1. On FCT16xH501T these pins have “Bus Hold”. All other pins are standard
inputs, outputs or I/Os.
ABSOLUTE MAXIMUM RATINGS
Symbol Description Max. Unit
(2)
VTERM
(3)
VTERM
TSTG Storage Temperature –65 to +150 °C
IOUT DC Output Current –60 to +120 mA
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
2. All device terminals except FCT162XXXT Output and I/O terminals.
3. Output and I/O terminals for FCT162XXXT.
B-to-A Output Enable Input (Active LOW)
Terminal Voltage with Respect to
GND
Terminal Voltage with Respect to
GND
(1)
(1)
2547 tbl 01
(1)
–0.5 to +7.0 V
–0.5 to
CC +0.5
V
2547 lnk 03
V
FUNCTION TABLE
(1,4)
Inputs Outputs
OEAB LEAB CLKAB Ax Bx
LXX XZ
HHX LL
HHX HH
HL↑ LL
HL↑ HH
HLL XB
HLH XB
NOTES: 2547 tbl 02
1. A-to-B data flow is shown. B-to-A data flow is similar but uses
LEBA, and CLKBA.
2. Output level before the indicated steady-state input conditions were
established.
3. Output level before the indicated steady-state input conditions were
established, provided that CLKAB was HIGH before LEAB went LOW.
4. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
Z = High-impedance
↑ = LOW-to-HIGH Transition
(2)
(3)
OEBA
CAPACITANCE (TA = +25°C, f = 1.0MHz)
Symbol Parameter
CIN Input
Capacitance
CI/O I/O
Capacitance
NOTE:
1. This parameter is measured at characterization but not tested.
(1)
Conditions Typ. Max. Unit
VIN = 0V 3.5 6.0 pF
VOUT = 0V 3.5 8.0 pF
2547 lnk 04
,
5.10 3
IDT54/74FCT16501AT/CT/ET, 162501AT/CT/ET, 162H501AT/CT/ET
FAST CMOS 18-BIT REGISTERED TRANSCEIVER MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE (STANDARD PARTS)
Following Conditions Apply Unless Otherwise Specified:
Commercial: TA = –40°C to +85°C, VCC = 5.0V ± 10%; Military: TA = –55°C to +125°C, VCC = 5.0V ± 10%
Symbol Parameter Test Conditions
(1)
Min. Typ.
VIH Input HIGH Level Guaranteed Logic HIGH Level 2.0 — — V
VIL Input LOW Level Guaranteed Logic LOW Level — — 0.8 V
II H Input HIGH Current (Input pins)
Input HIGH Current (I/O pins)
II L Input LOW Current (Input pins)
Input LOW Current (I/O pins)
(5)
VCC = Max. VI = VCC — — ±1 µA
(5)
(5)
VI = GND — — ±1
(5)
— — ±1
— — ±1
IOZH High Impedance Output Current VCC = Max. VO = 2.7V — — ±1 µA
IOZL (3-State Output pins)
(5)
VO = 0.5V — — ±1
VIK Clamp Diode Voltage VCC = Min., IIN = –18mA — –0.7 –1.2 V
IOS Short Circuit Current VCC = Max., VO = GND
(3)
–80 –140 –225 mA
VH Input Hysteresis — — 100 — mV
ICCL
Quiescent Power Supply Current VCC = Max., VIN = GND or VCC — 5 500 µA
ICCH
ICCZ
(2)
Max. Unit
2547 lnk 05
OUTPUT DRIVE CHARACTERISTICS FOR FCT16501T
Symbol Parameter Test Conditions
IO Output Drive Current VCC = Max., VO = 2.5V
(3)
(1)
Min. Typ.
–50 —–180 mA
VOH Output HIGH Voltage VCC = Min. IOH = –3mA 2.5 3.5 — V
VIN = VIH or VIL IOH = –12mA MIL.
VOL Output LOW Voltage VCC = Min.
IN = VIH or VIL
V
IOFF Input/Output Power Off Leakage
(5)
VCC = 0V, VIN or VO ≤ 4.5V — — ±1 µA
OH = –15mA COM'L.
I
IOH = –24mA MIL.
OH = –32mA COM'L.
I
IOL = 48mA MIL.
OL = 64mA COM'L.
I
2.4 3.5 — V
2.0 3.0 — V
(4)
— 0.2 0.55 V
(2)
Max. Unit
2547 lnk 06
OUTPUT DRIVE CHARACTERISTICS FOR FCT162501T
Symbol Parameter Test Conditions
IODL Output LOW Current VCC = 5V, VIN = VIH or VIL, VOUT = 1.5V
IODH Output HIGH Current VCC = 5V, VIN = VIH or V IL,
VOH Output HIGH Voltage VCC = Min.
V
IN = VIH or VIL
VOL Output LOW Voltage VCC = Min.
V
IN = VIH or VIL
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient.
3. Not more than one output should be tested at one time. Duration of the test should not exceed one second.
4. Duration of the condition can not exceed one second.
5. The test limit for this parameter is ± 5µA at T
A = –55°C.
(1)
(3)
VOUT = 1.5V
(3)
IOH = –16mA MIL.
I
OH = –24mA COM'L.
IOL = 16mA MIL.
I
OL = 24mA COM'L.
Min. Typ.
60 115 200 mA
–60 –115 –200 mA
2.4 3.3 — V
— 0.3 0.55 V
(2)
Max. Unit
2547 lnk 07
5.10 4
IDT54/74FCT16501AT/CT/ET, 162501AT/CT/ET, 162H501AT/CT/ET
FAST CMOS 18-BIT REGISTERED TRANSCEIVER MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE (BUS HOLD)
Following Conditions Apply Unless Otherwise Specified:
Commercial: TA = –40°C to +85°C, VCC = 5.0V ± 10%; Military: TA = –55°C to +125°C, VCC = 5.0V ± 10%
Symbol Parameter Test Conditions
V
IH
V
IL
I
I H
Input HIGH Level Guaranteed Logic HIGH Level 2.0 —
Input LOW Level Guaranteed Logic LOW Level — — 0.8 V
(5)
(5)
VCC = Max. VI = V
Input Standard Input
HIGH Standard I/O
(4)
Current
Bus-Hold Input — —
(1)
CC
Min. Typ.
——
——
Bus-Hold I/O — —
I
I L
Input Standard Input
LOW Standard I/O
(4)
Current
Bus-Hold Input — —
(5)
(5)
——
VI = GND — —
Bus-Hold I/O — —
I
BHH
I
BHL
I
OZH
I
OZL
V
IK
I
OS
V
H
I
CCL
I
CCH
I
CCZ
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient.
3. Not more than one output should be tested at one time. Duration of the test should not exceed one second.
4. Pins with Bus Hold are identified in the pin description.
5. The test limit for this parameter is ± 5µA at T
6. Does not include Bus Hold I/O pins.
Bus Hold Bus-Hold Input VCC = Min. VI = 2.0V –50 — —
Sustain
Current
(4)
I
= 0.8V +50 — —
V
High Impedance Output Current VCC = Max. VO = 2.7V —
(3-State Output pins)
Clamp Diode Voltage VCC = Min., I
Short Circuit Current VCC = Max., VO = GND
Input Hysteresis
Quiescent Power Supply Current VCC = Max., VIN = GND or V
(5,6)
A = –55°C.
IN
= –18mA —
—
VO = 0.5V —
(3)
CC
–80–140–225 mA
— 100
— 5 500
(2)
Max. Unit
—
±
1
±
1
±
100
±
100
±
1
±
1
±
100
±
100
—
—
–
0.7–1.2 V
±
1
±
1
—
V
µ
A
µ
A
µ
A
mV
µ
A
2547 lnk 08
5.10 5
IDT54/74FCT16501AT/CT/ET, 162501AT/CT/ET, 162H501AT/CT/ET
FAST CMOS 18-BIT REGISTERED TRANSCEIVER MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
Symbol Parameter Test Conditions
CC Quiescent Power Supply VCC = Max. — 0.5 1.5 mA
∆I
Current TTL Inputs HIGH V
ICCD Dynamic Power Supply Current
IN = 3.4V
(4)
VCC = Max., Outputs Open VIN = VCC — 75 120 µA/
OEAB =
(3)
OEBA
= V
CC or GND VIN = GND MHz
(1)
Min. Typ.
One Input Toggling
50% Duty Cycle
I
C Total Power Supply Current
(6)
VCC = Max., Outputs Open VIN = VCC — 0.8 1.7 mA
f
CP = 10MHz (CLKAB) VIN = GND
50% Duty Cycle
OEAB =
OEBA
= V
CC
LEAB = GND VIN = 3.4V — 1.3 3.2
One Bit Toggling V
f
i = 5MHz
IN = GND
50% Duty Cycle
V
CC = Max., Outputs Open VIN = VCC — 3.8 6.5
fCP = 10MHz (CLKAB) VIN = GND
50% Duty Cycle
OEAB =
OEBA
= V
CC
LEAB = GND VIN = 3.4V — 8.5 20.8
Eighteen Bits Toggling VIN = GND
f
i = 2.5MHz
50% Duty Cycle
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
3. Per TTL driven input (V
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the I
C = IQUIESCENT + IINPUTS + IDYNAMIC
6. I
IC = ICC + ∆ICC DHNT + ICCD (fCPNCP/2 + fiNi)
I
CC = Quiescent Current (ICCL, ICCH and ICCZ)
CC = Power Supply Current for a TTL High Input (VIN = 3.4V)
∆I
D
H = Duty Cycle for TTL Inputs High
T = Number of TTL Inputs at DH
N
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
CP = Clock Frequency for Register Devices (Zero for Non-Register Devices)
f
N
CP = Number of Clock Inputs at fCP
fi = Input Frequency
i = Number of Inputs at fi
N
CC = 5.0V, +25°C ambient.
IN = 3.4V). All other inputs at VCC or GND.
CC formula. These limits are guaranteed but not tested.
(2)
Max. Unit
(5)
(5)
2547 tbl 09
5.10 6
IDT54/74FCT16501AT/CT/ET, 162501AT/CT/ET, 162H501AT/CT/ET
FAST CMOS 18-BIT REGISTERED TRANSCEIVER MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
FCT16501AT/162501AT FCT16501CT/162501CT FCT16501ET/162501ET
Com'l. Mil. Com'l. Mil. Com'l. Mil.
(1)
Symbol Parameter Condition
fMAX CLKAB or CLKBA frequency
tPLH
Propagation Delay
Ax to Bx or Bx to Ax
tPHL
tPLH
Propagation Delay
LEBA to Ax, LEAB to Bx
tPHL
tPLH
Propagation Delay
CLKBA to Ax, CLKAB to Bx
tPHL
tPZH
Output Enable Time
OEBA
tPZL
tPHZ
tPLZ
to Ax, OEAB to Bx
Output Disable Time
OEBA
to Ax, OEAB to Bx
(4)
CL = 50pF — 150 — 150 — 150 — 150 — 150 — — MHz
RL = 500Ω 1.5 5.1 1.5 5.6 1.5 4.6 1.5 4.6 1.5 3.8 — — ns
tSU Set-up Time, HIGH or LOW
(2)
Min.
Max. Min.
1.5 5.6 1.5 6.0 1.5 5.3 1.5 5.6 1.5 4.2 — — ns
1.5 5.6 1.5 6.0 1.5 5.3 1.5 5.4 1.5 4.2 — — ns
1.5 6.0 1.5 6.4 1.5 5.6 1.5 6.0 1.5 4.8 — — ns
1.5 5.6 1.5 6.0 1.5 5.2 1.5 5.6 1.5 5.2 — — ns
3.0 — 3.0 — 3.0 — 3.0 — 2.4 — — — ns
Ax to CLKAB, Bx to CLKBA
tH Hold Time HIGH or LOW
0—0—0—0—0———ns
Ax to CLKAB, Bx to CLKBA
tSU Set-up Time
HIGH or LOW
Ax to LEAB,
Bx to LEBA
tH Hold Time, HIGH or LOW
Clock
LOW
Clock
HIGH
3.0 — 3.0 — 3.0 — 3.0 — 2.0 — — — ns
1.5 — 1.5 — 1.5 — 1.5 — 1.5 — — — ns
1.5 — 1.5 — 1.5 — 1.5 — 0.5 — — — ns
Ax to LEAB, Bx to LEBA
tW LEAB or LEBA Pulse Width
(4)
HIGH
tW CLKAB or CLKBA Pulse Width
HIGH or LOW
tSK(o) Output Skew
NOTES: 2547 tbl 10
1. See test circuits and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
4. This parameter is guaranteed but not tested.
(4)
(3)
3.0 — 3.0 — 3.0 — 3.0 — 3.0 — — — ns
3.0 — 3.0 — 3.0 — 3.0 — 3.0 — — — ns
— 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — — ns
(2)
Max. Min.
(2)
Max. Min.
(2)
Max. Min.
(2)
Max. Min.
(2)
Max. Unit
5.10 7
IDT54/74FCT16501AT/CT/ET, 162501AT/CT/ET, 162H501AT/CT/ET
FAST CMOS 18-BIT REGISTERED TRANSCEIVER MILITARY AND COMMERCIAL TEMPERATURE RANGES
TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS
V
CC
7.0V
SWITCH POSITION
Test Switch
Open Drain
Disable Low
Enable Low
All Other Tests
Generator.
Pulse
Generator
500
Ω
V
V
IN
OUT
D.U.T.
50pF
500
T
R
C
L
Ω
2547 drw 04
DEFINITIONS:
C
L= Load capacitance: includes jig and probe capacitance.
T = Termination resistance: should be equal to ZOUT of the Pulse
R
SET-UP, HOLD AND RELEASE TIMES PULSE WIDTH
DATA
INPUT
TIMING
INPUT
ASYNCHRONOUS CONTROL
PRESET
CLEAR
ETC.
SYNCHRONOUS CONTROL
PRESET
CLEAR
CLOCK ENABLE
ETC.
t
t
REM
H
t
H
t
SU
t
SU
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
2547 drw 05
LOW-HIGH-LOW
PULSE
HIGH-LOW-HIGH
PULSE
Closed
Open
2547 lnk 11
1.5V
t
W
1.5V
2547 drw 06
SAME PHASE
INPUT TRANSITION
OUTPUT
OPPOSITE PHASE
INPUT TRANSITION
t
PLH
t
PLH
t
t
PHL
PHL
3V
1.5V
0V
V
OH
1.5V
V
OL
3V
1.5V
0V
2547 drw 07
ENABLE AND DISABLE TIMESPROPAGATION DELAY
ENABLE DISABLE
3V
CONTROL
INPUT
t
PHZ
PLZ
t
F ≤ 2.5ns; tR ≤ 2.5ns
t
PZL
OUTPUT
NORMALLY
OUTPUT
NORMALLY
HIGH
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH
2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; t
LOW
SWITCH
CLOSED
t
PZH
SWITCH
OPEN
3.5V
1.5V
1.5V
0V
0.3V
0.3V
1.5V
0V
3.5V
V
V
0V
OL
OH
2547 drw 08
5.10 8
IDT54/74FCT16501AT/CT/ET, 162501AT/CT/ET, 162H501AT/CT/ET
FAST CMOS 18-BIT REGISTERED TRANSCEIVER MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
X
IDT
Temperature
Range
FCT
X
Drive
X
Bus Hold
XXXX
Device TypeXPackageXProcess
Blank
B
PV
PA
PF
E
501AT
501CT
501ET
Blank
H
16
162
54
74
Commercial
MIL-STD-883, Class B
Shrink Small Outline Package (SO56-1)
Thin Shrink Small Outline Package (SO56-2)
Thin Very Small Outline Package (SO56-3)
CERPACK (E56-1)
Non-Inverting 18-Bit Registered Transceiver
Standard
Bus Hold
16-Bit High Drive
16-Bit Balanced Drive
–55°C to +125°C
–40°C to +85°C
2547 drw 09
5.10 9
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