Datasheet IDT54FCT162H272AT, IDT54FCT162H272CT, IDT54FCT162H272ET, IDT74FCT162H272AT, IDT74FCT162H272CT Datasheet (Integrated Device Technology)

Integrated Device Technology, Inc.

FAST CMOS
12-BIT SYNCHRONOUS
BUS EXCHANGER

IDT54/74FCT162H272AT/CT/ET

FEATURES:

• 0.5 MICRON CMOS Technology

• Typical tSK(o) (Output Skew) < 250ps

• Low input and output leakage ≤ 1µA (max.)

• ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)

• Packages include 25 mil pitch SSOP, 19.6 mil pitch TSSOP,

15.7 mil pitch TVSOP and 25 mil pitch Cerpack

• Extended commercial range of -40°C to +85°C

• Balanced Output Drivers: ±24mA (commercial)

±16mA (military)

• Reduced system switching noise

• Typical V

OLP (Output Ground Bounce) < 0.6V at

VCC = 5V, TA = 25°C

• Bus Hold retains last active bus state during 3-state

• Eliminates the need for external pull up resistors

DESCRIPTION:

The FCT162H272AT/CT/ET synchronous tri-port bus ex-

changers are high-speed, bidirectional,12-bit, registered, bus

FUNCTIONAL BLOCK DIAGRAM

multiplexers for use in synchronous memory interleaving
applications. All registers have a common clock and use a
clock enable (CExxx) on each data register to control data

sequencing. The output enables and mux select (

OEA, OEB

and SEL) are also under synchronous control allowing direc­tion changes to be edge triggered events.

The tri-port bus exchanger has three 12-bit ports. Data may
be transferred between the A port and either/both of the B
ports. The clock enable (

CE1B, CE2B, CEA1B

and

CEA2B

inputs control the data storage. Both B ports have a common
output enable (

OEB

) to aid in synchronously loading the B

registers from the B port.

The FCT162H272AT/CT/ET have balanced output drive
with current limiting resistors. This offers low ground bounce,
minimal undershoot, and controlled output fall times-reducing
the need for external series terminating resistors.

The FCT162H272AT/CT/ET have "Bus Hold" which re­tains the input's last state whenever the input goes to high
impedance. This prevents "floating" inputs and eliminates the
need for pull-up/down resistors.

)

CEA1B

CLK

CE1B

SEL
OEB
OEA

A

1:12

CE2B

CEA2B

12

CONTROL

REGISTER

12

12

CE

A-1B

REGISTER

D

CE

REGISTER

Q

12

1

M
U

X

0

CE

REGISTER

Q

12

CE

REGISTER

D

1B-A

2B-A

A-2B

Q

12

D

D

Q

12

12

12

1B1:12

2B1:12

3071 drw 01

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES AUGUST 1996

1996 Integrated Device Technology, Inc. 5.5 DSC-3071/3

1

IDT54/74FCT162H272AT/CT/ET
FAST CMOS 12-BIT SYNCHRONOUS TRI-PORT BUS EXCHANGER MILITARY AND COMMERCIAL TEMPERATURES RANGES

PIN CONFIGURATIONS

CEA1B
CEA2B

2B3

GND

2B
2B1

VCC

A1
A2
A3

GND

A
A5
A6
A7
A8
A9

GND

A10
A11
A

VCC

1B1
1B2

GND

1B

OEA

SEL

1
2
3
4

2

5
6
7
8
9
10
11

4

12
13
14

SO56-1
SO56-2

15

SO56-3
16
17
18
19
20

12

21
22
23
24
25

3

26

27

28

SSOP/

56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29

CE1B
CE2B
2B
GND
2B
2B6
VCC
2B7
2B8
2B9
GND
2B
2B11
2B12
1B12
1B11
1B10
GND
1B
1B8
1B7
VCC
1B6
1B5
GND
1B
OEB
CLK

3071 drw 02

4

5

10

9

4

CEA1B
CEA2B

2B

GND

2B
2B1
VCC

A1
A2
A

GND

A4
A5
A6
A
A8
A9

GND

A10
A11

A
VCC
1B1
1B

GND

1B3

OEA

SEL

3

2

3

7

12

2

TSSOP/TVSOP

TOP VIEW

1
2

3
4
5
6
7
8
9
10
11
12
13
14

E56-1
15
16
17
18
19
20
21
22
23
24

26
27
28

CERPACK
TOP VIEW

56
55

54
53
52
51
50
49

48

47
46
45
44

43

42
41
40
39
38
37
36
35
34
33
3225
31
30
29

CE1B
CE2B

2B4
GND
2B

5

2B6
VCC

7

2B
2B8
2B9
GND
2B10
2B11
2B12
1B12
1B11
1B

10

GND
1B9
1B8
1B7
VCC
1B

6

1B5
GND

4

1B
OEB

CLK

3071 drw 03

5.5 2

IDT54/74FCT162H272AT/CT/ET
FAST CMOS 12-BIT SYNCHRONOUS TRI-PORT BUS EXCHANGER MILITARY AND COMMERCIAL TEMPERATURES RANGES

PIN DESCRIPTION

Signal I/O Description

A

(1:12) I/O Bidirectional Data Port A. Usually connected to the CPU's Address/Data bus.

1B(1:12) I/O Bidirectional Data Port 1B. Usually connected to the even path or even bank of memory.

2B(1:12) I/O Bidirectional Data Port 2B. Usually connected to the odd path or odd bank of memory.

CLK I Clock Input.

CEA1B

I Clock Enable Input for the A-1B Register. If

CEA1B

is LOW during the rising edge of CLK, data will be clocked

into register A-1B (Active LOW).

CEA2B

I Clock Enable Input for the A-2B Register. If

CEA2B

is LOW during the rising edge of CLK, data will be clocked

into register A-2B (Active LOW).

CE1B

I Clock Enable Input for the 1B-A Register. If

CE1B

is LOW during the rising edge of CLK, data will be clocked into

register 1B-A (Active LOW).

CE2B

I Clock Enable Input for the 2B-A Register. If

CE2B

is LOW during the rising edge of CLK, data will be clocked into

register 2B-A (Active LOW).

SEL I 1B or 2B Path Selection. When HIGH during the rising edge of CLK, SEL enables data transfer from 1B Port to

A Port. When LOW during the rising edge of CLK, SEL enables data transfer from 2B Port to A Port.

OEA
OEB

NOTES:

1. On FCT162H272T these pins have "Bus Hold". All other pins are standard inputs, outputs or I/Os.

I Synchronous Output Enable for A Port (Active LOW).
I Synchronous Output Enable for 1B Port and 2B Port (Active LOW).

(1)

(1)

(1)

3071 tbl 01

ABSOLUTE MAXIMUM RATINGS

(1)

Symbol Description Max. Unit

Terminal Voltage with Respect to

(2)

V

TERM

V

TERM

T

STG

I

OUT

NOTES:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT­INGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other condi­tions above those indicated in the operational sections of this specifica­tion is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.

2. All device terminals except FCT162XXXT Output and I/O terminals.

3. Output and I/O terminals for FCT162XXXT.

GND
Terminal Voltage with Respect to

(3)

GND
Storage Temperature –65 to +150°C

DC Output Current –60 to +120 mA

–0.5 to +7.0 V

–0.5 to

V

CC

+0.5

3071 tbl 02

V

CAPACITANCE (TA = +25°C, F = 1.0MHZ)

Symbol Parameter

CIN Input

Capacitance

CI/O I/O

Capacitance

NOTE:

1. This parameter is measured at characterization but not tested.

(1)

Conditions Typ. Max. Unit

VIN = 0V 3.5 6.0 pF

VOUT = 0V 3.5 8.0 pF

3071 tbl 03

FUNCTION TABLES

(2)

Inputs Output

1B 2B SEL

CE1B

CE1B

CE2B

CE2B

OEA

OEA

CLK A

HXHLX L↑ H

LXHLXL↑ L

XXHHXL↑A

(1)

XHLXLL↑ H
XLLXLL↑ L
XXLXHL↑A

(1)

XXXXXH↑ Z

3071 tbl 04

Inputs Outputs

A

CEA1B

CEA1B

CEA2B

CEA2B

OEB

OEB

CLK 1B 2B

HLLL↑ HH
LLLL↑LL
HLHL↑ HB
LLHL↑LB
HHLL↑B
LHLL↑B
XHHL↑B

(1)
(1)
(1)

(1)
(1)

H
L

(1)

B
XXXH↑ZZ
XXXL↑Active Active

NOTES:

1. Output level before the indicated steady-state input conditions were
established.

2. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
Z = High Impedance
↑ = LOW-to-HIGH Transition

3071 tbl 05

5.5 3

IDT54/74FCT162H272AT/CT/ET
FAST CMOS 12-BIT SYNCHRONOUS TRI-PORT BUS EXCHANGER MILITARY AND COMMERCIAL TEMPERATURES RANGES

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE (BUS HOLD)

Following Conditions Apply Unless Otherwise Specified:
Commercial: T

Symbol Parameter Test Conditions

V

IH

V

IL

I

I H

I

I L

I

BHH

I

BHL

I

OZH

I

OZL

V

IK

I

OS

V

H

I

CCL

I

CCH

I

CCZ

A = –40°C to +85°C, VCC = 5.0V ± 10%; Military: TA = –55°C to +125°C, VCC = 5.0V ± 10%

(1)

Min. Typ.

Input HIGH Level Guaranteed Logic HIGH Level 2.0 —

(2)

Max. Unit

—

Input LOW Level Guaranteed Logic LOW Level — — 0.8 V
Input Standard Input
HIGH Standard I/O

(4)

Current

Bus-Hold Input — —

Bus-Hold I/O — —
Input Standard Input
LOW Standard I/O

(4)

Current

Bus-Hold Input — —

Bus-Hold I/O — —
Bus Hold Bus-Hold Input VCC = Min. VI = 2.0V –50 — —
Sustain

(4)

Current
High Impedance Output Current VCC = Max. VO = 2.7V —

(3-State Output pins)
Clamp Diode Voltage VCC = Min., I
Short Circuit Current VCC = Max., VO = GND
Input Hysteresis
Quiescent Power Supply Current VCC = Max., VIN = GND or V

(5)

(5)

(5)

(5)

——

(5,6)

VCC = Max. VI = V

VI = GND — —

I

= 0.8V +50 — —

V

VO = 0.5V —

IN

= –18mA —

(3)

—

CC

CC

——
——

–80–140–225 mA

— 100
— 5 500

±

1

±

1

±

100

±

100

±

1

±

1

±

100

±

100

—
—

–

0.7–1.2 V

±

1

±

1

—

µ

µ

µ

mV

µ

3071 tbl 06

V

A

A

A

A

OUTPUT DRIVE CHARACTERISTICS FOR FCT162H272T

Symbol Parameter Test Conditions

I

ODL

I

ODH

V

OH

V

OL

NOTES:

1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.

2. Typical values are at Vcc = 5.0V, +25°C ambient.

3. Not more than one output should be tested at one time. Duration of the test should not exceed one second.

4. Pins with Bus Hold are identified in the pin description.

5. The test limit for this parameter is ± 5µA at T

6. Does not include Bus Hold I/O pins.

Output LOW Current VCC = 5V, V
Output HIGH Current VCC = 5V, V
Output HIGH Voltage VCC = Min.

IN

= V

IH

V

or V

Output LOW Voltage VCC = Min.

IN

= V

IH

V

A = –55°C.

or V

IN

= V

IH or VIL, VOUT

IN

= V

IH

IL

IL

or V

IL,

(1)

(3)

= 1.5V
= 1.5V

(3)

V

OUT

IOH = –16mA MIL.

OH

= –24mA COM'L.

I
IOL = 16mA MIL.

OL

= 24mA COM'L.

I

Min. Typ.

60 115 200 mA

–60 –115 –200 mA

2.4 3.3 — V

— 0.3 0.55 V

(2)

Max. Unit

3071 lnk 08

5.5 4

IDT54/74FCT162H272AT/CT/ET
FAST CMOS 12-BIT SYNCHRONOUS TRI-PORT BUS EXCHANGER MILITARY AND COMMERCIAL TEMPERATURES RANGES

POWER SUPPLY CHARACTERISTICS

Symbol Parameter Test Conditions

∆ICC Quiescent Power Supply Current

TTL Inputs HIGH

ICCD Dynamic Power Supply Current

VCC = Max.
V

IN = 3.4V

(4)

VCC = Max.

(3)

Outputs Open

(1)

V

IN = VCC

VIN = GND

Min. Typ.

— 0.5 1.5 mA

— 60 100

One Output Port Enabled

CExx

= GND
One Input Bit Toggling
One Output Bit Toggling
50% Duty Cycle

IC Total Power Supply Current

(6)

VCC = Max.
Outputs Open

VIN = VCC
VIN = GND

— 0.6 1.5

fi = 10MHz
50% Duty Cycle
One Output Port Enabled

CExx

= GND

V

IN = 3.4V

V

IN = GND

— 0.9 2.3

One Input Bit Toggling
One Output Bit Toggling
VCC = Max.
Outputs Open

VIN = VCC
VIN = GND

— 1.8 3.5

fi = 2.5MHz
50% Duty Cycle
One Output Port Enabled

CExx

= GND

V

IN = 3.4V

V

IN = GND

— 4.8 12.5

Twelve Input Bits Toggling
Twelve Output Bits Toggling

NOTES:

1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.

2. Typical values are at V

3. Per TTL driven input (V

4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.

5. Values for these conditions are examples of the I

6. I

C = IQUIESCENT + IINPUTS + IDYNAMIC

IC = ICC + ∆ICC DHNT + ICCD (fCPNCP/2 + fiNi)
I

CC = Quiescent Current (ICCL, ICCH and ICCZ)

CC = Power Supply Current for a TTL High Input (VIN = 3.4V)

∆I

H = Duty Cycle for TTL Inputs High

D
N

T = Number of TTL Inputs at DH

ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)

CP = Clock Frequency for Register Devices (Zero for Non-Register Devices)

f

CP = Number of Clock Inputs at fCP

N
fi = Input Frequency

i = Number of Inputs at fi

N

CC = 5.0V, +25°C ambient.

IN = 3.4V). All other inputs at VCC or GND.

CC formula. These limits are guaranteed but not tested.

(2)

Max. Unit

µA/

MHz

mA

(5)

(5)

3071 tbl 09

5.5 5

IDT54/74FCT162H272AT/CT/ET
FAST CMOS 12-BIT SYNCHRONOUS TRI-PORT BUS EXCHANGER MILITARY AND COMMERCIAL TEMPERATURES RANGES

SWITCHING CHARACTERISTICS OVER OPERATING RANGE

FCT162H272AT FCT162H272CT FCT162H272ET

Com'l. Mil. Com'l. Mil. Com'l. Mil.

(1)

Symbol Parameter Condition

tPLH

Propagation Delay
CLK to 1Bx or CLK to 2Bx

tPHL
tPLH

Propagation
Delay

tPHL

SEL Stable

CE

xB Enabled

CL = 50pF

R

L = 500Ω

CLK to Ax SEL Changing

CE

xB Disabled

SEL Changing

CE

xB Enabled

tPZH

Output Enable Time
CLK to Ax, CLK to 1Bx, or

tPZL

(2)

Min.

Max. Min.

1.5 5.8 1.5 6.2 1.5 5.2 1.5 5.6 1.5 4.8 — — ns

1.5 6.0 1.5 6.4 1.5 5.4 1.5 5.8 1.5 5.0 — — ns

1.5 6.0 1.5 6.4 1.5 5.4 1.5 5.8 1.5 5.4 — — ns

1.5 7.6 1.5 7.9 1.5 6.6 1.5 7.0 1.5 5.6 — — ns

1.5 7.7 1.5 8.1 1.5 6.8 1.5 7.2 1.5 6.0 — — ns

CLK to 2Bx

tPHZ

Output Disable Time
CLK to Ax, CLK to 1Bx, or

tPLZ

1.5 6.4 1.5 6.8 1.5 6.0 1.5 6.4 1.5 5.6 — — ns

CLK to 2Bx

tSU Set-Up Time, HIGH or LOW

2.0 — 2.0 — 2.0 — 2.0 — 2.0 — — — ns

Data to CLK

tSU Set-Up Time,

OEB

to CLK

OEA

to CLK,

2.0 — 2.0 — 2.0 — 2.0 — 2.0 — — — ns

tSU Set-Up Time, SEL to CLK 2.0 — 2.0 — 2.0 — 2.0 — 2.0 — — — ns
tSU Set-Up Time,

CE1B

to CLK,

or

CEA2B

CEA1B

CE2B

to CLK

to CLK,

to CLK,

2.0 — 2.0 — 2.0 — 2.0 — 2.0 — — — ns

tH Hold Time, CLK to Data 0 — 0 — 0 — 0 — 0 — — — ns
tH Hold Time, CLK to

CLK to

OEB

tH Hold Time, CLK to

CLK to

CE1B

CLK to

CEA2B

tW Pulse Width, CLK HIGH
tSK(o) Output Skew

NOTES:

1. See test circuits and waveforms.

2. Minimum limits are guaranteed but not tested on Propagation Delays.

3. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.

4. This parameter is guaranteed but not tested.

OEA

, CLK to SEL

CEA1B

, CLK to

(3)

CE2B

,

,

0.5 — 0.5 — 0.5 — 0.5 — 0.5 — — — ns

0—0—0—0—0———ns

,

(4)

3.0 — 3.0 — 3.0 — 3.0 — 3.0 — — — ns
— 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — — ns

(2)

Max. Min.

(2)

Max. Min.

(2)

Max. Min.

(2)

Max. Min.

(2)

Max. Unit

3071 tbl 10

5.5 6

IDT54/74FCT162H272AT/CT/ET
FAST CMOS 12-BIT SYNCHRONOUS TRI-PORT BUS EXCHANGER MILITARY AND COMMERCIAL TEMPERATURES RANGES

TEST CIRCUITS AND WAVEFORMS

SWITCH POSITION

TEST CIRCUITS FOR ALL OUTPUTS

Open Drain
Disable Low

All Other Tests

Generator.

Pulse

Generator

VIN

R T

VCC

D.U.T.

V OUT

50pF

C L

500Ω

500Ω

7.0V

3071 lnk 04

DEFINITIONS:

L= Load capacitance: includes jig and probe capacitance.

C

T = Termination resistance: should be equal to ZOUT of the Pulse

R

SET-UP, HOLD AND RELEASE TIMES PULSE WIDTH

DATA

INPUT

TIMING

INPUT

ASYNCHRONOUS CONTROL

PRESET

CLEAR

ETC.

SYNCHRONOUS CONTROL

PRESET

CLOCK ENABLE

CLEAR

ETC.

t

SU

t

SU

t

REM

t

t

H

H

3V

1.5V
0V

3V

1.5V
0V

3V

1.5V
0V

3V

1.5V
0V

3071 lnk 05

LOW-HIGH-LOW

HIGH-LOW-HIGH

Test Switch

Enable Low

PULSE

t

W

PULSE

Closed

Open

3032 tbl 11

1.5V

1.5V

3071 lnk 06

PROPAGATION DELAY

SAME PHASE

INPUT TRANSITION

t

PLH

OUTPUT

t

PLH

OPPOSITE PHASE

INPUT TRANSITION

t

t

PHL

PHL

3V

1.5V
0V

V

OH

1.5V

V

OL

3V

1.5V
0V

3071 lnk 07

ENABLE AND DISABLE TIMES

ENABLE DISABLE

3V

CONTROL

INPUT

PLZtPZL

t

OUTPUT

NORMALLY

LOW

SWITCH
CLOSED

3.5V

1.5V

tPZH tPHZ

OUTPUT

NORMALLY

NOTES:

1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH

2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; t

HIGH

SWITCH
OPEN

1.5V
0V

F ≤ 2.5ns; tR ≤ 2.5ns

0.3V

0.3V

1.5V
0V

3.5V

VOL

VOH

0V

3071 drw 08

5.5 7

IDT54/74FCT162H272AT/CT/ET
FAST CMOS 12-BIT SYNCHRONOUS TRI-PORT BUS EXCHANGER MILITARY AND COMMERCIAL TEMPERATURES RANGES

ORDERING INFORMATION

IDT

XX

Temp. Range

FCT

X

Drive

X

Bus Hold

XXXX

Device TypeXPackageXProcess

Blank
B

PV
PA
PF
E

272AT
272CT
272ET

H

162 16-Bit Balanced Drive

54
74

Commercial
MIL-STD-883, Class B

Shrink Small Outline Package (SO56-1)
Thin Shrink Small Outline Package (SO56-2)
Thin Very Small Outline Package (SO56-3)
CERPACK (E56-1)

12-Bit Synchronous Tri-Port Bus Exchanger

Bus Hold

-55°C to +125°C

-40°C to +85°C

3071 drw 09

5.5 8