Datasheet IDT74FCT16841CTE, IDT74FCT16841BTPVB, IDT74FCT16841BTPV, IDT74FCT16841BTPFB, IDT74FCT16841BTPF Datasheet (Integrated Device Technology)
...
Integrated Device Technology, Inc.
FAST CMOS 20-BIT
TRANSPARENT
LATCHES
IDT54/74FCT16841AT/BT/CT/ET
IDT54/74FCT162841AT/BT/CT/ET
FEATURES:
• Common features:
– 0.5 MICRON CMOS Technology
– High-speed, low-power CMOS replacement for
ABT functions
– Typical tSK(o) (Output Skew) < 250ps
– Low input and output leakage ≤1µA (max.)
– ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
– Packages include 25 mil pitch SSOP, 19.6 mil pitch
TSSOP, 15.7 mil pitch TVSOP and 25 mil pitch Cerpack
– Extended commercial range of -40°C to +85°C
–VCC = 5V ±10%
• Features for FCT16841AT/BT/CT/ET:
– High drive outputs (-32mA IOH, 64mA IOL)
– Power off disable outputs permit “live insertion”
– Typical V
VCC = 5V, TA = 25°C
• Features for FCT162841AT/BT/CT/ET:
– Balanced Output Drivers: ±24mA (commercial),
– Reduced system switching noise
– Typical VOLP (Output Ground Bounce) < 0.6V at
VCC = 5V,TA = 25°C
OLP (Output Ground Bounce) < 1.0V at
±16mA (military)
DESCRIPTION:
The FCT16841AT/BT/CT/ET and FCT162841AT/BT/CT/
ET 20-bit transparent D-type latches are built using advanced
dual metal CMOS technology. These high-speed, low-power
latches are ideal for temporary storage of data. They can be
used for implementing memory address latches, I/O ports,
and bus drivers. The Output Enable and Latch Enable controls
are organized to operate each device as two 10-bit latches or
one 20-bit latch. Flow-through organization of signal pins
simplifies layout. All inputs are designed with hysteresis for
improved noise margin.
The FCT16841AT/BT/CT/ET are ideally suited for driving
high-capacitance loads and low-impedance backplanes. The
output buffers are designed with power off disable capability
to allow "live insertion" of boards when used as backplane
drivers.
The FCT162841AT/BT/CT/ET have balanced output drive
with current limiting resistors. This offers low ground bounce,
minimal undershoot, and controlled output fall times–reducing
the need for external series terminating resistors. The
FCT162841AT/BT/CT/ET are plug-in replacements for the
FCT16841AT/BT/CT/ET and ABT16841 for on-board interface applications.
FUNCTIONAL BLOCK DIAGRAM
1OE
1LE
1D1
TO 9 OTHER CHANNELS
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
D
C
2556 drw 01
1Q1
2
OE
2LE
2D1
D
C
TO 9 OTHER CHANNELS
2Q1
2556 drw 02
MILITARY AND COMMERCIAL TEMPERATURE RANGES JULY 1996
1996 Integrated Device Technology, Inc. 5.18 DSC-2556/7
1
IDT54/74FCT16841AT/BT/CT/ET, 162841AT/BT/CT/ET
FAST CMOS 20-BIT TRANSPARENT LATCHES MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
1
OE
1Q1
1Q2
GND
1Q3
Q4
1
VCC
Q5
1
Q6
1
1
Q7
GND
Q8
1
1
Q9
1Q10
2Q1
Q2
2
Q3
2
GND
2Q4
2
Q5
2
Q6
VCC
Q7
2
2
Q8
GND
Q9
2
Q10
2
2OE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
SO56-1
SO56-2
15
SO56-3
16
17
18
19
20
21
22
23
24
26
27
28
SSOP/
TSSOP/TVSOP
TOP VIEW
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
3225
31
30
29
1LE
1D1
1
D2
GND
1D3
1
D4
VCC
1
D5
D6
1
1
D7
GND
D8
1
1
D9
1
D10
2D1
2
D2
2
D3
GND
D4
2
2
D5
2
D6
VCC
D7
2
2
D8
GND
2D9
2
D10
2
LE
2556 drw 03
OE
1
1Q1
Q2
1
GND
1Q3
1
Q4
VCC
1
Q5
1
Q6
1
Q7
GND
1
Q8
1
Q9
1Q10
2
Q1
2
Q2
Q3
2
GND
Q4
2
2
Q5
2
Q6
V
CC
2Q7
2
Q8
GND
2Q9
2
Q10
2OE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
CERPACK
TOP VIEW
E56-1
48
43
56
55
54
53
52
51
50
49
47
46
45
44
42
41
40
39
38
37
36
35
34
33
32
31
30
29
2556 drw 04
LE
1
1D1
1
D2
GND
1D3
1
D4
VCC
1
D5
1
D6
1
D7
GND
1
D8
1
D9
1
D10
D1
2
2
D2
2
D3
GND
2D4
D5
2
2
D6
VCC
2D7
D8
2
GND
2
D9
D10
2
2
LE
5.18 2
IDT54/74FCT16841AT/BT/CT/ET, 162841AT/BT/CT/ET
FAST CMOS 20-BIT TRANSPARENT LATCHES MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN DESCRIPTION
Pin Names Description
xDx Data Inputs
xLE Latch Enable Input (Active HIGH)
x
OE
xQx 3-State Outputs
ABSOLUTE MAXIMUM RATINGS
Symbol Description Max. Unit
(2)
VTERM
(3)
VTERM
TSTG Storage Temperature –65 to +150 °C
IOUT DC Output Current –60 to +120 mA
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
2. All device terminals except FCT162XXXT Output and I/O terminals.
3. Output and I/O terminals for FCT162XXXT.
Output Enable Input (Active LOW)
Terminal Voltage with Respect to
GND
Terminal Voltage with Respect to
GND
2556 tbl 01
(1)
–0.5 to +7.0 V
–0.5 to
CC +0.5
V
2556 lnk 03
V
FUNCTION TABLE
(1)
Inputs Outputs
xDx xLE x
OE
OE
xQx
HHLH
LHLL
XLLQ
(2)
XXHZ
NOTES: 2556 tbl 02
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
Z = High Impedance
2. Output level before xLE HIGH-to-LOW Transition.
CAPACITANCE (TA = +25°C, f = 1.0MHz)
Symbol Parameter
C
IN
Input
Capacitance
C
OUT
Output
Capacitance
NOTE:
1. This parameter is measured at characterization but not tested.
(1)
Conditions Typ. Max. Unit
VIN = 0V 3.5 6.0
V
OUT
= 0V 3.5 8.0
pF
pF
2556 lnk 04
5.18 3
IDT54/74FCT16841AT/BT/CT/ET, 162841AT/BT/CT/ET
FAST CMOS 20-BIT TRANSPARENT LATCHES MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: T
Symbol Parameter Test Conditions
VIH Input HIGH Level Guaranteed Logic HIGH Level 2.0 — — V
VIL Input LOW Level Guaranteed Logic LOW Level — — 0.8 V
II H Input HIGH Current (Input pins)
II L Input LOW Current (Input pins)
IOZH High Impedance Output Current VCC = Max. VO = 2.7V — — ±1 µA
IOZL (3-State Output pins)
VIK Clamp Diode Voltage VCC = Min., IIN = –18mA — –0.7 –1.2 V
IOS Short Circuit Current VCC = Max., VO = GND
VH Input Hysteresis — — 100 — mV
ICCL
ICCH
ICCZ
A = –40°C to +85°C, VCC = 5.0V ± 10%; Military: TA = –55°C to +125°C, VCC
(1)
(5)
VCC = Max. VI = VCC — — ±1 µA
Input HIGH Current (I/O pins)
Input LOW Current (I/O pins)
(5)
(5)
(5)
VI = GND — — ±1
(5)
VO = 0.5V — — ±1
(3)
= 5.0V ± 10%
Min. Typ.
(2)
Max. Unit
— — ±1
— — ±1
–80 –140 –225 mA
Quiescent Power Supply Current VCC = Max., VIN = GND or VCC — 5 500 µA
2556 lnk 05
OUTPUT DRIVE CHARACTERISTICS FOR FCT16841T
Symbol Parameter Test Conditions
IO Output Drive Current VCC = Max., VO = 2.5V
(3)
(1)
Min. Typ.
–50 —–180 mA
VOH Output HIGH Voltage VCC = Min. IOH = –3mA 2.5 3.5 — V
VIN = VIH or VIL IOH = –12mA MIL.
VOL Output LOW Voltage VCC = Min.
IN = VIH or VIL
V
IOFF Input/Output Power Off Leakage
(5)
VCC = 0V, VIN or VO ≤ 4.5V — — ±1 µA
OH = –15mA COM'L.
I
IOH = –24mA MIL.
OH = –32mA COM'L.
I
IOL = 48mA MIL.
OL = 64mA COM'L.
I
2.4 3.5 — V
2.0 3.0 — V
(4)
— 0.2 0.55 V
(2)
Max. Unit
2556 lnk 06
OUTPUT DRIVE CHARACTERISTICS FOR FCT162841T
Symbol Parameter Test Conditions
I
ODL
I
ODH
V
OH
V
OL
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient.
3. Not more than one output should be tested at one time. Duration of the test should not exceed one second.
4. Duration of the condition can not exceed one second.
5. The test limit for this parameter is ± 5µA at T
Output LOW Current VCC = 5V, V
Output HIGH Current VCC = 5V, V
Output HIGH Voltage VCC = Min.
IN
= V
IH
V
or V
Output LOW Voltage VCC = Min.
IN
= V
IH
V
A = –55°C.
or V
IN
= V
IH or VIL, VOUT
IN
= V
IH
or V
IL,
IL
IL
5.18 4
(1)
(3)
= 1.5V
= 1.5V
(3)
V
OUT
IOH = –16mA MIL.
OH
= –24mA COM'L.
I
IOL = 16mA MIL.
OL
= 24mA COM'L.
I
Min. Typ.
60 115 200 mA
–60 –115 –200 mA
2.4 3.3 — V
— 0.3 0.55 V
(2)
Max. Unit
2556 lnk 07
IDT54/74FCT16841AT/BT/CT/ET, 162841AT/BT/CT/ET
FAST CMOS 20-BIT TRANSPARENT LATCHES MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
Symbol Parameter Test Conditions
∆ICC Quiescent Power Supply Current
TTL Inputs HIGH
ICCD Dynamic Power Supply
Current
(4)
VCC = Max.
IN = 3.4V
V
(3)
VCC = Max.
Outputs Open
(1)
IN = VCC
V
IN = GND
V
Min. Typ.
— 0.5 1.5 mA
— 60 100 µA/
xOE = GND
One Input Toggling
50% Duty Cycle
IC Total Power Supply Current
(6)
VCC = Max.
Outputs Open
IN = VCC
V
IN = GND
V
— 0.6 1.5 mA
fi =10MHz
50% Duty Cycle
xOE = GND
= VCC
xLE
IN = 3.4V
V
IN = GND
V
— 0.9 2.3
One Bit Toggling
VCC = Max.
Outputs Open
IN = VCC
V
IN = GND
V
— 3.0 5.5
fi = 2.5MHz
50% Duty Cycle
xOE = GND
xLE = V
CC
IN = 3.4V
V
IN = GND
V
— 8.0 20.5
Twenty Bits Toggling
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
3. Per TTL driven input (V
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the I
C = IQUIESCENT + IINPUTS + IDYNAMIC
6. I
IC = ICC + ∆ICC DHNT + ICCD (fCPNCP/2 + fiNi)
I
CC = Quiescent Current (ICCL, ICCH and ICCZ)
CC = Power Supply Current for a TTL High Input (VIN = 3.4V)
∆I
D
H = Duty Cycle for TTL Inputs High
T = Number of TTL Inputs at DH
N
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
CP = Clock Frequency for Register Devices (Zero for Non-Register Devices)
f
CP = Number of Clock Inputs at fCP
N
fi = Input Frequency
i = Number of Inputs at fi
N
CC = 5.0V, +25°C ambient.
IN = 3.4V). All other inputs at VCC or GND.
CC formula. These limits are guaranteed but not tested.
(2)
Max. Unit
MHz
(5)
(5)
2556 tbl 08
5.18 5
IDT54/74FCT16841AT/BT/CT/ET, 162841AT/BT/CT/ET
FAST CMOS 20-BIT TRANSPARENT LATCHES MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
FCT16841AT/162841AT FCT16841BT/162841BT
Com'l. Mil. Com'l. Mil.
L = 500Ω
L = 500Ω
L = 500Ω
L = 500Ω
L = 500Ω
L = 500Ω
L = 500Ω
(1)
(5)
(5)
(5)
(5)
Symbol Parameter Condition
tPLH
tPHL
Propagation Delay
xDx to xQx
CL = 50pF
R
(LE = HIGH) CL = 300pF
R
tPLH
tPHL
Propagation Delay
xLE to xQx
CL = 50pF
R
CL = 300pF
R
tPZH
tPZL
Output Enable Time
xOE to xQx
CL = 50pF
R
CL = 300pF
R
tPHZ
tPLZ
Output Disable Time
xOE to xQx
CL = 5pF
R
CL = 50pF
R
L = 500Ω
tSU Set-Up Time HIGH or LOW,
xDx to xLE
CL = 50pF
R
L = 500Ω
tH Hold Time HIGH or LOW,
xDx to xLE
tW xLE Pulse Width HIGH 4.0
Min.
(2)
Max. Min.
(2)
Max. Min.
(2)
Max. Min.
(2)
1.5 9.0 1.5 10.0 1.5 6.5 1.5 7.5 ns
1.5 13.0 1.5 15.0 1.5 13.0 1.5 15.0
1.5 12.0 1.5 13.0 1.5 8.0 1.5 10.5 ns
1.5 16.0 1.5 20.0 1.5 15.5 1.5 18.0
1.5 11.5 1.5 13.0 1.5 8.0 1.5 8.5 ns
1.5 23.0 1.5 25.0 1.5 14.0 1.5 15.0
1.5 7.0 1.5 9.0 1.5 6.0 1.5 6.5 ns
1.5 8.0 1.5 10.0 1.5 7.0 1.5 7.5
2.5 — 2.5 — 2.5 — 2.5 — ns
2.5 — 3.0 — 2.5 — 2.5 — ns
(4)
— 5.0 — 4.0
(4)
— 4.0
(4)
Max. Unit
—ns
tSK(o) Output skew
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
4. This limit is guaranteed but not tested.
5. This condition is guaranteed but not tested.
(3)
— 0.5 — 0.5 — 0.5 — 0.5 ns
2556 tbl 09
5.18 6
IDT54/74FCT16841AT/BT/CT/ET, 162841AT/BT/CT/ET
FAST CMOS 20-BIT TRANSPARENT LATCHES MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
FCT16841CT/162841CT FCT16841ET/162841ET
Com'l. Mil. Com'l. Mil.
L = 500Ω
L = 500Ω
L = 500Ω
L = 500Ω
L = 500Ω
L = 500Ω
L = 500Ω
(1)
(5)
(5)
(5)
(5)
Symbol Parameter Condition
tPLH
tPHL
Propagation Delay
xDx to xQx
CL = 50pF
R
(LE = HIGH) CL = 300pF
R
tPLH
tPHL
Propagation Delay
xLE to xQx
CL = 50pF
R
CL = 300pF
R
tPZH
tPZL
Output Enable Time
xOE to xQx
CL = 50pF
R
CL = 300pF
R
tPHZ
tPLZ
Output Disable Time
xOE to xQx
CL = 5pF
R
CL = 50pF
R
L = 500Ω
tSU Set-Up Time HIGH or LOW,
xDx to xLE
CL = 50pF
R
L = 500Ω
tH Hold Time HIGH or LOW,
xDx to xLE
tW xLE Pulse Width HIGH 4.0
Min.
(2)
Max. Min.
(2)
Max. Min.
(2)
Max. Min.
(2)
1.5 5.5 1.5 6.3 1.5 3.4 — — ns
1.5 13.0 1.5 15.0 1.5 7.5 — —
1.5 6.4 1.5 6.8 1.5 3.7 — — ns
1.5 15.0 1.5 16.0 1.5 7.5 — —
1.5 6.5 1.5 7.3 1.5 4.4 — — ns
1.5 12.0 1.5 13.0 1.5 9.0 — —
1.5 5.7 1.5 6.0 1.5 3.6 — — ns
1.5 6.0 1.5 6.3 1.5 3.6 — —
2.5 — 2.5 — 1.0 — — — ns
2.5 — 2.5 — 1.0 — — — ns
(4)
— 4.0
(4)
— 3.0
(4)
———ns
Max. Unit
tSK(o) Output skew
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
4. This limit is guaranteed but not tested.
5. This condition is guaranteed but not tested.
(3)
— 0.5 — 0.5 — 0.5 — — ns
2556 tbl 10
5.18 7
IDT54/74FCT16841AT/BT/CT/ET, 162841AT/BT/CT/ET
FAST CMOS 20-BIT TRANSPARENT LATCHES MILITARY AND COMMERCIAL TEMPERATURE RANGES
TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS
SWITCH POSITION
Test Switch
V
CC
7.0V
Open Drain
Disable Low
500
Pulse
Generator
Ω
V
V
IN
D.U.T.
T
R
OUT
50pF
C
L
500
Ω
2556 drw 05
DEFINITIONS:
L= Load capacitance: includes jig and probe capacitance.
C
T = Termination resistance: should be equal to ZOUT of the Pulse
R
Enable Low
All Other Tests
Generator.
SET-UP, HOLD AND RELEASE TIMES PULSE WIDTH
DATA
INPUT
TIMING
INPUT
ASYNCHRONOUS CONTROL
PRESET
CLEAR
ETC.
SYNCHRONOUS CONTROL
PRESET
CLEAR
CLOCK ENABLE
ETC.
t
t
REM
H
t
H
t
SU
t
SU
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
2556 drw 06
LOW-HIGH-LOW
PULSE
HIGH-LOW-HIGH
PULSE
Closed
Open
2556 lnk 11
1.5V
t
W
1.5V
2556 drw 07
SAME PHASE
INPUT TRANSITION
OUTPUT
OPPOSITE PHASE
INPUT TRANSITION
t
PLH
t
PLH
t
t
PHL
PHL
3V
1.5V
0V
OH
V
1.5V
V
OL
3V
1.5V
0V
2556 drw 08
ENABLE AND DISABLE TIMESPROPAGATION DELAY
ENABLE DISABLE
3V
CONTROL
INPUT
t
PHZ
t
PLZ
t
PZL
OUTPUT
NORMALLY
OUTPUT
NORMALLY
HIGH
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH
2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; t
LOW
SWITCH
CLOSED
t
PZH
SWITCH
OPEN
3.5V
1.5V
1.5V
0V
1.5V
0V
3.5V
0.3V
V
OL
V
0.3V
F ≤ 2.5ns; tR ≤ 2.5ns
OH
0V
2556 drw 09
5.18 8
IDT54/74FCT16841AT/BT/CT/ET, 162841AT/BT/CT/ET
FAST CMOS 20-BIT TRANSPARENT LATCHES MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDT XX
Temp. Range
FCT
XXXX
Device Type
X
Package
X
Process
Blank
B
PV
PA
PF
E
16841AT
16841BT
16841CT
16841ET
162841AT
162841BT
162841CT
162841ET
54
74
Commercial
MIL-STD-883, Class B
Shrink Small Outline Package (SO56-1)
Thin Shrink Small Outline Package (SO56-2)
Thin Very Small Outline Package (SO56-3)
CERPACK (E56-1)
Non-Inverting 20-Bit Transparent Latch
–55°C to +125°C
–40°C to +85°C
2556 drw 10
5.18 9
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