Datasheet IDT74FCT162701TPVB, IDT74FCT162701TPV, IDT74FCT162701TPFB, IDT74FCT162701TPF, IDT74FCT162701TPAB Datasheet (Integrated Device Technology)

Integrated Device Technology, Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES AUGUST 1996

1996 Integrated Device Technology, Inc. 5.15 DSC-2915/3

The IDT logo is a registered trademark of Integrated Device Techology, Inc.

1

FAST CMOS 18-BIT
R/W BUFFER

IDT54/74FCT162701T/AT

DESCRIPTION:

The FCT162701T/AT is an 18-bit Read/Write buffer with
a four deep FIFO and a read-back latch. It can be used as
a read/write buffer between a CPU and memory or to
interface a high-speed bus and a slow peripheral. The A­to-B (write) path has a four deep FIFO for pipelined opera­tions. The FIFO can be reset and a FIFO full condition is
indicated by the full flag (FF). The B-to-A (read) path has a

latch. A HIGH on LE, allows data to flow transparently from
B-to-A. A LOW on LE allows the data to be latched on the
falling edge of LE.

The FCT162701T/AT has a balanced output drive with
series termination. This provides low ground bounce,
minimal undershoot and controlled output edge rates.

FEATURES:

• 0.5 MICRON CMOS Technology

• Typical tSK(o) (Output Skew) < 250ps

• Low input and output leakage ≤1µA (max.)

• ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)

• Packages include 25 mil pitch SSOP, 19.6 mil pitch TSSOP,

15.7 mil pitch TVSOP and 25 mil pitch Cerpack

• Extended commercial range of -40°C to +85°C

• Balanced Output Drivers: ±24mA (commercial),

±16mA (military)

• Reduced system switching noise

• Typical V

OLP (Output Ground Bounce) < 0.6V at

VCC = 5V, TA = 25°C

• Ideal for new generation x86 write-back cache solutions

• Suitable for modular x86 architectures

• Four deep write FIFO

• Latch in read path

• Synchronous FIFO reset

2915 drw 01

LATCH

LE

OEBA

18

18

A

1-18

B1-18

FIFO
(4 deep)

OEAB

FF

CLK

RESET

WCE

RCE

FUNCTIONAL BLOCK DIAGRAM

5.15 2

IDT54/74FCT162701T/AT
FAST CMOS 18-BIT R/W BUFFER MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN CONFIGURATIONS

2915 drw 03

2915 drw 02

RCE

B

2

B3

GND

B

4

B5

VCC

B6

B7

B1

B8
B9
B10
B11

GND

B12

B13

VCC

B14

GND

CLK

B

16

B15

B17
GND
B

18

RESET

FF

OEAB

WCE

A

1

GND

A

2

A3

VCC

A4
A5

GND

A

6

A7
A8
A9

GND

A

10

A11

VCC

A12

A18

A14

A13

A16

GND

A

17

LE

A

15

OEBA

47

37

38

39

40

41

42

43

44

45

46

33

34

35

36

56
55

49

50

51

52

53

54

48

1
2
3

4
5
6
7
8
9
10

12
13
14
15
16
17
18
19
20

11

21
22
23
24

29

30

31

3225
26
27
28

CERPACK
TOP VIEW

E56-1

RCE

B

2

B3

GND

B

4

B5

VCC

B6

B7

B1

B8
B9
B10
B11

GND

B

12

B13

VCC

B14

GND

CLK

B

16

B15

B17
GND
B

18

FF
RESET

OEAB

WCE

A

1

GND

A

2

A3

VCC

A4
A5

A9

A6

A7
A8

GND

GND

A

10

A11

VCC

A12

A18

A14

A13

A16

GND

A

17

LE

A

15

OEBA

47

37

38

39

40

41

42

43

44

45

46

33

34

35

36

56
55

49

50

51

52

53

54

48

1
2
3
4
5
6
7
8
9
10

12
13
14
15
16
17
18
19
20

11

21
22
23
24

SSOP/

TSSOP/TVSOP

TOP VIEW

SO56-1
SO56-2
SO56-3

29

30

31

3225
26
27
28

IDT54/74FCT162701T/AT
FAST CMOS 18-BIT R/W BUFFER MILITARY AND COMMERCIAL TEMPERATURE RANGES

5.15 3

PIN DESCRIPTION

ABSOLUTE MAXIMUM RATINGS

(1)

CAPACITANCE (TA = +25°C, f = 1.0MHz)

2915 lnk 03

NOTE:

1. This parameter is measured at characterization but not tested.

2915 tbl 01

Symbol Parameter

(1)

Conditions Typ. Max. Unit

CIN Input

Capacitance

VIN = 0V 3.5 6.0 pF

CI/O I/O

Capacitance

VOUT = 0V 3.5 8.0 pF

Pin Names I/O Description

A1-18 I/O 18 bit I/O port.
B1-18 I/O 18 bit I/O port.

CLK I Clock for write path FIFO. Clocks data into FIFO when

WCE

is low, clocks data out of FIFO when

RCE

is
low. When FIFO is full all further writes to the FIFO are inhibited. When FIFO is empty all reads from the
FIFO are inhibited. CLK also resets the FIFO when

RESET

is low.

WCE

I Enable pin for FIFO input clock.

RCE

I Enable pin for FIFO output clock.

FF

O Write path FIFO full flag. Goes low when FIFO is full.

RESET

I Synchronous FIFO reset - when low CLK resets the FIFO. The FIFO pointers are initialized to the

"empty" condition and FIFO output is forced high (all ones). The FIFO full flag (FF) will be high
immediately after reset.

OEAB

I Output Enable pin for B port.

OEBA

I Output Enable pin for A port.

LE I Read path latch enable pin. When high, data flows transparently from B port to A port, B data is latched

on the falling edge of LE.

Symbol Description Max. Unit

VTERM

(2)

Terminal Voltage with Respect to
GND

–0.5 to +7.0 V

VTERM

(3)

Terminal Voltage with Respect to
GND

–0.5 to

V

CC +0.5

V

TSTG Storage Temperature –65 to +150 °C
IOUT DC Output Current –60 to +120 mA

NOTES:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT­INGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is
not

implied. Exposure to absolute maximum rating conditions for

extended periods may affect reliability.

2. All device terminals except FCT162XXXT Output and I/O terminals.

3. Output and I/O terminals for FCT162XXXT.

2915 lnk 02

5.15 4

IDT54/74FCT162701T/AT
FAST CMOS 18-BIT R/W BUFFER MILITARY AND COMMERCIAL TEMPERATURE RANGES

APPLICATIONS: 486 INTERFACE

2915 drw 04

Figure 1. FCT162701T Application Example

i486

FCT162701T

CacheRAM

PAL

CLK,WCE,
RCE, RST

CLKW/R

LE,OEBA,
OEAB

DRAM

Coprocessor

A

B

FUNCTIONAL DESCRIPTION:

This device is useful as a read/write buffer for modular high

end designs. It provides multi-level buffering in the write path
and single deep buffering in the read path, and is suited to
write back cache implementation. The read path provides a
transparent latch.

The four deep FIFO uses one clock with two clock enable

pins,

WCE

and

RCE

to clock data in and out. The FIFO has
an external full flag which goes LOW when the FIFO is full.
Internal read and write pointers keep track of the words stored
in the FIFO. A write attempt to a full FIFO is ignored. An
attempt to read from an empty FIFO will have no effect and the
last read data remains at the output of the FIFO. The FIFO
may be reset by the synchronous

RESET

input. This resets

the read and write pointers to the original "empty" condition
and also sets all B outputs = 1. Simultaneous read and write
attempts (clock data into FIFO as well as clock data out of
FIFO) are possible except on FIFO empty and full boundaries.
When the FIFO is empty, and a simultaneous read and write
is attempted, the read is ignored while the write is executed.
If the same is attempted when the FIFO is full, the write is
ignored while the read is executed. Normal operation of the
four deep FIFO in the write path is independent of the read
path operation.

Power, ground and data pin positions on the FCT162701T
match those on the FCT16501T/162501T, allowing an easy
upgrade.

IDT54/74FCT162701T/AT
FAST CMOS 18-BIT R/W BUFFER MILITARY AND COMMERCIAL TEMPERATURE RANGES

5.15 5

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE

Following Conditions Apply Unless Otherwise Specified:
Commercial: TA = -40°C to +85°C, VCC = 5.0V ± 10%; Military: TA = -55°C to +125°C, VCC = 5.0V ± 10%

Symbol Parameter Test Conditions

(1)

Min. Typ.

(2)

Max. Unit

VIH Input HIGH Level Guaranteed Logic HIGH Level 2.0 — — V
VIL Input LOW Level Guaranteed Logic LOW Level — — 0.8 V
II H Input HIGH Current (Input pins)

(5)

VCC = Max. VI = VCC — — ±1 µA

Input HIGH Current (I/O pins)

(5)

— — ±1

II L Input LOW Current (Input pins)

(5)

VI = GND — — ±1

Input LOW Current (I/O pins)

(5)

— — ±1
IOZH High Impedance Output Current VCC = Max. VO = 2.7V — — ±1 µA
IOZL (3-State Output pins)

(5)

VO = 0.5V — — ±1
VIK Clamp Diode Voltage VCC = Min., IIN = –18mA — –0.7 –1.2 V
IOS Short Circuit Current VCC = Max., VO = GND

(3)

–80 –140 –225 mA
VH Input Hysteresis — — 100 — mV
ICCL

ICCH
ICCZ

Quiescent Power Supply Current VCC = Max., VIN = GND or VCC — 5 500 µA

2915 lnk 04

OUTPUT DRIVE CHARACTERISTICS

NOTES:

1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.

2. Typical values are at Vcc = 5.0V, +25°C ambient.

3. Not more than one output should be tested at one time. Duration of the test should not exceed one second.

4. Duration of the condition can not exceed one second.

5. The test limit for this parameter is ± 5µA at T

A = –55°C.

2915 lnk 05

Symbol Parameter Test Conditions

(1)

Min. Typ.

(2)

Max. Unit

IODL Output LOW Current VCC = 5V, VIN = VIH or VIL, VOUT = 1.5V

(3)

60 115 200 mA

IODH Output HIGH Current VCC = 5V, VIN = VIH or V IL,

VOUT = 1.5V

(3)

–60 –115 –200 mA

VOH Output HIGH Voltage VCC = Min.

V

IN = VIH or VIL

IOH = –16mA MIL.
I

OH = –24mA COM'L.

2.4 3.3 — V

VOL Output LOW Voltage VCC = Min.

V

IN = VIH or VIL

IOL = 16mA MIL.
I

OL = 24mA COM'L.

— 0.3 0.55 V

5.15 6

IDT54/74FCT162701T/AT
FAST CMOS 18-BIT R/W BUFFER MILITARY AND COMMERCIAL TEMPERATURE RANGES

POWER SUPLY CHARACTERISTICS

2915 tbl 06

NOTES:

1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.

2. Typical values are at V

CC = 5.0V, +25°C ambient.

3. Per TTL driven input (V

IN) = 3.4V). All other inputs at VCC or GND.

4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.

5. Values for these conditions are examples of the I

CC formula. These limits are guaranteed but not tested.

6. I

C = IQUIESCENT + IINPUTS + IDYNAMIC

IC = ICC + ∆ICC DHNT + ICCD (CLK) X fCP + ICCD (O/P) x fO NO
ICC = Quiescent Current (ICCL, ICCH and ICCZ)
∆I

CC = Power Supply Current for a TTL High Input (VIN = 3.4V)

D

H = Duty Cycle for TTL Inputs High

N

T = Number of TTL Inputs at D

I

CCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)

f

CP = Clock Frequency for Register Devices (Zero for Non-Register Devices)

f

O = Output Frequency

N

O = Number of Outputs at fO

Symbol Parameter Test Conditions

(1)

Min. Typ.

(2)

Max. Unit

∆ICC

Quiescent Power Supply Current
TTL Inputs HIGH

VCC = Max.
V

IN = 3.4V

(3)

— 0.5 1.5 mA

ICCD (CLK) Dynamic Power Supply Current

due to clock switching

(4)

VCC = Max.
Outputs Open

CLK Toggling
50% Duty Cycle

VIN = VCC
V

IN = GND

— 180 240 µA/

MHz

ICCD (O/P) Dynamic Power Supply Current

due to output switching

(4)

One Bit Toggling
50% Duty Cycle

— 80 120

IC Total Power Supply Current

(6)

VCC = Max.
Outputs Open
f

CP= 10MHz

50% Duty Cycle

V

IN = VCC

V

IN = GND

— 1.8 2.9

(5)

mA

OEAB

= GND;

OEBA

= VCC

LE =

WCE

=

RCE

= GND

RESET

= V

CC

All Inputs Low

V

IN = 3.4V

V

IN = GND

— 2.1 3.7

(5)

VCC = Max.
Outputs Open
f

CP= 10MHz

50% Duty Cycle

V

IN = VCC

V

IN = GND

— 2.2 3.5

OEAB

= GND;

OEBA

= VCC

LE =

WCE

=

RCE

= GND

RESET

= V

CC

One Bit Toggling
at fo = 5MHz
50% Duty Cycle

V

IN = 3.4V

V

IN = GND

— 2.7 5.0

IDT54/74FCT162701T/AT
FAST CMOS 18-BIT R/W BUFFER MILITARY AND COMMERCIAL TEMPERATURE RANGES

5.15 7

NOTES:

1. See test circuit and waveforms.

2. Minimum limits are guaranteed but not tested on Propagation Delays.

3. Guaranteed but not tested.

SWITCHING CHARACTERISTICS OVER OPERATING RANGE

2915 tbl 07

FCT162701T FCT162701AT

Parameter Test Conditions

(1)

Min.

(2)

Max.

(2)

Min.

(2)

Max.

(2)

Unit

PROPAGATION DELAYS

1B1-18 to A1-18 Read path/latch 1.5 6.5 1.5 5.5 ns
2 LE (Low to Hi) to A1-18 Read path/latch 1.5 5.7 1.5 4.7 ns
3 CLK to

FF

Write path 2 7.0 2 6.0 ns

4 CLK to B1-18 Write path 1 6.0 1 5.2 ns

SETUP & HOLD TIMES

(3)

5A1-18 to CLK (Low to Hi) Setup Write path 2.5 — 2.5 — ns
6A1-18 to CLK (Low to Hi) Hold Write path 0 — 0 — ns
7B1-18 to LE (Hi to Low) Setup Read path/latch 3 — 3 — ns
8B1-18 to LE (Hi to Low) Hold Read path/latch 0 — 0 — ns
9

WCE, RCE

(Low) to CLK Setup Write path 3 — 3 — ns

10

WCE, RCE

(Low) to CLK Hold Write path 0 — 0 — ns

11

RESET

(Low) to CLK Setup Write path 3 — 3 — ns

12

RESET

(Low) to CLK Hold Write path 0 — 0 — ns

ENABLE & DISABLE TIMES

(3)

13

OEBA

Low to A1-18 Enable Write path 1.5 7.0 1.5 6.0 ns

14

OEBA

High to A1-18 Disable Write path 1.5 6.0 1.5 5.0 ns

15

OEAB

Low to B1-18 Enable Read path 1.5 7.0 1.5 6.0 ns

16

OEAB

High to B1-18 Disable Read path 1.5 6.0 1.5 5.0 ns

MINIMUM PULSE WIDTHS

17 CLK HIGH or LOW Pulse Width Write path 3.0 — 3.0 — ns
18 LE HIGH Pulse Width Read path/latch 3.0 — 3.0 — ns

5.15 8

IDT54/74FCT162701T/AT
FAST CMOS 18-BIT R/W BUFFER MILITARY AND COMMERCIAL TEMPERATURE RANGES

Pulse

Generator

R

T

D.U.T.

V

CC

V

IN

C

L

V

OUT

50pF

500

Ω

500

Ω

7.0V

3V

1.5V
0V

3V

1.5V
0V

3V

1.5V
0V

3V

1.5V

0V

DATA

INPUT

TIMING

INPUT

ASYNCHRONOUS CONTROL

PRESET

CLEAR

ETC.

SYNCHRONOUS CONTROL

t

SU

t

H

t

REM

t

SU

t

H

HIGH-LOW-HIGH

PULSE

LOW-HIGH-LOW

PULSE

t

W

1.5V

1.5V

SAME PHASE

INPUT TRANSITION

3V

1.5V
0V

1.5V

V

OH

t

PLH

OUTPUT

OPPOSITE PHASE

INPUT TRANSITION

3V

1.5V
0V

t

PLH

t

PHL

t

PHL

V

OL

CONTROL

INPUT

3V

1.5V
0V

3.5V

0V

OUTPUT

NORMALLY

LOW

OUTPUT

NORMALLY

HIGH

SWITCH
CLOSED

SWITCH
OPEN

V

OL

0.3V

0.3V

t

PLZ

t

PZL

t

PZH

t

PHZ

3.5V

0V

1.5V

1.5V

ENABLE DISABLE

V

OH

PRESET

CLEAR

CLOCK ENABLE

ETC.

ENABLE AND DISABLE TIMESPROPAGATION DELAY

SET-UP, HOLD AND RELEASE TIMES PULSE WIDTH

SWITCH POSITION

TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS

Test Switch

Disable Low

Enable Low

Closed

All Other Tests

Open

Open Drain

DEFINITIONS:

C

L= Load capacitance: includes jig and probe capacitance.

R

T = Termination resistance: should be equal to ZOUT of the Pulse

Generator.

2915 lnk 07

2915 drw 04

2915 drw 06

NOTES:

1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH

2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; t

F ≤ 2.5ns; tR ≤ 2.5ns

2915 drw 08

2915 drw 07

2915 drw 05

IDT54/74FCT162701T/AT
FAST CMOS 18-BIT R/W BUFFER MILITARY AND COMMERCIAL TEMPERATURE RANGES

5.15 9

ORDERING INFORMATION

X

Temperature

Range

XXXX

Device

Type

X

PackageXProcess

Blank

Commercial

B

MIL-STD-883, Class B

PV
PA
PF
E

Shrink Small Outline Package (SO56-1)
Thin Shrink Small Outline Package (SO56-2

)

Thin Very Small Outline Package (SO56-3)
CERPACK (E56-1)

162701T
162701AT

18-Bit R/W Buffer

-55°C to +125°C

-40°C to +85°C

54
74

IDT

FCT

2915 drw 09