Datasheet IDT54FCT162260CTPAB, IDT54FCT162260CTPF, IDT54FCT162260CTPFB, IDT54FCT162260CTPV, IDT54FCT162260CTPVB Datasheet (Integrated Device Technology Inc)

Integrated Device Technology, Inc.

FAST CMOS
12-BIT TRI-PORT
BUS EXCHANGER

IDT54/74FCT16260AT/CT/ET

IDT54/74FCT162260AT/CT/ET

FEATURES:

• Common features:

– 0.5 MICRON CMOS Technology

– High-speed, low-power CMOS replacement for

ABT functions

– Typical t
– Low input and output leakage ≤1µA (max.)

– ESD > 2000V per MIL-STD-883, Method 3015;
– Packages include 25 mil pitch SSOP, 19.6 mil pitch

TSSOP, 15.7 mil pitch TVSOP and 25 mil pitch Cerpack
– Extended commercial range of -40°C to +85°C
–VCC = 5V ±10%

• Features for FCT16260AT/CT/ET:

– High drive outputs (-32mA IOH, 64mA IOL)
– Power off disable outputs permit “live insertion”
– Typical VOLP (Output Ground Bounce) < 1.0V at

VCC = 5V, TA = 25°C

• Features for FCT162260AT/CT/ET:

– Balanced Output Drivers: ±24mA (commercial),
– Reduced system switching noise

– Typical VOLP (Output Ground Bounce) < 0.6V at

VCC = 5V,TA = 25°C

SK(o) (Output Skew) < 250ps

> 200V using machine model (C = 200pF, R = 0)

±16mA (military)

DESCRIPTION:

The FCT16260AT/CT/ET and the FCT162260AT/CT/ET
Tri-Port Bus Exchangers are high-speed 12-bit latched bus
multiplexers/transceivers for use in high-speed microproces­sor applications. These Bus Exchangers support memory
interleaving with latched outputs on the B ports and address
multiplexing with latched inputs on the B ports.

The Tri-Port Bus Exchanger has three 12-bit ports. Data
may be transferred between the A port and either/both of the
B ports. The latch enable (LE1B, LE2B, LEA1B and LEA2B)
inputs control data storage. When a latch-enable input is
HIGH, the latch is transparent. When a latch-enable input is
LOW, the data at the input is latched and remains latched until
the latch enable input is returned HIGH. Independent output
enables (

writing to the other port.
capacitance loads and low impedance backplanes. The

output buffers are designed with power off disable capability
to allow "live insertion" of boards when used as backplane
drivers.

with current limiting resistors. This offers low ground bounce,
minimal undershoot, and controlled output fall times - reduc­ing the need for external series terminating resistors.

OE1B

and

OE2B

) allow reading from one port while

The FCT16260AT/CT/ET are ideally suited for driving high

The FCT162260AT/CT/ET have balanced output drive

FUNCTIONAL BLOCK DIAGRAM

OE1B

LEA1B

LE1B

12

SEL

OEA

A

1:12

12

LE2B

LEA2B 12

OE2B

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

12

1

M
U

X

0

12

12

MILITARY AND COMMERCIAL TEMPERATURE RANGES AUGUST 1996

1996 Integrated Device Technology, Inc. 5.4 DSC-3032/6

A-1B

LATCH

1B-A

LATCH

2B-A

LATCH

A-2B

LATCH

12

1B1:12

12

12

2B1:12

3032 drw 01

1

IDT54/74FCT16260AT/CT/ET, 162260AT/CT/ET
FAST CMOS 12-BIT TRI-PORT BUS EXCHANGER MILITARY AND COMMERCIAL TEMPERATURES RANGES

PIN CONFIGURATIONS

OEA

LE1B

2B3

GND

2B
2B1

VCC

A1
A2
A3

GND

A
A5
A6
A7
A8
A9

GND

A10
A11
A12

VCC

1B1
1B2

GND

1B

LE2B

SEL

1
2
3
4

2

5
6
7
8
9
10
11

4

12
13
14

SO56-1
SO56-2

15

SO56-3
16
17
18
19
20
21
22
23
24
25

3

26

27

28

56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29

OE2B
LEA2B
2B

4

GND

5

2B
2B6
VCC
2B7
2B8
2B9
GND

10

2B
2B11
2B12
1B12
1B11
1B10
GND
1B

9

1B8
1B7
VCC
1B6
1B5
GND

4

1B
LEA1B
OE1B

OEA

LE1B

2B

GND

2B
2B1
VCC

A1
A2
A

GND

A4
A5
A6
A
A8
A9

GND

A10
A11

A
VCC
1B1
1B

GND

1B3

LE2B

SEL

1
2

3

3
4

2

5
6
7
8
9

3

10
11
12
13
14

E56-1

7

15
16
17
18
19
20

12

21
22
23

2

24

56
55
54
53
52
51
50
49

48

47
46
45
44

43

42
41
40
39
38
37
36
35
34
33

3225
26
27
28

31

30

29

OE2B
LEA2B

2B4
GND

5

2B
2B6
VCC

7

2B
2B8
2B9
GND
2B10
2B11
2B12
1B12
1B11

10

1B
GND
1B9
1B8
1B7
VCC

6

1B
1B5
GND

4

1B
LEA1B

OE1B

SSOP/

TSSOP/TVSOP

TOP VIEW

3032 drw 02

CERPACK
TOP VIEW

5.4 2

3032 drw 03

IDT54/74FCT16260AT/CT/ET, 162260AT/CT/ET
FAST CMOS 12-BIT TRI-PORT BUS EXCHANGER MILITARY AND COMMERCIAL TEMPERATURES RANGES

PIN DESCRIPTION

Signal I/O Description

A

(1:12) I/O Bidirectional Data Port A. Usually connected to the CPU's Address/Data bus.

(1:12) I/O Bidirectional Data Port 1B. Connected to the even path or even bank of memory.

1B
2B

(1:12) I/O Bidirectional Data Port 2B. Connected to the odd path or odd bank of memory.

LEA1B I Latch Enable Input for A-1B Latch. The Latch is open when LEA1B is HIGH. Data from the A-port is latched on

the HIGH to LOW transition of LEA1B.

LEA2B I Latch Enable Input for A-2B Latch. The Latch is open when LEA2B is HIGH. Data from the A-Port is latched on

the HIGH to LOW transition of LEA2B.

LE1B I Latch Enable Input for the 1B-A Latch. The Latch is open when LE1B is HIGH. Data from the 1B port is latched

on the HIGH to LOW transition of LE1B.

LE2B I Latch Enable Input for the 2B-A Latch. The Latch is open when LE2B is HIGH. Data from the 2B port is latched

on the HIGH to LOW transition of LE2B.

SEL I 1B or 2B Path Selection. When HIGH, SEL enables data transfer from 1B Port to A Port. When LOW, SEL enables

data transfer from 2B Port to A Port.

OEA

OE1B
OE2B

ABSOLUTE MAXIMUM RATINGS

Symbol Description Max. Unit

(2)

VTERM

(3)

VTERM

TSTG Storage Temperature –65 to +150 °C
IOUT DC Output Current –60 to +120 mA

NOTES:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT­INGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.

2. All device terminals except FCT162XXXT Output and I/O terminals.

3. Output and I/O terminals for FCT162XXXT.

CAPACITANCE (TA = +25°C, F = 1.0MHZ)

Symbol Parameter

CIN Input

CI/O I/O

NOTE:

1. This parameter is measured at characterization but not tested.

I Output Enable for A Port (Active LOW).
I Output Enable for 1B Port (Active LOW).

I Output Enable for 2B Port (Active LOW).

(1)

Terminal Voltage with Respect to
GND
Terminal Voltage with Respect to
GND

(1)

Conditions Typ. Max. Unit

VIN = 0V 3.5 6.0 pF

Capacitance

VOUT = 0V 3.5 8.0 pF

Capacitance

–0.5 to +7.0 V

–0.5 to

CC +0.5

V

V

3032 tbl 02

3032 tbl 03

3032 tbl 01

FUNCTION TABLES

(2)

Inputs Output

1B 2B SEL LE1B LE2B

OEA

OEA

A

HXHHXL H

LXHHXL L

XXHLXL A

(1)

XHLXHL H
XLLXHL L
XXLXLL A

(1)

XXXXXH Z

3032 tbl 04

Inputs Outputs

A LEA1BLEA2B

OE1B

OE1B

OE2B

OE2B

1B 2B

HHHLL H H

LHHLL L L

HHLLL H B

LHLLL L B

HLHLL B

LLHLL B

XLLLL B

(1)
(1)
(1)

(1)
(1)

H
L

(1)

B
XXXHH Z Z
X X X L H Active Z
X X X H L Z Active
X X X L L Active Active

NOTES:

1. Output level before the indicated steady-state input conditions were
established.

2. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
Z = High Impedance
↑ = LOW-to-HIGH Transition

3032 tbl 05

5.4 3

IDT54/74FCT16260AT/CT/ET, 162260AT/CT/ET
FAST CMOS 12-BIT TRI-PORT BUS EXCHANGER MILITARY AND COMMERCIAL TEMPERATURES RANGES

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE

Following Conditions Apply Unless Otherwise Specified:
Commercial: T

Symbol Parameter Test Conditions

VIH Input HIGH Level Guaranteed Logic HIGH Level 2.0 — — V
VIL Input LOW Level Guaranteed Logic LOW Level — — 0.8 V
II H Input HIGH Current (Input pins)

II L Input LOW Current (Input pins)

IOZH High Impedance Output Current VCC = Max. VO = 2.7V — — ±1 µA
IOZL (3-State Output pins)
VIK Clamp Diode Voltage VCC = Min., IIN = –18mA — –0.7 –1.2 V
IOS Short Circuit Current VCC = Max., VO = GND
VH Input Hysteresis — — 100 — mV
ICCL

ICCH
ICCZ

A = –40°C to +85°C, VCC = 5.0V ± 10%; Military: TA = –55°C to +125°C, VCC = 5.0V ± 10%

Input HIGH Current (I/O pins)

Input LOW Current (I/O pins)

(5)

(1)

(5)

VCC = Max. VI = VCC — — ±1 µA

(5)

(5)

VI = GND — — ±1

(5)

Min. Typ.

— — ±1

— — ±1

VO = 0.5V — — ±1

(3)

–80 –140 –225 mA

(2)

Max. Unit

Quiescent Power Supply Current VCC = Max., VIN = GND or VCC — 5 500 µA

3032 tbl 06

OUTPUT DRIVE CHARACTERISTICS FOR FCT16260T

Symbol Parameter Test Conditions

IO Output Drive Current VCC = Max., VO = 2.5V

(3)

(1)

Min. Typ.

–50 —–180 mA

VOH Output HIGH Voltage VCC = Min. IOH = –3mA 2.5 3.5 — V

VIN = VIH or VIL IOH = –12mA MIL.

VOL Output LOW Voltage VCC = Min.

IN = VIH or VIL

V

IOFF Input/Output Power Off Leakage

(5)

VCC = 0V, VIN or VO ≤ 4.5V — — ±1 µA

OH = –15mA COM'L.

I
IOH = –24mA MIL.

OH = –32mA COM'L.

I
IOL = 48mA MIL.

OL = 64mA COM'L.

I

2.4 3.5 — V

2.0 3.0 — V

(4)

— 0.2 0.55 V

(2)

Max. Unit

3032 tbl 07

OUTPUT DRIVE CHARACTERISTICS FOR FCT162260T

Symbol Parameter Test Conditions

IODL Output LOW Current VCC = 5V, VIN = VIH or VIL, VOUT = 1.5V
IODH Output HIGH Current VCC = 5V, VIN = VIH or V IL,
VOH Output HIGH Voltage VCC = Min.

V

IN = VIH or VIL

VOL Output LOW Voltage VCC = Min.

V

IN = VIH or VIL

NOTES:

1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.

2. Typical values are at Vcc = 5.0V, +25°C ambient.

3. Not more than one output should be tested at one time. Duration of the test should not exceed one second.

4. Duration of the condition can not exceed one second.

5. The test limit for this parameter is ± 5µA at T

A = –55°C.

(1)

(3)

VOUT = 1.5V

(3)

IOH = –16mA MIL.
I

OH = –24mA COM'L.

IOL = 16mA MIL.
I

OL = 24mA COM'L.

Min. Typ.

60 115 200 mA

–60 –115 –200 mA

2.4 3.3 — V

— 0.3 0.55 V

(2)

Max. Unit

3032 lnk 08

5.4 4

IDT54/74FCT16260AT/CT/ET, 162260AT/CT/ET
FAST CMOS 12-BIT TRI-PORT BUS EXCHANGER MILITARY AND COMMERCIAL TEMPERATURES RANGES

POWER SUPPLY CHARACTERISTICS

Symbol Parameter Test Conditions

∆ICC Quiescent Power Supply Current

TTL Inputs HIGH

ICCD Dynamic Power Supply Current

VCC = Max.
V

IN = 3.4V

(4)

VCC = Max.

(3)

Outputs Open

(1)

V

IN = VCC

VIN = GND

Min. Typ.

— 0.5 1.5 mA

— 60 100

One Output Port Enabled
LExx = V

CC

One Input Bit Toggling
One Output Bit Toggling
50% Duty Cycle

IC Total Power Supply Current

(6)

VCC = Max.
Outputs Open

VIN = VCC
VIN = GND

— 0.6 1.5

fi = 10MHz
50% Duty Cycle
One Output Port Enabled
LExx = V

CC

V

IN = 3.4V

V

IN = GND

— 0.9 2.3

One Input Bit Toggling
One Output Bit Toggling
VCC = Max.
Outputs Open

VIN = VCC
VIN = GND

— 1.8 3.5

fi = 2.5MHz
50% Duty Cycle
One Output Port Enabled
LExx = V

CC

V

IN = 3.4V

V

IN = GND

— 4.8 12.5

Twelve Input Bits Toggling
Twelve Output Bits Toggling

NOTES:

1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.

2. Typical values are at V

3. Per TTL driven input (V

4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.

5. Values for these conditions are examples of the I

6. I

C = IQUIESCENT + IINPUTS + IDYNAMIC

IC = ICC + ∆ICC DHNT + ICCD (fCPNCP/2 + fiNi)
I

CC = Quiescent Current (ICCL, ICCH and ICCZ)

CC = Power Supply Current for a TTL High Input (VIN = 3.4V)

∆I

H = Duty Cycle for TTL Inputs High

D
N

T = Number of TTL Inputs at DH

ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)

CP = Clock Frequency for Register Devices (Zero for Non-Register Devices)

f

CP = Number of Clock Inputs at fCP

N
fi = Input Frequency

i = Number of Inputs at fi

N

CC = 5.0V, +25°C ambient.

IN = 3.4V). All other inputs at VCC or GND.

CC formula. These limits are guaranteed but not tested.

(2)

Max. Unit

µA/

MHz

mA

(5)

(5)

3032 tbl 09

5.4 5

IDT54/74FCT16260AT/CT/ET, 162260AT/CT/ET
FAST CMOS 12-BIT TRI-PORT BUS EXCHANGER MILITARY AND COMMERCIAL TEMPERATURES RANGES

SWITCHING CHARACTERISTICS OVER OPERATING RANGE

FCT16260AT/162260AT FCT16260CT/162260CT FCT16260ET/162260ET

Com'l. Mil. Com'l. Mil. Com'l. Mil.

(1)

Symbol Parameter Condition

tPLH

Propagation Delay
A

tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL

X to 1BX or Ax to 2BX

Propagation Delay

X to AX or 2BX to AX

1B
Propagation Delay
LE

XB to AX

Propagation Delay
LEA1B to 1B
LEA2B to 2B

tPLH

Propagation Delay
SEL to A

tPHL
tPZH

Output Enable Time

OEA

tPZL

OE2B

tPHZ

Output Disable Time

OEA

tPLZ

OE2B

to A

to 2B

to A

to 2B

X

X,

X,

X or
X

OE1B

X

OE1B

X

to 1BX, or

to 1BX, or

CL = 50pF

R

L = 500Ω

tSU Set-Up Time, HIGH or LOW

(2)

Min.

Max. Min.

1.5 5.2 1.5 5.6 1.5 4.7 1.5 5.1 1.5 3.6 — — ns

1.5 5.6 1.5 5.9 1.5 5.0 1.5 5.4 1.5 3.6 — — ns

1.5 5.2 1.5 5.6 1.5 4.7 1.5 5.1 1.5 4.0 — — ns

1.5 4.7 1.5 5.2 1.5 4.4 1.5 4.8 1.5 4.0 — — ns

1.5 5.2 1.5 5.6 1.5 4.7 1.5 5.1 1.5 4.0 — — ns

1.5 5.7 1.5 6.1 1.5 5.1 1.5 5.4 1.5 4.4 — — ns

1.5 4.4 1.5 4.8 1.5 4.0 1.5 4.4 1.5 4.0 — — ns

1.5 — 1.5 — 1.0 — 1.0 — 1.0 — — — ns

Data to Latch

tH Hold Time, Latch to Data 1.0 — 1.5 — 1.0 — 1.5 — 1.0 — — — ns
tW Pulse Width, Latch HIGH
tSK(o) Output Skew

NOTES:

1. See test circuit and waveforms.

2. Minimum limits are guaranteed but not tested on Propagation Delays.

3. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.

4. This parameter is guaranteed but not tested.

(3)

(4)

3.0 — 3.0 — 3.0 — 3.0 — 3.0 — — — ns
— 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — — ns

(2)

Max. Min.

(2)

Max. Min.

(2)

Max. Min.

(2)

Max. Min.

(2)

Max. Unit

3032 tbl 10

5.4 6

IDT54/74FCT16260AT/CT/ET, 162260AT/CT/ET
FAST CMOS 12-BIT TRI-PORT BUS EXCHANGER MILITARY AND COMMERCIAL TEMPERATURES RANGES

TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS

V

CC

V

OUT

50pF

C

L

Pulse

Generator

V

IN

D.U.T.

T

R

500

500

Ω

Ω

3032 lnk 04

SWITCH POSITION

7.0V

DEFINITIONS:

L= Load capacitance: includes jig and probe capacitance.

C

T = Termination resistance: should be equal to ZOUT of the Pulse

R

Generator.

Test Switch

Open Drain
Disable Low

Enable Low

All Other Tests

SET-UP, HOLD AND RELEASE TIMES PULSE WIDTH

DATA

INPUT

TIMING

INPUT

ASYNCHRONOUS CONTROL

PRESET

CLEAR

ETC.

SYNCHRONOUS CONTROL

PRESET

CLEAR

CLOCK ENABLE

ETC.

t

t

REM

H

t

H

t

SU

t

SU

3V

1.5V
0V

3V

1.5V
0V

3V

1.5V
0V

3V

1.5V
0V

3032 lnk 05

LOW-HIGH-LOW

PULSE

HIGH-LOW-HIGH

PULSE

Closed

Open

3032 lnk 11

1.5V

t

W

1.5V

3032 lnk 06

PROPAGATION DELAY

SAME PHASE

INPUT TRANSITION

t

PLH

OUTPUT

t

OPPOSITE PHASE

INPUT TRANSITION

PLH

t

t

PHL

PHL

3V

1.5V
0V

OH

V

1.5V

V

OL

3V

1.5V
0V

3032 lnk 07

ENABLE AND DISABLE TIMES

ENABLE DISABLE

3V

CONTROL

INPUT

t

t

PHZ

PLZ

F ≤ 2.5ns; tR ≤ 2.5ns

t

PZL

OUTPUT

NORMALLY

OUTPUT

NORMALLY

HIGH

NOTES:

1. Diagram shown for input Control Enable-LOW and input Control Disable­HIGH

2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; t

LOW

SWITCH
CLOSED

t

PZH

SWITCH
OPEN

3.5V

1.5V

1.5V
0V

0.3V

0.3V

1.5V
0V

3.5V

V

OL

V

OH

0V

3032 lnk 08

5.4 7

IDT54/74FCT16260AT/CT/ET, 162260AT/CT/ET
FAST CMOS 12-BIT TRI-PORT BUS EXCHANGER MILITARY AND COMMERCIAL TEMPERATURES RANGES

ORDERING INFORMATION

IDT

Temperature

Range

FCT

X

XXXX

Device

Type

X

PackageXProcess

Blank
B

PV
PA
PF
E

16260AT
16260CT
16260ET
162260AT
162260CT
162260ET

54
74

Commercial
MIL-STD-883, Class B

Shrink Small Outline Package (SO56-1)
Thin Shrink Small Outline Package (SO56-2)
Thin Very Small Outline Package (SO56-3)
CERPACK (E56-1)

12-Bit Tri-Port Bus Exchanger

-55°C to +125°C

-40°C to +85°C

3032 drw 09

5.4 8