Datasheet IDT74FCT16543TPVB, IDT74FCT16543TPV, IDT74FCT16543TPFB, IDT74FCT16543TPAB, IDT74FCT16543TPA Datasheet (Integrated Device Technology)
...
Integrated Device Technology, Inc.
FAST CMOS
16-BIT LATCHED
TRANSCEIVER
IDT54/74FCT16543T/AT/CT/ET
IDT54/74FCT162543T/AT/CT/ET
FEATURES:
• Common features:
– 0.5 MICRON CMOS Technology
– High-speed, low-power CMOS replacement for
ABT functions
– Typical tSK(o) (Output Skew) < 250ps
– Low input and output leakage ≤1µA (max.)
– ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
– Packages include 25 mil pitch SSOP, 19.6 mil pitch
TSSOP, 15.7 mil pitch TVSOP and 25 mil pitch Cerpack
– Extended commercial range of -40°C to +85°C
–V
CC = 5V ±10%
• Features for FCT16543T/AT/CT/ET:
– High drive outputs (-32mA IOH, 64mA IOL)
– Power off disable outputs permit “live insertion”
– Typical VOLP (Output Ground Bounce) < 1.0V at
VCC = 5V, TA = 25°C
• Features for FCT162543T/AT/CT/ET:
– Balanced Output Drivers: ±24mA (commercial),
±16mA (military)
– Reduced system switching noise
– Typical VOLP (Output Ground Bounce) < 0.6V at
VCC = 5V,TA = 25°C
DESCRIPTION:
The FCT16543T/AT/CT/ET and FCT162543T/AT/CT/ET
16-bit latched transceivers are built using advanced dual metal
CMOS technology. These high-speed, low-power devices are
organized as two independent 8-bit D-type latched transceivers with separate input and output control to permit independent control of data flow in either direction. For example, the Ato-B Enable (x
the A port or to output data from the B port. x
latch function. When x
ent. A subsequent LOW-to-HIGH transition of x
puts the A latches in the storage mode. x
enable function on the B port. Data flow from the B port to the
A port is similar but requires using x
inputs. Flow-through organization of signal pins simplifies
layout. All inputs are designed with hysteresis for improved
noise margin.
The FCT16543T/AT/CT/ET are ideally suited for driving
high-capacitance loads and low-impedance backplanes. The
output buffers are designed with power off disable capability to
allow "live insertion" of boards when used as backplane drivers.
The FCT162543T/AT/CT/ET have balanced output drive
with current limiting resistors. This offers low ground bounce,
minimal undershoot, and controlled output fall times–reducing
the need for external series terminating resistors. The
FCT162543T/AT/CT/ET are plug-in replacements for the
FCT16543T/AT/CT/ET and 54/74ABT16543 for on-board bus
interface applications.
CEAB
) must be LOW in order to enter data from
LEAB
LEAB
is LOW, the latches are transpar-
OEAB
performs output
CEBA
, x
LEBA
controls the
LEAB
signal
, and x
OEBA
FUNCTIONAL BLOCK DIAGRAM
1
OEBA
1
CEBA
1
LEBA
1
OEAB
1
CEAB
1
LEAB
1A1
C
D
TO 7 OTHER CHANNELS
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
C
D
1B1
2618 drw 01
MILITARY AND COMMERCIAL TEMPERATURE RANGES SEPTEMBER 1996
1996 Integrated Device Technology, Inc. 5.12 DSC-2618/7
2OEBA
2CEBA
2LEBA
2OEAB
2CEAB
2
LEAB
2A1
C
D
C
D
TO 7 OTHER CHANNELS
B1
2
2618 drw 02
1
IDT54/74FCT16543T/AT/CT/ET, 162543T/AT/CT/ET
FAST CMOS 16-BIT LATCHED TRANSCEIVER MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
1
OEAB
1
LEAB
1
CEAB
GND
GND
GND
GND
2
CEAB
2
LEAB
OEAB
2
1A1
1
V
1
1
1A5
1
1
1
2A1
2
2
2
2
2
V
2
2A8
A
CC
A
A
A
A
A
A
A
A
A
A
CC
A
1OEAB
1LEAB
1CEAB
GND
1A1
1
A2
VCC
1
A3
1
A4
1A5
GND
A6
1
1
A7
1
A8
2A1
2
A2
A3
2
GND
A4
2
2
A5
A6
2
VCC
2
A7
2A8
GND
2CEAB
2LEAB
2OEAB
48
43
56
55
54
53
52
51
50
49
47
46
45
44
42
41
40
39
38
37
36
35
34
33
3225
31
30
29
1
OEBA
1
LEBA
1
CEBA
GND
1B1
B
2
1
V
CC
1B3
1
B
4
1
B
5
GND
B
6
1
1B7
1
B
8
2
B
1
B
2
2
2B3
GND
B
4
2
2
B
5
2
B
6
V
CC
2B7
2
B
8
GND
2
CEBA
2
LEBA
2
OEBA
1
2
3
4
5
2
6
7
3
4
8
9
10
11
6
7
8
2
3
12
13
14
15
16
17
SO56-1
SO56-2
SO56-3
18
4
5
6
19
20
21
22
7
23
24
26
27
28
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
26
27
28
E56-1
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
3225
31
30
29
OEBA
1
1LEBA
1CEBA
GND
B1
1
1
B2
VCC
1B3
1
B4
1
B5
GND
B6
1
1B7
1
B8
2
B1
2
B2
2B3
GND
B4
2
2
B5
2
B6
VCC
2B7
2
B8
GND
2CEBA
2LEBA
2OEBA
SSOP/
TSSOP/TVSOP
TOP VIEW
2618 drw 03
CERPACK
2618 drw 04
TOP VIEW
5.12 2
IDT54/74FCT16543T/AT/CT/ET, 162543T/AT/CT/ET
FAST CMOS 16-BIT LATCHED TRANSCEIVER MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN DESCRIPTION
Pin Names Description
x
OEAB
x
OEBA
x
CEAB
x
CEBA
x
LEAB
x
LEBA
xAx A-to-B Data Inputs or B-to-A 3-State Outputs
xBx B-to-A Data Inputs or A-to-B 3-State Outputs
ABSOLUTE MAXIMUM RATINGS
Symbol Description Max. Unit
(2)
VTERM
(3)
VTERM
TSTG Storage Temperature –65 to +150 °C
IOUT DC Output Current –60 to +120 mA
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
2. All device terminals except FCT162XXXT Output and I/O terminals.
3. Output and I/O terminals for FCT162XXXT.
A-to-B Output Enable Input (Active LOW)
B-to-A Output Enable Input (Active LOW)
A-to-B Enable Input (Active LOW)
B-to-A Enable Input (Active LOW)
A-to-B Latch Enable Input (Active LOW)
B-to-A Latch Enable Input (Active LOW)
Terminal Voltage with Respect to
GND
Terminal Voltage with Respect to
GND
2618 tbl 01
(1)
–0.5 to +7.0 V
–0.5 to
CC +0.5
V
2618 lnk 03
V
FUNCTION TABLE
(1, 2)
For A-to-B (Symmetric with B-to-A)
Latch Output
Inputs Status Buffers
x
CEAB
CEAB
x
LEAB
LEAB
x
OEAB
OEAB
xAx to xBx xBx
H X X Storing High Z
X H X Storing X
L L L Transparent Current A Inputs
L H L Storing Previous* A Inputs
L L H Transparent High Z
L H H Storing High Z
NOTES: 2618 tbl 02
1. * Before x
H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
2. A-to-B data flow shown; B-to-A flow control is the same, except using
x
CEBA
LEAB
LOW-to-HIGH Transition
, x
LEBA
and x
OEBA
.
CAPACITANCE (TA = +25°C, f = 1.0MHz)
Symbol Parameter
C
IN
Input
Capacitance
C
I/O
I/O
Capacitance
NOTE:
1. This parameter is measured at characterization but not tested.
(1)
Conditions Typ. Max. Unit
VIN = 0V 3.5 6.0 pF
V
OUT
= 0V 3.5 8.0 pF
2618 lnk 04
5.12 3
IDT54/74FCT16543T/AT/CT/ET, 162543T/AT/CT/ET
FAST CMOS 16-BIT LATCHED TRANSCEIVER MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: TA = –40°C to +85°C, VCC = 5.0V ± 10%; Military: TA = –55°C to +125°C, VCC = 5.0V ± 10%
Symbol Parameter Test Conditions
(1)
Min. Typ.
VIH Input HIGH Level Guaranteed Logic HIGH Level 2.0 — — V
VIL Input LOW Level Guaranteed Logic LOW Level — — 0.8 V
II H Input HIGH Current (Input pins)
Input HIGH Current (I/O pins)
II L Input LOW Current (Input pins)
Input LOW Current (I/O pins)
(5)
VCC = Max. VI = VCC — — ±1 µA
(5)
(5)
VI = GND — — ±1
(5)
— — ±1
— — ±1
IOZH High Impedance Output Current VCC = Max. VO = 2.7V — — ±1 µA
IOZL (3-State Output pins)
(5)
VO = 0.5V — — ±1
VIK Clamp Diode Voltage VCC = Min., IIN = –18mA — –0.7 –1.2 V
IOS Short Circuit Current VCC = Max., VO = GND
(3)
–80 –140 –225 mA
VH Input Hysteresis — — 100 — mV
ICCL
Quiescent Power Supply Current VCC = Max., VIN = GND or VCC — 5 500 µA
ICCH
ICCZ
(2)
Max. Unit
2618 lnk 05
OUTPUT DRIVE CHARACTERISTICS FOR FCT16543T
Symbol Parameter Test Conditions
IO Output Drive Current VCC = Max., VO = 2.5V
(3)
(1)
Min. Typ.
–50 —–180 mA
VOH Output HIGH Voltage VCC = Min. IOH = –3mA 2.5 3.5 — V
VIN = VIH or VIL IOH = –12mA MIL.
VOL Output LOW Voltage VCC = Min.
IN = VIH or VIL
V
IOFF Input/Output Power Off Leakage
(5)
VCC = 0V, VIN or VO ≤ 4.5V — — ±1 µA
OH = –15mA COM'L.
I
IOH = –24mA MIL.
OH = –32mA COM'L.
I
IOL = 48mA MIL.
OL = 64mA COM'L.
I
2.4 3.5 — V
2.0 3.0 — V
(4)
— 0.2 0.55 V
(2)
Max. Unit
2618 lnk 06
OUTPUT DRIVE CHARACTERISTICS FOR FCT162543T
Symbol Parameter Test Conditions
I
ODL
I
ODH
V
OH
V
OL
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient.
3. Not more than one output should be tested at one time. Duration of the test should not exceed one second.
4. Duration of the condition can not exceed one second.
5. The test limit for this parameter is ± 5µA at T
Output LOW Current VCC = 5V, V
Output HIGH Current VCC = 5V, V
Output HIGH Voltage VCC = Min.
IN
= V
IH
V
or V
Output LOW Voltage VCC = Min.
IN
= V
IH
V
A = –55°C.
or V
IN
= V
IH or VIL, VOUT
IN
= V
IH
IL
IL
or V
IL,
(1)
(3)
= 1.5V
= 1.5V
(3)
V
OUT
IOH = –16mA MIL.
OH
= –24mA COM'L.
I
IOL = 16mA MIL.
OL
= 24mA COM'L.
I
Min. Typ.
60 115 200 mA
–60 –115 –200 mA
2.4 3.3 — V
— 0.3 0.55 V
(2)
Max. Unit
2618 lnk 07
5.12 4
IDT54/74FCT16543T/AT/CT/ET, 162543T/AT/CT/ET
FAST CMOS 16-BIT LATCHED TRANSCEIVER MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
Symbol Parameter Test Conditions
∆I
CC Quiescent Power Supply VCC = Max. — 0.5 1.5 mA
Current TTL Inputs HIGH V
ICCD Dynamic Power Supply Current
(4)
IN = 3.4V
VCC = Max., Outputs Open VIN = VCC — 60 100 µA/
x
CEAB
x
CEBA
(3)
and x
= V
CC
OEAB
= GND V
(1)
IN = GND MHz
Min. Typ.
One Input Toggling
50% Duty Cycle
C Total Power Supply Current
I
(6)
VCC = Max., Outputs Open VIN = VCC — 0.6 1.5 mA
i = 10MHz VIN = GND
f
50% Duty Cycle
x
LEAB
, x
CEAB
and
x
OEAB
x
CEBA
= GND V
= V
CC VIN = GND
IN = 3.4V — 0.9 2.3
One Bit Toggling
(2)
Max. Unit
CC = Max., Outputs Open VIN = VCC — 2.4 4.5
V
fi = 2.5MHz VIN = GND
50% Duty Cycle
x
LEAB
, x
CEAB
and
x
OEAB
= GND V
x
CEBA
= VCC VIN = GND
IN = 3.4V — 6.4 16.5
Sixteen Bits Toggling
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
3. Per TTL driven input (V
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the I
6. I
C = IQUIESCENT + IINPUTS + IDYNAMIC
IC = ICC + ∆ICC DHNT + ICCD (fCPNCP/2 + fiNi)
I
CC = Quiescent Current (ICCL, ICCH and ICCZ)
CC = Power Supply Current for a TTL High Input (VIN = 3.4V)
∆I
H = Duty Cycle for TTL Inputs High
D
N
T = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
CP = Clock Frequency for Register Devices (Zero for Non-Register Devices)
f
CP = Number of Clock Inputs at fCP
N
fi = Input Frequency
i = Number of Inputs at fi
N
CC = 5.0V, +25°C ambient.
IN = 3.4V). All other inputs at VCC or GND.
CC formula. These limits are guaranteed but not tested.
(5)
(5)
2618 tbl 08
5.12 5
IDT54/74FCT16543T/AT/CT/ET, 162543T/AT/CT/ET
FAST CMOS 16-BIT LATCHED TRANSCEIVER MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
FCT16543T/162543T FCT16543AT/162543AT
Com'l. Mil. Com'l. Mil.
Symbol Parameter Condition
tPLH
Propagation Delay
tPHL
Transparent Mode
CL = 50pF
L = 500Ω
R
xAx to xBx or xBx to xAx
tPLH
Propagation Delay
tPHL
x
LEBA
tPZH
Output Enable Time
tPZL
x
OEBA
x
CEBA
tPHZ
Output Disable Time
tPLZ
x
OEBA
x
CEBA
to xAx, x
or x
or x
or x
or x
LEAB
OEAB
CEAB
to xAx or xBx
OEAB
CEAB
to xAx or xBx
to xBx
to xAx or xBx
to xAx or xBx
tSU Set-up Time HIGH or LOW
xAx or xBx to x
LEAB
or x
LEBA
tH Hold Time HIGH or LOW
xAx or xBx to x
tW x
LEBA
or x
LEAB
LEAB
or x
LEBA
Pulse Width
LOW
tSK(o) Output Skew
(3)
(1)
Min.
(2)
Max. Min.
(2)
Max. Min.
(2)
Max. Min.
(2)
Max. Unit
1.5 8.5 1.5 10.0 1.5 6.5 1.5 7.5 ns
1.5 12.5 1.5 14.0 1.5 8.0 1.5 9.0 ns
1.5 12.0 1.5 14.0 1.5 9.0 1.5 10.0 ns
1.5 9.0 1.5 13.0 1.5 7.5 1.5 8.5 ns
3.0 — 3.0 — 2.0 — 2.0 — ns
2.0 — 2.0 — 2.0 — 2.0 — ns
5.0 — 5.0 — 5.0 — 5.0 — ns
— 0.5 — 0.5 — 0.5 — 0.5 ns
2618 tbl 09
FCT16543CT/162543CT FCT16543ET/162543ET
Com'l. Mil. Com'l. Mil.
Symbol Parameter Condition
tPLH
Propagation Delay
tPHL
Transparent Mode
CL = 50pF
L = 500Ω
R
(1)
Min.
(2)
Max. Min.
(2)
Max. Min.
(2)
Max. Min.
(2)
Max. Unit
1.5 5.3 1.5 6.1 1.5 3.4 — — ns
xAx to xBx or xBx to xAx
tPLH
Propagation Delay
tPHL
x
LEBA
tPZH
Output Enable Time
tPZL
x
OEBA
x
CEBA
tPHZ
Output Disable Time
tPLZ
x
OEBA
x
CEBA
to xAx, x
or x
or x
or x
or x
LEAB
OEAB
CEAB
to xAx or xBx
OEAB
CEAB
to xAx or xBx
to xBx
to xAx or xBx
to xAx or xBx
tSU Set-up Time, HIGH or LOW
xAx or xBx to x
LEBA
or x
tH Hold Time HIGH or LOW
xAx or xBx to x
tW x
LEBA
or x
LEBA
LEAB
or x
Pulse Width
LEAB
LEAB
1.5 7.0 1.5 8.0 1.5 3.7 — — ns
1.5 8.0 1.5 9.0 1.5 4.8 — — ns
1.5 6.5 1.5 7.5 1.5 4.0 — — ns
2.0 — 2.0 — 1.0 — — — ns
2.0 — 2.0 — 1.0 — — — ns
5.0 — 5.0 — 3.0
(4)
———ns
LOW
tSK(o) Output Skew
NOTES: 2618 tbl 10
1. See test circuits and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
4. This limit is guaranteed but not tested.
(3)
— 0.5 — 0.5 — 0.5 — — ns
5.12 6
IDT54/74FCT16543T/AT/CT/ET, 162543T/AT/CT/ET
FAST CMOS 16-BIT LATCHED TRANSCEIVER MILITARY AND COMMERCIAL TEMPERATURE RANGES
TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS
V
CC
V
OUT
50pF
C
L
Pulse
Generator
V
IN
D.U.T.
T
R
500
500
Ω
Ω
2618 drw 05
SWITCH POSITION
7.0V
All Other Tests
DEFINITIONS:
L= Load capacitance: includes jig and probe capacitance.
C
T = Termination resistance: should be equal to ZOUT of the Pulse
R
Generator.
Test
Open Drain
Disable Low
Enable Low
SET-UP, HOLD AND RELEASE TIMES PULSE WIDTH
DATA
INPUT
TIMING
INPUT
ASYNCHRONOUS CONTROL
PRESET
CLEAR
ETC.
SYNCHRONOUS CONTROL
PRESET
CLEAR
CLOCK ENABLE
ETC.
t
t
REM
H
t
H
t
SU
t
SU
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
2618 drw 06
LOW-HIGH-LOW
PULSE
HIGH-LOW-HIGH
PULSE
Switch
Closed
Open
2618 lnk 10
1.5V
t
W
1.5V
2618 drw 07
SAME PHASE
INPUT TRANSITION
OUTPUT
OPPOSITE PHASE
INPUT TRANSITION
t
PLH
t
PLH
t
t
PHL
PHL
3V
1.5V
0V
V
OH
1.5V
V
OL
3V
1.5V
0V
2618 drw 08
ENABLE AND DISABLE TIMESPROPAGATION DELAY
ENABLE DISABLE
CONTROL
INPUT
t
PHZ
PLZ
t
0.3V
V
0.3V
2618 drw 09
F ≤ 2.5ns; tR ≤ 2.5ns
t
PZL
OUTPUT
NORMALLY
OUTPUT
NORMALLY
HIGH
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH
2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; t
LOW
SWITCH
CLOSED
t
PZH
SWITCH
OPEN
3.5V
1.5V
1.5V
0V
3V
1.5V
0V
3.5V
OL
V
OH
0V
5.12 7
IDT54/74FCT16543T/AT/CT/ET, 162543T/AT/CT/ET
FAST CMOS 16-BIT LATCHED TRANSCEIVER MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDT
Temperature
Range
X
FCT
XXXX
Device
X
PackageXProcess
Type
Blank
B
PV
PA
PF
E
16543T
Commercial
MIL-STD-883, Class B
Shrink Small Outline Package (SO56-1)
Thin Shrink Small Outline Package (SO56-2)
Thin Very Small Outline Package (SO56-3)
CERPACK (E56-1)
16-Bit Latched Transceiver
16543AT
16543CT
16543ET
162543T
162543AT
162543CT
162543ET
54
74
–55°C to +125°C
–40°C to +85°C
2618 drw 10
5.12 8
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