Datasheet IDT74ALVCH16245PA, IDT74ALVCH16245PF, IDT74ALVCH16245PV Datasheet (Integrated Device Technology Inc)

IDT74ALVCH16245
3.3V CMOS 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
3.3V CMOS 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS AND BUS-HOLD
FEA TURES:
• Typical tSK(o) (Output Skew) < 250ps
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0)
•VCC = 3.3V ± 0.3V, Normal Range
•VCC = 2.7V to 3.6V, Extended Range
•VCC = 2.5V ± 0.2V
• CMOS power levels (0.4
• Rail-to-Rail output swing for increased noise margin
• Available in SSOP, TSSOP, and TVSOP packages
DRIVE FEA TURES:
• High Output Drivers: ±24mA
• Suitable for heavy loads
APPLICA TIONS:
• 3.3V high speed systems
• 3.3V and lower voltage computing systems
µµ
µ W typ. static)
µµ
IDT74ALVCH16245
DESCRIPTION:
This 16-bit bus transceiver is built using advanced dual metal CMOS technology. The ALVCH16245 is designed for asynchronous communication between data buses. The control-function implementation minimizes external timing requirements.
This device can be used as two 8-bit transceivers or one 16-bit transceiver. It allows data transmission from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so that the buses are effectively isolated.
The ALVCH16245 has been designed with a ±24mA output driver. This driver is capable of driving a moderate to heavy load while maintaining speed performance.
The ALVCH16245 has “bus-hold” which retains the inputs’ last state whenever the input bus goes to a high impedance. This prevents floating inputs and eliminates the need for pull-up/down resistors.
FUNCTIONAL BLOCK DIAGRAM
1
1DIR
47
1A1
46
1
A2
44
1
A3
43
1
A4
41
1
A5
40
1
A6
38
1
A7
37
1
A8
24
2DIR
48
OE
1
36
2A1
2
B1
1
35
2
3
B2
1
5
B3
1
6
B4
1
8
B5
1
9
B6
1
11
B7
1
12
B8
1
A2
33
2
A3
32
2
A4
30
2
A5
29
2
A6
27
2
A7
26
2
A8
25
OE
2
13
B1
2
14
B2
2
16
B3
2
17
B4
2
19
B5
2
20
B6
2
22
B7
2
23
2
B8
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MARCH 1999INDUSTRIAL TEMPERATURE RANGE
© 1999 Integrated Device Technology, Inc. DSC-4697/1
1
IDT74ALVCH16245
3.3V CMOS 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
1DIR
1B1
1B2
GND
1
B3
1
B4
V
CC
B5
1 1
B6
GND
B7
1 1
B8
B1
2
2
B2
GND
2B3
B4
2
VCC
B5
2
B6
2
GND
B7
2 2B8
2
DIR
2 3 4
5 6
7 8 9
10 11
12 13 14 15 16 17 18
19
20 21 22
23 24
481 47 46 45 44
43 42
41
40 39 38
37 36 35
34 33 32
31
30 29 28 27 26 25
1OE 1A1
1A2
GND
A3
1
A4
1
V
CC
A5
1
A6
1
GND
A7
1 1
A8 A1
2 2
A2
GND
2A3
A4
2
VCC
2
A5
2
A6
GND
2
A7
2A8
OE
2
ABSOLUTE MAXIMUM RATINGS
Symbol Description Max Unit
(2)
VTERM VTERM TSTG Storage Temperature –65 to +150 °C IOUT DC Output Current –50 to +50 mA I
IK Continuous Clamp Current, ±50 mA
IOK Continuous Clamp Current, VO < 0 –50 mA I
CC Continuous Current through each ±100 mA
SS VCC or GND
I
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. V
3. All terminals except VCC.
Terminal Voltage with Respect to GND –0.5 to +4.6 V
(3)
Terminal Voltage with Respect to GND –0.5 to VCC+0.5 V
VI < 0 or VI > VCC
CC terminals.
(1)
CAPACITANCE (TA = +25°C, F = 1.0MHz)
Symbol Parameter
CIN Input Capacitance VIN = 0V 5 7 pF COUT Output Capacitance VOUT = 0V 7 9 pF C
I/O I/O Port Capacitance VIN = 0V 7 9 pF
NOTE:
1. As applicable to the device type.
(1)
Conditions Typ. Max. Unit
PIN DESCRIPTION
Pin Names Description
xOE Output Enable Inputs (Active LOW)
DIR Direction Control Inputs
xAx Side A Inputs or 3-State Outputs xBx Side B Inputs or 3-State Outputs
NOTE:
1. These pins have "Bus-Hold". All other pins are standard inputs, outputs, or I/Os.
(1)
(1)
SSOP/ TSSOP/ TVSOP
TOP VIEW
FUNCTION T ABLE (EACH 8-BIT SECTION)
Inputs
xOE xDIR Outputs
L L Bus B Data to Bus A L H Bus A Data to Bus B
H X High Z state
NOTE:
1. H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care
2
(1)
IDT74ALVCH16245
3.3V CMOS 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = –40°C to +85°C
Symbol Parameter Test Conditions Min. Typ.
VIH Input HIGH Voltage Level VCC = 2.3V to 2.7V 1.7 V
VCC = 2.7V to 3.6V 2
IL Input LOW Voltage Level VCC = 2.3V to 2.7V 0.7 V
V
VCC = 2.7V to 3.6V 0.8 IIH Input HIGH Current VCC = 3.6V VI = VCC ——±A IIL Input LOW Current VCC = 3.6V VI = GND ±A
IOZH High Impedance Output Current VCC = 3.6V VO = VCC ——±10 µA IOZL (3-State Output pins) VO = GND ±10
VIK Clamp Diode Voltage VCC = 2.3V, IIN = –18mA –0.7 –1.2 V
VH Input Hysteresis VCC = 3.3V 100 mV
I
CCL Quiescent Power Supply Current VCC = 3.6V 0.1 40 µA
ICCH VIN = GND or VCC ICCZ
ICC Quiescent Power Supply Current One input at VCC - 0.6V, other inputs at VCC or GND 750 µA
Variation
NOTE:
1. Typical values are at VCC = 3.3V, +25°C ambient.
(1)
Max. Unit
BUS-HOLD CHARACTERISTICS
Symbol Parameter
(1)
Test Conditions Min. Typ.
IBHH Bus-Hold Input Sustain Current VCC = 3V VI = 2V – 75 µA IBHL VI = 0.8V 75 — IBHH Bus-Hold Input Sustain Current VCC = 2.3V VI = 1.7V – 45 µ A IBHL VI = 0.7V 45
IBHHO Bus-Hold Input Overdrive Current VCC = 3.6V VI = 0 to 3.6V ±500 µA IBHLO
NOTES:
1. Pins with Bus-Hold are identified in the pin description.
2. Typical values are at VCC = 3.3V, +25°C ambient.
(2)
Max. Unit
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IDT74ALVCH16245
3.3V CMOS 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
OUTPUT DRIVE CHARACTERISTICS
Symbol Parameter Test Conditions
V
OH Output HIGH Voltage V CC = 2.3V to 3.6V IOH = – 0.1mA VCC – 0.2 V
VCC = 2.3V IOH = – 6mA 2 — VCC = 2.3V IOH = – 12mA 1.7 — VCC = 2.7V 2.2
CC = 3V 2.4
V VCC = 3V IOH = – 24mA 2
VOL Output LOW Voltage VCC = 2.3V to 3.6V IOL = 0.1mA 0.2 V
VCC = 2.3V IOL = 6mA 0.4
CC = 2.7V IOL = 12mA 0.4
V V
CC = 3V IOL = 24mA 0.55
NOTE:
1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range. TA = – 40°C to + 85°C.
(1)
Min. Max. Unit
IOL = 12mA 0.7
OPERATING CHARACTERISTICS, TA = 25°C
VCC = 2.5V ± 0.2V VCC = 3.3V ± 0.3V
Symbol Parameter Test Conditions Typical Typical Unit
CPD Power Dissipation Capacitance Outputs enabled CL = 0pF, f = 10Mhz 22 29 pF CPD Power Dissipation Capacitance Outputs disabled 4 5
SWITCHING CHARACTERISTICS
Symbol Parameter Min. Max. Min. Max. Min. Max. Unit
tPLH Propagation Delay 1 3.7 3.6 1 3 ns tPHL xAx to xYx tPZH Output Enable Time 1 5.7 5.4 1 4.4 ns tPZL xOE to xYx tPHZ Output Disable Time 1 5.2 4.6 1 4.1 ns tPLZ xOE to xYx
tSK( o) Output Skew
NOTES:
1. See TEST CIRCUITS AND WAVEFORMS. TA = – 40°C to + 85°C.
2. Skew between any two outputs of the same package and switching in the same direction.
(2)
(1)
VCC = 2.5V ± 0.2V VCC = 2.7V VCC = 3.3V ± 0.3V
—— — — —500 ps
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IDT74ALVCH16245
3.3V CMOS 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS TEST CONDITIONS
Symbol VCC
(1)
= 3.3V±0.3V VCC
VLOAD 6 6 2 x Vcc V
VIH 2.7 2.7 Vcc V VT 1.5 1.5 Vcc / 2 V
VLZ 300 300 150 mV
VHZ 300 300 150 mV
L 50 50 30 pF
C
(1, 2)
Pulse Generator
VIN
Test Circuit for All Outputs
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
NOTES:
1. Pulse Generator for All Pulses: Rate 1.0MHz; tF 2.5ns; tR 2.5ns.
2. Pulse Generator for All Pulses: Rate 1.0MHz; tF 2ns; tR 2ns.
RT
VCC
D.U.T.
(1)
= 2.7V VCC
VOU T
(2)
= 2.5V±0.2V Unit
500
500
CL
ALVC Link
SWITCH POSITION
Test Switch
Open Drain
Disable Low V
Enable Low
Disable High GND
Enable High
All Other Tests Open
LOAD
VLOAD Open
GND
SAME PHASE
INPUT TRANSITION
OUTPUT
OPPOSITE PHASE
INPUT TRANSITION
tPLH
tPLH
tPHL
tPHL
VIH VT 0V
V VT VOL
VIH VT 0V
ALVC Link
OH
Propagation Delay
DISABLE
tPLZ
tPHZ
VIH VT 0V
VLOAD/2 V
LZ
VOL VOH
VHZ 0V
ALVC Link
CONTROL
INPUT
OUTPUT
NORMALLY
LOW
OUTPUT
NORMALLY
HIGH
ENABLE
tPZL
SWITCH
CLOSED
tPZH
SWITCH
OPEN
VLOAD/2
VT
VT 0V
Enable and Disable Times
NOTE:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
DATA
INPU T
TIMING
INPUT
ASYNCHRONOUS
CONTROL
SYNCHRONOUS
CONTROL
t
SU
tSU
tH
tREM
tH
ALVC Link
VIH VT 0V
VIH VT 0V
VIH VT 0V
VIH VT 0V
INPUT
OUTPUT 1
OUTPUT 2
tPLH1
tPLH2
tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1
tSK (x)
t
PHL1
tPHL2
Output Skew - tSK(X)
NOTES:
1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs.
2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.
tSK (x)
VIH VT
0V V
OH
VT VOL
VOH VT
VOL
ALVC Link
Set-up, Hold, and Release Times
LOW-HIGH-LOW
PULSE
tW
HIGH-LOW-HIGH
PULSE
VT
VT
ALVC Link
Pulse Width
5
IDT74ALVCH16245
3.3V CMOS 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS
ORDERING INFORMATION
INDUSTRIAL TEMPERATURE RANGE
IDT XX
Temp. Range
ALVC
XXX
FamilyBus-Hold
XXX
XX
PackageDevice Type
PV PA PF
245
16
H
74
Shrink Small Outline Package Thin Shrink Small Outline Package Thin Very Small Outline Package
16-Bit Bus Transceiver with 3-State Outputs
Double-Density, ±24mA
Bus-Hold
–40°C to +85°C
CORPORATE HEADQUARTERS for SALES: for Tech Support:
2975 Stender Way 800-345-7015 or 408-727-6116 logichelp@idt.com Santa Clara, CA 95054 fax: 408-492-8674 (408) 654-6459
www.idt.com
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