Datasheet IDT54841CP, IDT54841AL, IDT54841ALB, IDT54841AP, IDT54841APB Datasheet (Integrated Device Technology Inc)
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Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES APRIL 1994
1994 Integrated Device Technology, Inc. 7.22 DSC-4603/2
IDT54/74FCT841A/B/C
HIGH-PERFORMANCE
CMOS BUS INTERFACE
LATCHES
FEATURES:
• Equivalent to AMD’s Am29841-46 bipolar registers in
pinout/function, speed and output drive over full temperature and voltage supply extremes
• IDT54/74FCT841A equivalent to FAST speed
• IDT54/74FCT841B 25% faster than FAST
• IDT54/74FCT841C 40% faster than FAST
• Buffered common latch enable, clear and preset inputs
•I
OL = 48mA (commercial) and 32mA (military)
• Clamp diodes on all inputs for ringing suppression
• CMOS power levels (1mW typ. static)
• TTL input and output level compatible
• CMOS output level compatible
• Substantially lower input current levels than AMD’s
bipolar Am29800 series (5µA max.)
• Product available in Radiation Tolerant and Radiation
Enhanced versions
• Military product compliant to MIL-STD-883, Class B
DESCRIPTION:
The IDT54/74FCT800 series is built using an advanced
dual metal CMOS technology.
The IDT54/74FCT840 series bus interface latches are
designed to eliminate the extra packages required to buffer
existing latches and provide extra data width for wider address/
data paths or buses carrying parity. The IDT54/74FCT841 is
a buffered, 10-bit wide version of the popular ‘373 function.
All of the IDT54/74FCT800 high-performance interface
family are designed for high-capacitance load drive capability,
while providing low-capacitance bus loading at both inputs
and outputs. All inputs have clamp diodes and all outputs are
designed for low-capacitance bus loading in the high-impedance state.
1
2607 drw 01
FUNCTIONAL BLOCK DIAGRAM
D0
D
CLR
Y
0
LE
Q
P
CLR
LE
OE
PRE
DN
D
CLR
Y
N
LE
Q
P
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
FAST is a trademark of National Semiconductor Co.
7.22 2
IDT54/74FCT841A/B/C
HIGH-PERFORMANCE CMOS BUS INTERFACE LATCHES MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
OE
D
0
D1
D2
D3
D4
D5
D6
D7
GND
Y
0
Y1
Y2
Y3
Y4
Y6
LE
Y
5
Y7
VCC
P24-1
D24-1
E24-1
&
SO24-2
D
8
D9
Y8
Y9
DIP/CERPACK/SOIC
TOP VIEW
INDEX
D2
Y2
Y3
Y4
NC
Y
5
OE
D
1
NC
V
CC
Y0
D8
GND
LE
Y
9
Y8
LCC
TOP VIEW
L28-1
D3
D4
NC
D
5
D6
D7
D0
Y1
Y6
Y7
D9
NC
32
20
19
1
4
5
6
7
8
1817161514
9
10
11
12 13
21
22
23
24
25
262728
1
2
3
4
5
6
7
8
9
10
13
14
15
16
17
18
19
20
11
12
21
22
23
24
2607 drw 02
2607 drw 03
PIN DESCRIPTION
FUNCTION TABLE
(1)
Name I/O Description
CLR
I When
CLR
is LOW, the outputs are
LOW if OE is LOW. When
CLR
is HIGH,
data can be entered into the latch.
DI I The latch data inputs.
LE I The latch enable input. The latches are
transparent when LE is HIGH. Input
data is latched on the HIGH-to-LOW
transition.
YI O The 3-state latch outputs.
OE
I The output enable control. When OE is
LOW, the outputs are enabled. When
OE
is HIGH, the outputs (Y
I) are in the
high-impedance (off) state.
PRE
I Preset line. When
PRE
is LOW, the
outputs are HIGH if OE is LOW. Preset
overrides
CLR
.
2607 tbl 01
Inputs
Inter-
nal
Out-
puts
CLR
CLR
PRE
PREOEOE
LE DIQ
I
Y
I
Function
H H H X X X Z High Z
H H H H L L Z High Z
H H H H H H Z High Z
H H H L X NC Z Latched (High Z)
H H L H L L L Transparent
H H L H H H H Transparent
H H L L X NC NC Latched
H L L X X H H Preset
L H L X X L L Clear
L L L X X H H Preset
L H H L X L Z Latched (High Z)
H L H L X H Z Latched (High Z)
NOTE: 2607 tbl 02
1. H = HIGH, L = LOW, X = Don’t Care, NC = No Change,
Z = High Impedance
IDT54/74FCT841A/B/C
HIGH-PERFORMANCE CMOS BUS INTERFACE LATCHES MILITARY AND COMMERCIAL TEMPERATURE RANGES
7.22 3
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol Rating Commercial Military Unit
VTERM
(2)
Terminal Voltage
with Respect to
GND
–0.5 to +7.0 –0.5 to +7.0 V
VTERM
(3)
Terminal Voltage
with Respect to
GND
–0.5 to VCC –0.5 to VCC V
TA Operating
Temperature
0 to +70 –55 to +125 °C
TBIAS Temperature
Under Bias
–55 to +125 –65 to +135 °C
TSTG Storage
Temperature
–55 to +125 –65 to +150 °C
PT Power Dissipation 0.5 0.5 W
IOUT DC Output
Current
120 120 mA
NOTE: 2607 tbl 03
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability. No terminal voltage
may exceed V
CC by +0.5V unless otherwise noted.
2. Input and V
CC terminals only.
3. Outputs and I/O terminals only.
CAPACITANCE (TA = +25°C, f = 1.0MHz)
Symbol Parameter
(1)
Conditions Typ. Max. Unit
C
IN
Input
Capacitance
VIN = 0V 6 10 pF
C
OUT
Output
Capacitance
V
OUT
= 0V 8 12 pF
NOTE: 2607 tbl 04
1. This parameter is measured at characterization but not tested.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: VLC = 0.2V; VHC = VCC – 0.2V
Commercial: TA = 0°C to +70°C, VCC = 5.0V ± 5%; Military: TA = –55°C to +125°C, VCC = 5.0V ± 10%
NOTES: 2607 tbl 05
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. This parameter is guaranteed but not tested.
Symbol Parameter Test Conditions
(1)
Min. Typ.
(2)
Max. Unit
VIH Input HIGH Level Guaranteed Logic HIGH Level 2.0 — — V
VIL Input LOW Level Guaranteed Logic LOW Level — — 0.8 V
II H Input HIGH Current VCC = Max. VI = VCC —— 5µA
VI = 2.7V — — 5
(4)
II L Input LOW Current VI = 0.5V — — –5
(4)
VI = GND — — –5
IOZH Off State (High Impedance) VCC = Max. VO = VCC ——10µA
Output Current VO = 2.7V — — 10
(4)
IOZL VO = 0.5V — — –10
(4)
VO = GND — — –10
VIK Clamp Diode Voltage VCC = Min., IN = –18mA — –0.7 –1.2 V
IOS Short Circuit Current VCC = Max.
(3)
, VO = GND –75 –120 — mA
VOH Output HIGH Voltage VCC = 3V, VIN = VLC or VHC, IOH = –32µAVHC VCC —V
VCC = Min. IOH = –300µAVHC VCC —
VIN = VIH or VIL IOH = –15mA MIL. 2.4 4.3 —
IOH = –24mA COM'L. 2.4 4.3 —
VOL Output LOW Voltage VCC = 3V, VIN = VLC or VHC, IOL = 300µA — GND VLC V
VCC = Min. IOL = 300µA — GND VLC
(4)
VIN = VIH or VIL IOL = 32mA MIL. — 0.3 0.5
IOL = 48mA COM'L. — 0.3 0.5
7.22 4
IDT54/74FCT841A/B/C
HIGH-PERFORMANCE CMOS BUS INTERFACE LATCHES MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
VLC = 0.2V; VHC = VCC – 0.2V
NOTES: 2607 tbl 06
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VC
C = 5.0V, +25°C ambient.
3. Per TTL driven input (V
IN = 3.4V); all other inputs at VCC or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
5. Values for these conditions are examples of the I
CC formula. These limits are guaranteed but not tested.
6. I
C = IQUIESCENT + IINPUTS + IDYNAMIC
IC = ICC + ∆ICC DHNT + ICCD (fCP/2 + fiNi)
I
CC = Quiescent Current
∆I
CC = Power Supply Current for a TTL High Input (VIN = 3.4V)
D
H = Duty Cycle for TTL Inputs High
N
T = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
f
CP = Clock Frequency for Register Devices (Zero for Non-Register Devices)
f
i = Input Frequency
N
i = Number of Inputs at fi
All currents are in milliamps and all frequencies are in megahertz.
Symbol Parameter Test Conditions
(1)
Min. Typ.
(2)
Max. Unit
ICC
Quiescent Power Supply Current VCC = Max.
V
IN ≥ VHC; V IN ≤ VLC
— 0.2 1.5 mA
∆ICC
Quiescent Power Supply Current
TTL Inputs HIGH
VCC = Max.
V
IN = 3.4V
(3)
— 0.5 2.0 mA
ICCD Dynamic Power Supply
Current
(4)
VCC = Max.
Outputs Open
OE
= GND
LE = V
CC
One Input Toggling
50% Duty Cycle
V
IN ≥ VHC
V
IN ≤ VLC
— 0.15 0.25 mA/
MHz
IC Total Power Supply Current
(6)
VCC = Max.
Outputs Open
fi = 10MHz
50% Duty Cycle
VIN ≥ VHC
V
IN ≤ VLC
(FCT)
— 1.7 4.0 mA
OE
= GND
LE = V
CC
One Bit Toggling
V
IN = 3.4V
V
IN = GND
— 2.0 5.0
VCC = Max.
Outputs Open
fi = 2.5MHz
50% Duty Cycle
VIN ≥ VHC
V
IN ≤ VLC
(FCT)
— 3.2 6.5
(5)
OE
= GND
LE = V
CC
Eight Bits Toggling
V
IN = 3.4V
V
IN = GND
— 5.2 14.5
(5)
IDT54/74FCT841A/B/C
HIGH-PERFORMANCE CMOS BUS INTERFACE LATCHES MILITARY AND COMMERCIAL TEMPERATURE RANGES
7.22 5
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
FCT841A FCT841B FCT841C
Com'l. Mil. Com'l. Mil. Com'l. Mil.
Symbol Parameter Conditions
(1)
Min.
(2)
Max. Min.
(2)
Max. Min.
(2)
Max. Min.
(2)
Max. Min.
(2)
Max. Min.
(2)
Max.
Unit
tPLH
tPHL
Propagation Delay
D
I to YI (LE = HIGH)
CL = 50pF
R
L = 500Ω
1.5 9.0 1.5 10.0 1.5 6.5 1.5 7.5 1.5 5.5 1.5 6.3 ns
CL = 300pF
(4)
RL = 500Ω
1.5 13.0 1.5 15.0 1.5 13.0 1.5 15.0 1.5 13.0 1.5 15.0
tPLH
tPHL
Propagation Delay
LE to Y
I
CL = 50pF
R
L = 500Ω
1.5 12.0 1.5 13.0 1.5 8.0 1.5 10.5 1.5 6.4 1.5 6.8 ns
CL = 300pF
(4)
RL = 500Ω
1.5 16.0 1.5 20.0 1.5 15.5 1.5 18.0 1.5 15.0 1.5 16.0
tPLH Propagation Delay,
PRE
to YI CL = 50pF 1.5 12.0 1.5 14.0 1.5 8.0 1.5 10.0 1.5 7.0 1.5 9.0 ns
tPHL RL = 500Ω 1.5 14.0 1.5 17.0 1.5 10.0 1.5 13.0 1.5 9.0 1.5 12.0
tPHL Propagation Delay,
CLR
to YI 1.5 13.0 1.5 14.0 1.5 10.0 1.5 11.0 1.5 9.0 1.5 10.0 ns
tPLH 1.5 14.0 1.5 17.0 1.5 10.0 1.5 10.0 1.5 9.0 1.5 9.0
tPZH
tPZL
Output Enable Time OE to YI CL = 50pF
R
L = 500Ω
1.5 11.5 1.5 13.0 1.5 8.0 1.5 8.5 1.5 6.5 1.5 7.3 ns
CL = 300pF
(4)
RL = 500Ω
1.5 23.0 1.5 25.0 1.5 14.0 1.5 15.0 1.5 12.0 1.5 13.0
tPHZ
tPLZ
Output Disable Time OE to Y I CL = 5pF
(4)
RL = 500Ω
1.5 7.0 1.5 9.0 1.5 6.0 1.5 6.5 1.5 5.7 1.5 6.0 ns
CL = 50pF
R
L = 500Ω
1.5 8.0 1.5 10.0 1.5 7.0 1.5 7.5 1.5 6.0 1.5 6.3
tSU Data to LE Set-up Time CL = 50pF 2.5 — 2.5 — 2.5 — 2.5 — 2.5 — 2.5 — ns
tH Data to LE Hold Time RL = 500Ω 2.5 — 3.0 — 2.5 — 2.5 — 2.5 — 2.5 — ns
tW LE Pulse Width
(3)
HIGH 4.0 — 5.0 — 4.0 — 4.0 — 4.0 — 4.0 — ns
tW
PRE
Pulse Width
(3)
LOW 5.0 — 7.0 — 4.0 — 4.0 — 4.0 — 4.0 — ns
tW
CLR
Pulse Width
(3)
LOW 4.0 — 5.0 — 4.0 — 4.0 — 4.0 — 4.0 — ns
tREM Recovery Time
PRE
to LE 4.0 — 4.0 — 4.0 — 4.0 — 4.0 — 4.0 — ns
tREM Recovery Time
CLR
to LE 3.0 — 3.0 — 3.0 — 3.0 — 3.0 — 3.0 — ns
NOTES: 2607 tbl 07
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. These parameters are guaranteed but not tested.
4. These conditions are guaranteed but not tested.
7.22 6
IDT54/74FCT841A/B/C
HIGH-PERFORMANCE CMOS BUS INTERFACE LATCHES MILITARY AND COMMERCIAL TEMPERATURE RANGES
Pulse
Generator
R
T
D.U.T.
V
CC
V
IN
CL
V
OUT
50pF
500Ω
500Ω
7.0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
DATA
INPUT
TIMING
INPUT
ASYNCHRONOUS CONTROL
PRESET
CLEAR
ETC.
SYNCHRONOUS CONTROL
tSU
tH
tREM
tSU
tH
HIGH-LOW-HIGH
PULSE
LOW-HIGH-LOW
PULSE
tW
1.5V
1.5V
SAME PHASE
INPUT TRANSITION
3V
1.5V
0V
1.5V
V
OH
tPLH
OUTPUT
OPPOSITE PHASE
INPUT TRANSITION
3V
1.5V
0V
tPLH tPHL
tPHL
VOL
CONTROL
INPUT
3V
1.5V
0V
3.5V
0V
OUTPUT
NORMALLY
LOW
OUTPUT
NORMALLY
HIGH
SWITCH
CLOSED
SWITCH
OPEN
VOL
0.3V
0.3V
t
PLZtPZL
tPZH tPHZ
3.5V
0V
1.5V
1.5V
ENABLE DISABLE
VOH
PRESET
CLEAR
CLOCK ENABLE
ETC.
TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS
SET-UP, HOLD AND RELEASE TIMES PULSE WIDTH
SWITCH POSITION
Test Switch
Open Drain
Disable Low Closed
Enable Low
All Other Tests Open
DEFINITIONS: 2607 tbl 08
CL = Load capacitance: includes jig and probe capacitance.
R
T = Termination resistance: should be equal to ZOUT of the Pulse
Generator.
ENABLE AND DISABLE TIMESPROPAGATION DELAY
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control DisableHIGH
2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; t
F ≤ 2.5ns; tR ≤ 2.5ns
2607 drw 04
IDT54/74FCT841A/B/C
HIGH-PERFORMANCE CMOS BUS INTERFACE LATCHES MILITARY AND COMMERCIAL TEMPERATURE RANGES
7.22 7
ORDERING INFORMATION
IDT XX
Temp. Range
XXXX
Device TypeXPackage
X
Process
Blank
B
P
D
E
L
SO
841A
841B
841C
Commercial
MIL-STD-883, Class B
Plastic DIP
CERDIP
CERPACK
Leadless Chip Carrier
Small Outline IC
10-Bit Non-Inverting Latch
54
74
–55°C to +125°C
0°C to +70°C
FCT
2607 drw 05
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