Datasheet IDT7383L45FFB, IDT7383L45GB, IDT7383L45JB, IDT7383L55FF, IDT7383L55G Datasheet (Integrated Device Technology Inc)
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Integrated Device Technology, Inc.
HIGH-SPEED
4K x 9 DUAL-PORT
STATIC RAM
IDT7014S
MILITARY AND COMMERCIAL TEMPERATURE RANGES OCTOBER 1996
©1996 Integrated Device Technology, Inc. DSC-2528/6
1
DESCRIPTION:
The IDT7014 is an extremely high-speed 4K x 9 Dual-Port
Static RAM designed to be used in systems where on-chip
hardware port arbitration is not needed. This part lends itself
to high-speed applications which do not need on-chip arbitration to manage simultaneous access.
The IDT7014 provides two independent ports with separate
control, address, and I/O pins that permit independent,
asynchronous access for reads or writes to any location in
memory. See functional description.
The IDT7014 utilitizes a 9-bit wide data path to allow for
parity at the user's option. This feature is especially useful in
data communication applications where it is necessary to use
a parity bit for transmission/reception error checking.
Fabricated using IDT’s high-performance technology, the
IDT7014 Dual-Ports typically operate on only 900mW of
power at maximum access times as fast as 12ns.
The IDT7014 is packaged in a 52-pin PLCC and a 64-pin
thin plastic quad flatpack (TQFP).
FUNCTIONAL BLOCK DIAGRAM
FEATURES:
• True Dual-Ported memory cells which allow simultaneous
access of the same memory location
• High-speed access
— Military: 20/25/35ns (max.)
— Commercial: 12/15/20/25ns (max.)
• Low-power operation
— IDT7014S
Active: 900mW (typ.)
• Fully asynchronous operation from either port
• TTL-compatible; single 5V (±10%) power supply
• Available in 52-pin PLCC and a 64-pin TQFP
• Industrial temperature range (–40°C to +85°C) is available, tested to military electrical specifications
COLUMN
CONTROL
COLUMN
CONTROL
MEMORY
ARRAY
LEFT SIDE
ADDRESS
DECODE
LOGIC
RIGHT SIDE
ADDRESS
DECODE
LOGIC
R/
W
R
OE
R
A0R- A
11R
R/
W
L
OE
L
A0L- A
11L
I/O0L- I/O
8L
2528 drw 01
I/O0R- I/O
8R
6.11
For latest information contact IDT’s web site at www.idt.com or fax-on-demand at 408-492-8391.
The IDT logo is a registereed trademark of Integrated Device Technology, Inc.
6.11 2
IDT7014S
HIGH-SPEED 4K x 9 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
(1,2)
NOTES:
1. All V
CC pins must be connected to power supply.
2. All ground pins must be connected to ground supply.
3. This text does not indicate the orientation of the actual part-marking
2528 tbl 02
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Ambient
Grade Temperature GND VCC
Military –55°C to +125°C 0V 5.0V ± 10%
Commercial 0°C to +70°C 0V 5.0V ± 10%
RECOMMENDED DC OPERATING
CONDTIONS
Symbol Parameter Min. Typ. Max. Unit
V
CC Supply Voltage 4.5 5.0 5.5 V
GND Supply Voltage 0 0 0 V
V
IH Input High Voltage 2.2 — 6.0
(2)
V
V
IL Input Low Voltage –0.5
(1)
— 0.8 V
NOTES: 2528 tbl 03
1. VIL > -1.5V for pulse width less than 10ns.
2. VTERM must not exceed Vcc + 0.5V.
2528 drw 02
IDT 7014
J52-1
PLCC
Top View
(3)
INDEX
A
6R
A
5R
A
4R
A
3R
A
2R
A
1R
A
0R
A
0L
A
1L
A
2L
A
3L
A
4L
A
5L
46
45
44
43
42
41
40
39
38
37
36
35
34
I/O
6L
A
6L
A
7L
A
8L
A
9L
A
10L
A
11L
V
CC
I/O
7L
8
9
10
11
12
13
14
15
16
17
18
19
20
474849505152
1
23456
7
33323130292827262524232221
OE
L
R/
W
L
GND
I/O
8L
I/O
6R
I/O
5R
I/O
7R
GND
R/
W
R
GND
OE
R
A
11R
A
10R
A
8R
A
7R
A
9R
I/O
8R
I/O
5L
V
CC
I/O
4L
I/O
3L
I/O
2L
I/O
1L
I/O
0L
I/O
0R
I/O
1R
I/O
2R
I/O
3R
I/O
4R
V
CC
INDEX
IDT7014
PN64-1
TQFP
Top View
(3)
8
9
10
11
12
13
14
15
16
1
2
3
GND
GND
4
5
N/C
N/C
N/C
N/C
6
7
46
45
44
43
42
41
40
39
38
37
36
35
34
47
48
33
17
18
19
20
32
31
30
29
28
27
26
25
24
23
22
21
49
50
51
52
63
62
61
60
59
58
57
56
55
54
53
64
N/C
A
10L
A
11L
N/C
R/
W
L
N/C
GND
A
9L
OE
L
V
CC
A
6L
A
7L
A
8L
I/O
8L
I/O
7L
I/O
6L
I/O
6R
GND
A
7R
A
8R
A
9R
A
10R
A
11R
N/C
N/C
N/C
I/O
7R
A
6R
GND
I/O
8R
R/
W
R
OE
R
2528 drw 03
I/O
5L
V
CC
I/O
4L
I/O
3L
I/O
2L
I/O
1L
I/O
0L
I/O
0R
I/O
1R
I/O
2R
I/O
3R
V
CC
I/O
4R
I/O
5R
A
5R
A
4R
A
3R
A
2R
A
1R
A
0R
A
0L
A
1L
A
2L
A
3L
A
4L
A
5L
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol Rating Commercial Military Unit
V
TERM
(2)
Terminal Voltage –0.5 to +7.0 –0.5 to +7.0 V
with Respect to
GND
V
TERM
(3)
Terminal Voltage –0.5 to Vcc –0.5 to Vcc V
T
A Operating 0 to +70 –55 to +125 °C
Temperature
T
BIAS Temperature –55 to +125 –65 to +135 °C
Under Bias
T
STG Storage –55 to +125 –65 to +150 °C
Temperature
I
OUT DC Output Current 50 50 mA
NOTES: 2528 tbl 01
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
2. V
TERM must not exceed Vcc + 0.5V for more than 25% of the cycle time
or 10ns maximum, and is limited to
< 20mA for the period of VTERM > Vcc
+ 0.5V.
6.11 3
IDT7014S
HIGH-SPEED 4K x 9 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE
(VCC = 5.0V ± 10%)
IDT7014S
Symbol Parameter Test Condition Min. Max. Unit
|I
LI| Input Leakage Current VCC = 5.5V, VIN = 0V to VCC —10µA
|I
LO| Output Leakage Current VOUT = 0V to VCC —10µA
V
OL Output Low Voltage IOL = 4mA — 0.4 V
V
OH Output High Voltage IOH = –4mA 2.4 — V
2528 tbl 04
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE
(VCC = 5V ± 10%)
IDT7014S12 IDT7014S15 IDT7014S20 IDT7014S25 IDT7014S35
Test Com'l. Only
Com'l. Only Mil. Only
Symbol Parameter Condition Version Typ. Max. Typ. Max. Typ. Max. Typ. Max. Typ. Max. Unit
I
CC Dynamic Outputs Open Mil. — — 160 260 155 260 150 255 150 250 mA
Operating f = f
MAX
(1)
Current (Both Com’l. 160 250 160 250 155 245 150 240 — —
Ports Active)
NOTE: 2528 tbl 05
1. At f = fmax, address inputs are cycling at the maximum read cycle of 1/tRC using the "AC Test Conditions" input levels of GND to 3V.
AC TEST CONDITIONS
Input Pulse Levels GND to 3.0V
Input Rise/Fall Times 3ns
Input Timing Reference Levels 1.5V
Output Reference Levels 1.5V
Output Load Figures 1, 2, and 3
2528 tbl 06
Symbol Parameter Condition
(2)
Max. Unit
C
IN Input Capacitance VIN = 3dV 9 pF
C
OUT Output Capacitance VOUT = 3dV 10 pF
2528 tbl 07
CAPACITANCE
(1)
(TA = +25°C, f = 1.0MHz) TQFP Package Only
NOTES:
1. This parameter is determined by device characteristics but is not tested.
2. 3dv references the interperlated capacitance when the input and output
signals swith from 0V to 3V or from 3V to 0V.
893Ω
30pF347Ω
DATAOUT
BUSY
INT
5V
5V
893Ω
5pF347Ω
DATAOUT
2528 drw 05
2528 drw 04
Figure 1. AC Output Test Load.
Figure 2. Output Test Load
(for t
HZ, tWZ, and tOW)
Including scope and jig.
Figure 3. Typical Output Derating (Lumped Capacitive Load).
1
2
3
4
5
6
7
8
20 40 10060 80 120 140 160 180 200
∆t
AA
(Typical, ns)
Capacitance (pF)
2528 drw 06
-1
0
- 10pF is the I/O capacitance
of this device, and 3 pF is the
AC Test Load Capacitance
6.11 4
IDT7014S
HIGH-SPEED 4K x 9 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES
7014S12 7014S15 7014S20 7014S25 7014S35
Com'l. Only Com'l. Only Mil. Only
Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
READ CYCLE
t
RC Read Cycle Time 12 — 15 — 20 — 25 — 35 — ns
t
AA Address Access Time — 12 — 15 — 20 — 25 — 35 ns
t
AOE Output Enable Access Time — 8 — 8 — 10 — 12 — 20 ns
t
OH Output Hold from Address Change 3 — 3 — 3 — 3 — 3 — ns
t
LZ Output Low-Z Time
(1, 2)
3—3—3—3—3—ns
t
HZ Output High-Z Time
(1, 2)
—7—7—9—11—15ns
NOTES: 2528 tbl 08
1. Transition is measured ±200mV from Low or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is determined by device characterization, but is not production tested.
TIMING WAVEFORM OF READ CYCLE NO. 1, EITHER SIDE
(1,2)
TIMING WAVEFORM OF READ CYCLE NO. 2, EITHER SIDE
(1, 3)
NOTES:
1. R/W = V
IH for Read Cycles.
2.OE = V
IL.
3. Addresses valid prior to OE transition LOW.
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE
ADDRESS
DATA
OUT
PREVIOUS DATA VALID DATA VALID
t
OH
t
OH
t
AA
t
RC
2528 drw 07
2528 drw 08
DATA
OUT
VALID DATA
t
AOE
OE
t
LZ
t
HZ
6.11 5
IDT7014S
HIGH-SPEED 4K x 9 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES
7014S12 7014S15 7014S20 7014S25 7014S35
Com'l. Only Com'l. Only Mil. Only
Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
WRITE CYCLE
t
WC Write Cycle Time 12 — 15 — 20 — 25 — 35 — ns
t
AW Address Valid to End-of-Write 10 — 14 — 15 — 20 — 30 — ns
t
AS Address Set-up Time 0 — 0 — 0 — 0 — 0 — ns
t
WP Write Pulse Width 10 — 12 — 15 — 20 — 30 — ns
t
WR Write Recovery Time 1 — 1 — 2 — 2 — 2 — ns
t
DW Data Valid to End-of-Write 8 — 10 — 12 — 15 — 25 — ns
t
HZ Output High-Z Time
(1, 2)
—7—7—9—11—15ns
t
DH Data Hold Time
(3)
0—0—0—0—0—ns
t
WZ Write Enabled to Output in High-Z
(1, 2)
—7—7—9—11—15ns
t
OW Output Active from End-of-Write
(1, 2, 3)
0—0—0—0—0—ns
t
WDD Write Pulse to Data Delay
(4)
—25—30—40—45—55ns
t
DDD Write Data Valid to Read Data Delay
(4)
—22—25—30—35—45ns
NOTES: 2528 tbl 09
1. Transition is measured ±200mV from Low or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. The specification for t
DH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values will vary
over voltage and temperature, the actual t
DH will always be smaller than the actual tOW.
4. Port-to-port delay through RAM cells from writing port to reading port, refer to “Timing Waveform of Write With Port-to-Port Read”.
2528 drw 09
R/
W
"A"
VALID
t
WC
MATCH
VALID
MATCH
t
WP
t
DW
t
WDD
t
DDD
ADDR
"A"
DATA
IN "A"
DATA
OUT "B"
ADDR
"B"
t
DH
TIMING WAVEFORM OF WRITE WITH PORT-TO-PORT READ
(1,2)
NOTES:
1. R/
W
"B" = VIH, Read cycle pass through.
2. All timing is the same for left and right ports. Port "A" may be either left or right port. Port "B" is opposite from port "A".
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE
6.11 6
IDT7014S
HIGH-SPEED 4K x 9 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES
TABLE I – READ/WRITE CONTROL
Left or Right Port
(1)
R/
WW
WW
W
OEOE
OEOE
OE
D0-8 Function
L X DATA
IN Data written into memory
H L DATA
OUT Data in memory output on port
X H Z High-impedance outputs
NOTE: 2528 tbl 10
1. AOL - A11L is not equal to AOR - A11R.
'H' = HIGH,'L' = LOW, 'X' = Don’t Care, and 'Z' = High-impedance.
TIMING WAVEFORM OF WRITE CYCLE
(1, 2, 3, 4, 5)
FUNCTIONAL DESCRIPTION
The IDT7014 provides two ports with separate control,
address, and I/O pins that permit independent access for
reads or writes to any location in memory. It lacks the chip
enable feature of most Dual-Ports, thus it operates in active
mode as soon as power is applied. Each port has its own
Output Enable control (OE). In the read mode, the port’s
OE
turns on the output drivers when set LOW. The user application
should avoid simultaneous write operations to the same
memory location. There is no on-chip arbitration circuitry to
resolve write priority and partial data from both ports may be
written. READ/WRITE conditions are illustrated in Table 1.
2528 drw 10
R/
W
t
WC
t
WP
t
DW
DATA
OUT
ADDRESS
DATA
IN
OE
t
AW
t
AS
(5)
t
WR
t
DH
t
OW
t
HZ
(4)
(3)(3)
t
WZ
(4)
NOTES:
1. R/W must be HIGH during all address transitions.
2. t
WR is measured from R/
W
going HIGH to the end of write cycle.
3. During this period, the I/O pins are in the output state, and input signals must not be applied.
4. Transition is measured ±200mV from the Low or High-impedance voltage with the Output Test Load (Figure 2).
5. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of t
WP or (tWZ + tDW) to allow the I/O drivers to turn off data to
be placed on the bus for the required t
DW. If
OE
is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can
be as short as the specified t
WP.
6.11 7
IDT7014S
HIGH-SPEED 4K x 9 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
2528 drw 11
IDT
XXXX A
999 A A
Device Type Power Speed Package Process/
Temperature
Range
Blank
PF
J
12
15
20
25
35
Commercial (0°C to +70°C)
64-pin TQFP (PN64-1)
52-pin PLCC (J52-1)
Speed in nanoseconds
Commercial Only
Military Only
Commercial Only
S
Standard Power
7014 36K (4K x 9-Bit) Dual-Port RAM
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