Datasheet IDT72V01L25J, IDT72V01L35J, IDT72V02L25J, IDT72V02L35J, IDT72V03L25J Datasheet (Integrated Device Technology Inc)

Integrated Device Technology, Inc.

3.3 VOLT CMOS
ASYNCHRONOUS FIFO
512 x 9, 1024 x 9, 2048 x 9, 4096 x 9

IDT72V01
IDT72V02
IDT72V03

IDT72V04

FEATURES:

• 3.3V family uses 70% less power than the 5 Volt 7201/
02/03/04 family

• 512 x 9 organization (72V01)

• 1024 x 9 organization (72V02)

• 2048 x 9 organization (72V03)

• 4096 X 9 organization (72V04)

• Functionally compatible with 720x family

• 25 ns access time

• Asynchronous and simultaneous read and write

• Fully expandable by both word depth and/or bit width

• Status Flags: Empty, Half-Full, Full

• Auto-retransmit capability

• Available in 32-pin PLCC and 28-pin SOIC Package (to
be determined)

• Industrial temperature range (-40

o

C to +85oC) is avail-

able, tested to military electrical specifications

DESCRIPTION:

The IDT72V01/72V02/72V03/72V04 are dual-port FIFO
memories that operate at a power supply voltage (Vcc)
between 3.0V and 3.6V. Their architecture, functional opera­tion and pin assignments are identical to those of the IDT7201/

7202/7203/7204. These devices load and empty data on a
first-in/first-out basis. They use Full and Empty flags to
prevent data overflow and underflow and expansion logic to
allow for unlimited expansion capability in both word size and
depth.

The reads and writes are internally sequential through the
use of ring pointers, with no address information required to
load and unload data. Data is toggled in and out of the devices
through the use of the Write (W) and Read (R) pins. The devices

have a maximum data access time as fast as 25 ns.

The devices utilize a 9-bit wide data array to allow for
control and parity bits at the user’s option. This feature is
especially useful in data communications applications where
it is necessary to use a parity bit for transmission/reception
error checking. They also feature a Retransmit (RT) capability
that allows for reset of the read pointer to its initial position
when RT is pulsed low to allow for retransmission from the
beginning of data. A Half-Full Flag is available in the single
device mode and width expansion modes.

The IDT72V01/72V02/72V03/72V04 is fabricated using
IDT’s high-speed CMOS technology. It has been designed for
those applications requiring asynchronous and simultaneous
read/writes in multiprocessing and rate buffer applications.

FUNCTIONAL BLOCK DIAGRAM

DATA INPUTS

0(D –D8)

W

R

XI

CEMOS is a trademark of Integrated Device Technology, Inc.
FAST is a trademark of National Semiconductor Co.

COMMERCIAL TEMPERATURE RANGE DECEMBER 1996

1996 Integrated Device Technology, Inc. DSC-3033/6

WRITE

CONTROL

WRITE

POINTER

THREE­STATE
BUFFERS

READ

CONTROL

FLAG

LOGIC

EXPANSION

LOGIC

For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.

RAM

ARRAY

512x 9
1024 x 9
2048 x 9
4096 x 9

DATA OUTPUTS

0(Q –Q8)

EF
FF

XO/HF

5.08 1

READ

POINTER

RS

RESET

LOGIC

FL/RT

2679 drw 01

IDT72V01/72V02/72V03/72V04 3.3 VOLT CMOS ASYNCHRONOUS FIFO
512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 COMMERCIAL TEMPERATURE RANGE

PIN CONFIGURATIONS

W

D8

1
2

28

27
D3 D5326
D2 D6425
D1 D7524
D0

XI RS

FF EF

Q0

623
722
821

920
Q1 Q710 19
Q2 Q611 18
Q3 Q512 17
Q8 Q413 16

GND

14 15

SMALL OUTLINE PACKAGE TO BE DETERMINED

ABSOLUTE MAXIMUM RATINGS

Symbol Rating Com’l. Unit

V

TERM Terminal Voltage –0.5 to +7.0 V

with Respect
to GND

T

A Operating 0 to +70 °C

Temperature

T

BIAS Temperature –55 to +125 °C

Under Bias

T

STG Storage –55 to +125 °C

Temperature

I

OUT DC Output 50 mA

Current

NOTE: 2679 tbl 01

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliabilty.

VCC
D4

FL/RT

XO/HF

R

2679 drw 02a

(1)

INDEX

D2 5

1 6

D

0 7

D

XI

FF

0 10

Q

1 11

Q

NC 12

2 13

Q

8

3

D

D

WNCV

3 2132 31 30

4

8

J32-1

9

CC

4

5

D

D

29
28
27
26
25
24
23
22
21

D6
D7
NC

FL/RT
RS
EF
XO/HF

7

Q
Q6

14 15 16 17 18 19 20

Q3Q

8

GND

NC

4Q5

R

Q

2679 drw 02b

PLCC

TOP VIEW

RECOMMENDED DC OPERATING
CONDITIONS

Symbol Rating Min. Typ. Max. Unit

CC Supply Voltage 3.0 3.3 3.6 V

V
GND Supply Voltage 0 0 0 V

(1)

IH

V

IL

V

NOTE: 2679 tbl 03

1. VIH = 2.6V for XI input (commercial).

2. 1.5V undershoots are allowed for 10ns once per cycle.

Input High Voltage 2.0 — VCC+0.5 V

(2)

Input Low Voltage — — 0.8 V

CAPACITANCE (TA = +25°C, f = 1.0 MHz)

Symbol Parameter

C

IN Input Capacitance VIN = 0V 8 pF
OUT Output Capacitance VOUT = 0V 8 pF

C

NOTE: 2679 tbl 02

1. This parameter is sampled and not 100% tested.

(1)

Condition Max. Unit

5.08 2

IDT72V01/72V02/72V03/72V04 3.3 VOLT CMOS ASYNCHRONOUS FIFO
512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 COMMERCIAL TEMPERATURE RANGE

DC ELECTRICAL CHARACTERISTICS

(Commercial: VCC = 3.3 V ± 0.3V, TA = 0°C to +70°C)

IDT72V01/72V02/ IDT72V01/72V02/

72V03/72V04 72V03/72V04

Commercial Commercial

t

A = 25 ns tA = 35 ns

Symbol Parameter Min. Typ. Max. Min. Typ. Max. Unit

(1)

LI

I

(2)

LO

I

OH Output Logic “1” Voltage IOH = –2mA 2.4 — — 2.4 — — V

V

OL Output Logic “0” Voltage IOL = 8mA — — 0.4 — — 0.4 V

V

(3,4)

CC1

I

(3)

CC2

I

CC3(L)

I

NOTES: 2679 tbl 05

1. Measurements with 0.4 ≤ VIN ≤ VCC.

2.R ≥ V

CC measurements are made with outputs open (only capacitive loading).

3. I

4. Tested at f = 20MHz.

Input Leakage Current (Any Input) –1 — 1 –1 — 1 µA
Output Leakage Current –10 — 10 –10 — 10 µA

Active Power Supply Current — 35 50 — 35 50 mA
Standby Current (R=W=RS=FL/RT=VIH)—58—58mA

(3)

Power Down Current (All Input = VCC - 0.2V) — — 0.3 — — 0.3 mA

IH, 0.4 ≤ VOUT ≤ VCC.

5.08 3

IDT72V01/72V02/72V03/72V04 3.3 VOLT CMOS ASYNCHRONOUS FIFO
512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 COMMERCIAL TEMPERATURE RANGE

AC ELECTRICAL CHARACTERISTICS

(Commercial: VCC = 3.3V±0.3V, TA = 0°C to +70°C)

Commercial Commercial
72V01L25/72V02L25 72V01L35/72V02L35
72V03L25/72V04L25 72V03L35/72V04L35

Symbol Parameter Min. Max. Min. Max. Unit

S Shift Frequency — 28.5 — 22.2 MHz

f

RC Read Cycle Time 35 — 45 — ns

t
t

A Access Time — 25 — 35 ns
RR Read Recovery Time 10 — 10 — ns

t

RPW Read Pulse Width

t
t

RLZ Read Pulse Low to Data Bus at Low Z
WLZ Write Pulse High to Data Bus at Low Z

t

DV Data Valid from Read Pulse High 5 — 5 — ns

t
t

RHZ Read Pulse High to Data Bus at High Z
WC Write Cycle Time 35 — 45 — ns

t

WPW Write Pulse Width

t
t

WR Write Recovery Time 10 — 10 — ns

DS Data Set-up Time 15 — 18 — ns

t

DH Data Hold Time 0 — 0 — ns

t

RSC Reset Cycle Time 35 — 45 — ns

t
t

RS Reset Pulse Width

RSS Reset Set-up Time

t

RSR Reset Recovery Time 10 — 10 — ns

t
t

RTC Retransmit Cycle Time 35 — 45 — ns

RT Retransmit Pulse Width

t

RTS Retransmit Set-up Time

t
t

RTR Retransmit Recovery Time 10 — 10 — ns
EFL Reset to Empty Flag Low — 35 — 45 ns

t

HFH,FFH Reset to Half-Full and Full Flag High — 35 — 45 ns

t
t

RTF Retransmit Low to Flags Valid — 35 — 45 ns
REF Read Low to Empty Flag Low — 25 — 30 ns

t

RFF Read High to Full Flag High — 25 — 30 ns

t

RPE Read Pulse Width after

t
t

WEF Write High to Empty Flag High — 25 — 30 ns
WFF Write Low to Full Flag Low — 25 — 30 ns

t

WHF Write Low to Half-Full Flag Low — 35 — 45 ns

t
t

RHF Read High to Half-Full Flag High — 35 — 45 ns
WPF Write Pulse Width after

t

XOL Read/Write to

t
t

XOH Read/Write to

XI

t

XIR

t
t

XIS

NOTES: 2679 tbl 06

1. Timings referenced as in AC Test Conditions. 3. Values guaranteed by design, not currently tested.

2. Pulse widths less than minimum value are not allowed. 4. Only applies to read data flow-through mode.

XI

Pulse Width

XI

Recovery Time 10 — 10 — ns

XI

Set-up Time 10 — 10 — ns

(2)

(3)

(3,4)

(3)

(2)

(2)

(3)

(2)

(3)

EF

High 25 — 35 — ns

FF

High 25 — 35 — ns

XO

Low — 25 — 35 ns

XO

High — 25 — 35 ns

(2)

25 — 35 — ns

5—5—ns
5—10—ns

— 18 — 20 ns

25 — 35 — ns

25 — 35 — ns
25 — 35 — ns

25 — 35 — ns
25 — 35 — ns

25 — 35 — ns

5.08 4

IDT72V01/72V02/72V03/72V04 3.3 VOLT CMOS ASYNCHRONOUS FIFO
512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 COMMERCIAL TEMPERATURE RANGE

AC TEST CONDITIONS

Input Pulse Levels GND to 3.0V
Input Rise/Fall Times 5ns
Input Timing Reference Levels 1.5V
Output Reference Levels 1.5V
Output Load See Figure 1

2679 tbl 08

SIGNAL DESCRIPTIONS

INPUTS:

DATA IN (D0 – D8)

Data inputs for 9-bit wide data.

CONTROLS:

RESET (

taken to a low state. During reset, both internal read and write
pointers are set to the first location. A reset is required after
power up before a write operation can take place. Both the

Read Enable (
the high state during the window shown in Figure 2, (i.e.,
t

RSS before the rising edge of

until tRSR after the rising edge of
will be reset to high after Reset (

WRITE ENABLE (

Full Flag (FF) is not set. Data set-up and hold times must be
adhered to with respect to the rising edge of the Write Enable
(W). Data is stored in the RAM array sequentially and
independently of any on-going read operation.

the next write operation, the Half-Full Flag (HF) will be set to
low and will remain set until the difference between the write
pointer and read pointer is less than or equal to one half of the
total memory of the device. The Half-Full Flag (HF) is then
reset by the rising edge of the read operation.

inhibiting further write operations. Upon the completion of a
valid read operation, the Full Flag (FF) will go high after t
allowing a valid write to begin. When the FIFO is full, the
internal write pointer is blocked from W, so external changes
in W will not affect the FIFO when it is full.

READ ENABLE (

Enable (R) provided the Empty Flag (EF) is not set. The data
is accessed on a First-In/First-Out basis, independent of any
ongoing write operations. After Read Enable (R) goes high,

RSRS)

Reset is accomplished whenever the Reset (RS) input is

RR) and Write Enable (

WW) inputs must be in

RSRS) and should not change

RSRS. Half-Full Flag (

HFHF)

RSRS).

WW)

A write cycle is initiated on the falling edge of this input if the

After half of the memory is filled and at the falling edge of

To prevent data overflow, the Full Flag (FF) will go low,

RFF,

RR)

A read cycle is initiated on the falling edge of the Read

5.0V

1.1K

TO

OUTPUT

PIN

680Ω

or equivalent circuit

Figure 1. Output Load

* Includes scope and jig capacitances.

30pF*

2679 drw 03

the Data Outputs (Q0 – Q8) will return to a high impedance
condition until the next Read operation. When all data has
been read from the FIFO, the Empty Flag (EF) will go low,
allowing the “final” read cycle but inhibiting further read
operations with the data outputs remaining in a high imped­ance state. Once a valid write operation has been accom­plished, the Empty Flag (EF) will go high after tWEF and a valid
Read can then begin. When the FIFO is empty, the internal
read pointer is blocked from R so external changes in R will not
affect the FIFO when it is empty.

FIRST LOAD/RETRANSMIT (

FLFL/

RTRT)

This is a dual-purpose input. In the Depth Expansion Mode,
this pin is grounded to indicate that it is the first loaded (see
Operating Modes). In the Single Device Mode, this pin acts as
the restransmit input. The Single Device Mode is initiated by
grounding the Expansion In (XI).

The IDT72V01/72V02/72V03/72V04 can be made to re­transmit data when the Retransmit Enable control (RT) input
is pulsed low. A retransmit operation will set the internal read
pointer to the first location and will not affect the write pointer.
Read Enable (R) and Write Enable (W) must be in the high
state during retransmit. This feature is useful when less than
512/1024/2048/4096 writes are performed between resets.
The retransmit feature is not compatible with the Depth
Expansion Mode and will affect the Half-Full Flag (HF), de­pending on the relative locations of the read and write point­ers.

EXPANSION IN (

XIXI)

This input is a dual-purpose pin. Expansion In (XI) is
grounded to indicate an operation in the single device mode.
Expansion In (XI) is connected to Expansion Out (XO) of the
previous device in the Depth Expansion or Daisy Chain Mode.

OUTPUTS:

FULL FLAG (

The Full Flag (FF) will go low, inhibiting further write op­eration, when the write pointer is one location less than the
read pointer, indicating that the device is full. If the read
pointer is not moved after Reset (RS), the Full-Flag (FF) will go

FFFF)

5.08 5

IDT72V01/72V02/72V03/72V04 3.3 VOLT CMOS ASYNCHRONOUS FIFO
512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 COMMERCIAL TEMPERATURE RANGE

low after 512/1024/2048/4096 writes to the IDT72V01/72V02/
72V03/72V04.

EMPTY FLAG (

EFEF)

The Empty Flag (EF) will go low, inhibiting further read
operations, when the read pointer is equal to the write pointer,
indicating that the device is empty.

EXPANSION OUT/HALF-FULL FLAG (

XOXO/

HFHF)

This is a dual-purpose output. In the single device mode,
when Expansion In (XI) is grounded, this output acts as an

RS

W

R

indication of a half-full memory.

After half of the memory is filled and at the falling edge of
the next write operation, the Half-Full Flag (HF) will be set low
and will remain set until the difference between the write
pointer and read pointer is less than or equal to one half of the
total memory of the device. The Half-Full Flag (HF) is then
reset by using rising edge of the read operation.

In the Depth Expansion Mode, Expansion In (XI) is con­nected to Expansion Out (XO) of the previous device. This
output acts as a signal to the next device in the Daisy Chain
by providing a pulse to the next device when the previous
device reaches the last location of memory.

tRSC

tRS

tRSS

tRSS

tEFL

t

RSR

EF

HF, FF

NOTES:

1. EF, FF, HF may change status during Reset, but flags will be valid at tRSC.

2. W and R = V

IH around the rising edge of

t

RS

.

t

RC

A

Figure 2. Reset

t

RR

R

t

Q0 – Q

RLZ

8

t

WPW

DATA OUT VALID DATA OUT VALID

t

WC

t

DV

t

WR

W

t

D0 – D

DS

8

DATA IN VALID DATA IN VALID

t

DH

HFH

, tFFHt

2679 drw 04

t

RPW

t

A

t

RHZ

Figure 3. Asynchronous Write and Read Operation

5.08 6

2679 drw 05

IDT72V01/72V02/72V03/72V04 3.3 VOLT CMOS ASYNCHRONOUS FIFO
512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 COMMERCIAL TEMPERATURE RANGE

W

FF

W

LAST WRITERIGNORED

WRITE

FIRST READ ADDITIONAL

READS

FIRST

WRITE

tWFF tRFF

2679 drw 06

Figure 4. Full Flag From Last Write to First Read

LAST READ

IGNORED

READ

FIRST WRITE ADDITIONAL

WRITES

FIRST
READ

R

tREF tWEF

EF

DATA OUT

HF, EF, FF

RT

W,R

t A

VALID VALID

Figure 5. Empty Flag From Last Read to First Write

t

RTC

t

RT

t

RTS

RTF

Figure 6. Retransmit

t

RTR

2679 drw 07

FLAG VALID

2679 drw 08

5.08 7

IDT72V01/72V02/72V03/72V04 3.3 VOLT CMOS ASYNCHRONOUS FIFO
512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 COMMERCIAL TEMPERATURE RANGE

W

t WEF

EF

tRPE

R

2679 drw 09

Figure 7. Minimum Timing for an Empty Flag Coincident Read Pulse

R

t RFF

FF

t

WPF

W

HF

2679 drw 10

Figure 8. Minimum Timing for an Full Flag Coincident Write Pulse

W

t

RHF

R

HALF-FULL OR LESS

t

WHF

MORE THAN HALF-FULL

HALF-FULL OR LESS

2678 drw 11

Figure 9. Half-Full Flag Timing

WRITE TO

LAST PHYSICAL

LOCATION

W

READ FROM

LAST PHYSICAL

LOCATION

R

t

t

XOL

XOH

t

XOL

t

XOH

XO

2679 drw 12

Figure 10. Expansion Out

5.08 8

IDT72V01/72V02/72V03/72V04 3.3 VOLT CMOS ASYNCHRONOUS FIFO
512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 COMMERCIAL TEMPERATURE RANGE

tXIRt XI

XI

t XIS

W

R

WRITE TO

FIRST PHYSICAL

LOCATION

Figure 11. Expansion In

OPERATING MODES:

Care must be taken to assure that the appropriate flag is
monitored by each system (i.e. FF is monitored on the device
where W is used; EF is monitored on the device where R is used).
For additional information, refer to Tech Note 8:

FIFOs on Full and Empty Boundary Conditions

Designing with FIFOs.

6:

Single Device Mode

A single IDT72V01/72V02/72V03/72V04 may be used
when the application requirements are for 512/1024/2048/
4096 words or less. IDT72V01/72V02/72V03/72V04 is in a
Single Device Configuration when the Expansion In (XI)
control input is grounded (see Figure 12).

Depth Expansion

The IDT72V01/72V02/72V03/72V04 can easily be adapted
to applications when the requirements are for greater than
512/1,024/2,048/4,096 words. Figure 14 demonstrates Depth
Expansion using three IDT72V01/72V02/72V03/72V04s. Any
depth can be attained by adding additional IDT72V01/72V02/
72V03/72V04s. The IDT72V01/72V02/72V03/72V04 oper­ates in the Depth Expansion mode when the following condi­tions are met:

1. The first device must be designated by grounding the First

Load (FL) control input.

2. All other devices must have FL in the high state.

3. The Expansion Out (XO) pin of each device must be tied to

the Expansion In (XI) pin of the next device. See Figure 14.

4. External logic is needed to generate a composite Full Flag

(FF) and Empty Flag (EF). This requires the ORing of all

EF

s and ORing of all FFs (i.e. all must be set to generate the

correct composite FF or EF). See Figure 14.

5. The Retransmit (RT) function and Half-Full Flag (HF) are

not available in the Depth Expansion Mode.

For additional information, refer to Tech Note 9:

FIFOs or FIFO Modules.

Operating

and Tech Note

Cascading

t XIS

READ FROM

FIRST PHYSICAL

LOCATION

2679 drw 13

Figure 13 demonstrates an 18-bit word width by using two
IDT72V01/72V02/72V03/72V04s. Any word width can be
attained by adding additional IDT72V01/72V02/72V03/72V04s
(Figure 13).

Bidirectional Operation

Applications which require data buffering between two
systems (each system capable of Read and Write operations)
can be achieved by pairing IDT72V01/72V02/72V03/72V04s
as shown in Figure 16. Both Depth Expansion and Width
Expansion may be used in this mode.

Data Flow-Through

Two types of flow-through modes are permitted, a read
flow-through and write flow-through mode. For the read flow­through mode (Figure 17), the FIFO permits a reading of a
single word after writing one word of data into an empty FIFO.
The data is enabled on the bus in (t

WEF + tA) ns after the rising

edge of W, called the first write edge, and it remains on the
bus until the R line is raised from low-to-high, after which the
bus would go into a three-state mode after t

RHZ ns. The

EF

line
would have a pulse showing temporary deassertion and then
would be asserted.

In the write flow-through mode (Figure 18), the FIFO
permits the writing of a single word of data immediately after
reading one word of data from a full FIFO. The R line causes
the FF to be deasserted but the W line being low causes it to
be asserted again in anticipation of a new data word. On the
rising edge of W, the new word is loaded in the FIFO. The

W

line must be toggled when FF is not asserted to write new data
in the FIFO and to increment the write pointer.

Compound Expansion

The two expansion techniques described above can be
applied together in a straightforward manner to achieve large
FIFO arrays (see Figure 15).

USAGE MODES:

Width Expansion

Word width may be increased simply by connecting the
corresponding input control signals of multiple devices. Sta­tus flags (EF, FF and HF) can be detected from any one device.

5.08 9

IDT72V01/72V02/72V03/72V04 3.3 VOLT CMOS ASYNCHRONOUS FIFO
512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 COMMERCIAL TEMPERATURE RANGE

DATA

(D)

IN

WRITE (W)

FULL FLAG (FF)

RESET (RS)

(HALF–FULL FLAG)

WRITE (W)

DATA IN (D)

FULL FLAG (FF)

RESET (RS)

EXPANSION IN (XI)

Figure 12. Block Diagram of Single 1024 x 9 FIFO

9918

9

HF

IDT

72V01
72V02
72V03
72V04

(HF)

IDT
72V01
72V02
72V03
72V04

9

9

READ (R)

DATA OUT (Q)
EMPTY FLAG (EF)

RETRANSMIT (RT)

HF

IDT

72V01
72V02
72V03
72V04

9

2679 drw 14

READ (R)
EMPTY FLAG (EF)

RETRANSMIT (RT)

XI XI

18

OUT

(Q)

2679 drw 15

DATA

Figure 13. Block Diagram of 1024 x 18 FIFO Memory Used in Width Expansion Mode

TABLE I—RESET AND RETRANSMIT

Single Device Configuration/Width Expansion Mode

Inputs Internal Status Outputs

Mode

Reset 0 X 0 Location Zero Location Zero 0 1 1
Retransmit 1 0 0 Location Zero Unchanged X X X
Read/Write 1 1 0 Increment

NOTE: 2679 tbl 09

1. Pointer will increment if flag is High.

RS

RS

RT

RT

XI

XI

Read Pointer Write Pointer

(1)

Increment

(1)

EF

EF

FF

FF

HF

HF

XXX

TABLE II—RESET AND FIRST LOAD TRUTH TABLE

Depth Expansion/Compound Expansion Mode

Inputs Internal Status Outputs

Mode

Reset First Device 0 0 (1) Location Zero Location Zero 0 1
Reset All Other Devices 0 1 (1) Location Zero Location Zero 0 1
Read/Write 1 X (1) X X X X

NOTE: 2679 tbl 10

1.XI is connected to XO of previous device. See Figure 14. RS = Reset Input, FL/RT = First Load/Retransmit, EF = Empty Flag Output, FF = Flag Full Output,

XI

= Expansion Input, HF = Half-Full Flag Output

RS

RS

FL

FL

XI

XI

Read Pointer Write Pointer

EF

EF

FF

FF

5.08 10

IDT72V01/72V02/72V03/72V04 3.3 VOLT CMOS ASYNCHRONOUS FIFO
512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 COMMERCIAL TEMPERATURE RANGE

XO

W

D

9

FF EF

99

IDT

72V01
72V02
72V03
72V04

FL

R

Q

CC

V

XI

XO

R, W, RS

FULL

RS

FF EF

IDT

72V01

9

72V02
72V03
72V04

FL

XI

XO

FF EF

IDT

72V01

9

72V02
72V03
72V04

FL

XI

Figure 14. Block Diagram of 3072 x 9 FIFO Memory (Depth Expansion)

•••

Q0–Q8 Q9 –Q17

IDT
72V01/72V02
72V03/72V04

DEPTH

EXPANSION

BLOCK

IDT
72V01/72V02
72V03/72V04

DEPTH

EXPANSION

BLOCK

•••

EMPTY

2679 drw 16

Q (N-8) -QN

IDT
72V01/72V02
72V03/72V04

DEPTH

EXPANSION

BLOCK

D 0 -D8 D9 -D17 D(N-8)-DN

D0–DN

Figure 15. Compound FIFO Expansion

NOTES:

1. For depth expansion block see section on Depth Expansion and Figure 14.

2. For Flag detection see section on Width Expansion and Figure 13.

5.08 11

•••

2679 drw 17

IDT72V01/72V02/72V03/72V04 3.3 VOLT CMOS ASYNCHRONOUS FIFO
512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 COMMERCIAL TEMPERATURE RANGE

DATA

Q

B 0-8

B 0-8

D

EF
HF

FF

R

B

B

B

W

B

B

2679 drw 18

W

A

FF

A

D

A 0-8

SYSTEM A SYSTEM B

A 0-8

Q

R

A

HF

A

EF

A

Figure 16. Bidirectional FIFO Mode

IN

IDT

72V01

IDT

72V02

7201A

72V03
72V04

IDT
72V01
72V02
72V03
72V04

W

tRPE

R

DATAOUT

W

FF

DATAIN

DATAOUT

EF

tREF

tWEF

tWLZ

tA

DATAOUT VALID

2679 drw 19

Figure 17. Read Data Flow-Through Mode

R

tWPF

t

RFF

t WFF t DH

DATAIN

VALID

t

DS

t

A

DATA

Figure 18. Write Data Flow-Through Mode

OUT

VALID

2679 drw 20

5.08 12

IDT72V01/72V02/72V03/72V04 3.3 VOLT CMOS ASYNCHRONOUS FIFO
512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 COMMERCIAL TEMPERATURE RANGE

ORDERING INFORMATION

IDT

XXXXX

Device Type

Power

XXX

L

Speed

X

PackageXProcess/

Temperature

Range

Blank

Commercial (0°C to + 70°C)

J Plastic Leaded Chip Carrier

25
35

Comercial Only
Access Time (t )Speed in Nanoseconds

A

L Low Power

72V01
72V02
72V03
72V04

512 x 9 FIFO
1024 x 9 FIFO
2048 x 9 FIFO
4096 x 9 FIFO

2679 drw 21

5.08 13