Datasheet IDT72T7285, IDT72T7295, IDT72T72105, IDT72T72115 Datasheet (IDT)

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2.5 VOLT HIGH-SPEED TeraSyncTM FIFO 72-BIT CONFIGURATIONS

16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72

FEATURES:

••

• Choose among the following memory organizations:

••

IDT72T7285 IDT72T7295 IDT72T72105 IDT72T72115

••

Up to 225 MHz Operation of Clocks

•

••

• User selectable HSTL/LVTTL Input and/or Output

••

• Read Enable & Read Clock Echo outputs aid high speed operation

••

•

User selectable Asynchronous read and/or write port timing

••

•

2.5V LVTTL or 1.8V, 1.5V HSTL Port Selectable Input/Ouput voltage

••

•

3.3V Input tolerant

••

Mark & Retransmit, resets read pointer to user marked position

•

••

• Write Chip Select (WCS) input disables Write Port HSTL inputs

••

• Read Chip Select (RCS) synchronous to RCLK

••

• Programmable Almost-Empty and Almost-Full flags, each flag can

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default to one of eight preselected offsets

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• Program programmable flags by either serial or parallel means

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• Selectable synchronous/asynchronous timing modes for Almost-

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Empty and Almost-Full flags

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• Separate SCLK input for Serial programming of flag offsets

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 16,384 x 72

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 32,768 x 72

 

 65,536 x 72

 

 131,072 x 72



IDT72T7285, IDT72T7295,

IDT72T72105, IDT72T72115

••

• User selectable input and output port bus-sizing

••

- x72 in to x72 out

- x72 in to x36 out

- x72 in to x18 out

- x36 in to x72 out

- x18 in to x72 out

••

• Big-Endian/Little-Endian user selectable byte representation

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•

Auto power down minimizes standby power consumption

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•

Master Reset clears entire FIFO

••

•

Partial Reset clears data, but retains programmable settings

••

Empty, Full and Half-Full flags signal FIFO status

•

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• Select IDT Standard timing (using EF and FF flags) or First Word

••

Fall Through timing (using OR and IR flags)

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• Output enable puts data outputs into high impedance state

••

• JTAG port, provided for Boundary Scan function

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• Available in 324-pin (19mm x 19mm)Plastic Ball Grid Array (PBGA)

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• Easily expandable in depth and width

••

• Independent Read and Write Clocks (permit reading and writing

••

simultaneously)

••

• High-performance submicron CMOS technology

••

• Industrial temperature range (–40

••

°°

°C to +85

°°

°C) is available

°°

FUNCTIONAL BLOCK DIAGRAM

WEN

WCLK/WR

WCS

ASYW

MRS

PRS

TCK

TRST

TMS TDO

TDI

Vref

WHSTL

RHSTL SHSTL

WRITE CONTROL

LOGIC

WRITE POINTER

CONTROL

LOGIC

BUS

CONFIGURATION

RESET

LOGIC

JTAG CONTROL

(BOUNDARY SCAN)

HSTL I/0

CONTROL

D0 -D

(x72, x36 or x18)

INPUT REGISTER

RAM ARRAY

16,384 x 72 32,768 x 72 65,536 x 72

131,072 x 72

OUTPUT REGISTER

Q0 -Qn (x72, x36 or x18)

OFFSET REGISTER

FLAG

LOGIC

READ POINTER

READ

CONTROL

LOGIC

EREN

ERCLK

SEN

SCLK

MARK

ASYR

RCLK/RD

REN RCS

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FF/IR PAF EF/OR PAE HF

FWFT/SI PFM FSEL0 FSEL1

IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The TeraSync FIFO is a trademark of Integrated Device Technology, Inc.

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES



SEPTEMBER 2003

DSC-5994/12

IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync 16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72

PIN CONFIGURATION

A1 BALL PAD CORNER



 72-BIT FIFO



COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

D59

D57

D51

D48

D45

D44

D41

D36

D33

D30

D27

D24

D21

D19 D20 D13

D18

PRS

D60

D61

D58 D62 D70

D55

D56

D53

D52

D50

D49

D47

D46

SEN

SCLK

D43

D42

D39

D40

D38

D37

D35

D34

D32

D31

D29

D28

D26

D25 Q27

D22

D23

D64

D65 D71D68

WHSTL

ASYW

VREF

D66

D67

D5D10

D14D17

D16 D15

D9D12

WCLK

D69

WEN

WCS

GND

MRS

GND

GND Q68MARK Q71

SHSTLFWFT/SI FS0OW IPFS1BEGND PFMBM

D4 TMS

GNDV

GND

GND GND

GND

TRST

TCK

GND

GNDV

TDO

TDI

PAF

EREN

PAELD HF

RCLKD63

REN

RCS

RHSTL

DDQ

GNDGND V

GND

GND GNDGND V

GND V

DDQ

GNDGND GNDGND GND V

GND

DDQVDDQ

DDQ

GND V

DDQ

GND

DDQ

GND

DDQ

GND

DDQ

Q5D11 D8D7 GND Q6Q1 Q9 Q12

Q69 Q66

ASYR

DDQ

DDQVDDQ

Q64

Q65

Q67Q70

Q58

Q55D54

Q52

DDQ

Q49

DDQ

Q46

DDQ

Q43

DDQ

Q40

DDQ

Q39

DDQ

Q36

DDQ

Q33

DDQ

Q30

DDQ

Q24

Q14GND Q0 Q2 Q11Q8Q3

Q15

Q16GND ERCLK Q4 Q13Q10Q7

Q61

Q59

Q56

Q53

Q50

Q47

Q44

Q41

Q38

Q35

Q32

Q29

Q26

Q23

Q18

Q17

Q62

Q60

Q57

Q54

Q51

Q48

Q45

Q42

Q37

Q34

Q31

Q28

Q25

Q22

Q20Q21

Q19

DDQ

Q63

12 345678910111213141516

PBGA: 1mm pitch, 19mm x 19mm (BB324-1, order code: BB)

TOP VIEW

17 18

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IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync 16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72



 72-BIT FIFO



COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

DESCRIPTION:

The IDT72T7285/72T7295/72T72105/72T72115 are exceptionally deep, extremely high speed, CMOS First-In-First-Out (FIFO) memories with clocked read and write controls and a flexible Bus-Matching x72/x36/x18 data flow. These FIFOs offer several key user benefits:

• Flexible x72/x36/x18 Bus-Matching on both read and write ports

• A user selectable MARK location for retransmit

• User selectable I/O structure for HSTL or LVTTL

• Asynchronous/Synchronous translation on the read or write ports

• The first word data latency period, from the time the first word is written to an

empty FIFO to the time it can be read, is fixed and short.

• High density offerings up to 9 Mbit

Bus-Matching TeraSync FIFOs are particularly appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match busses of unequal sizes.

Each FIFO has a data input port (D which can assume either a 72-bit, 36-bit or a 18-bit width as determined by the state of external control pins Input Width (IW), Output Width (OW), and BusMatching (BM) pin during the Master Reset cycle.

The input port can be selected as either a Synchronous (clocked) interface, or Asynchronous interface. During Synchronous operation the input port is controlled by a Write Clock (WCLK) input and a Write Enable (WEN) input. Data present on the Dn data inputs is written into the FIFO on every rising edge of WCLK when WEN is asserted. During Asynchronous operation only the WR input is used to write data into the FIFO. Data is written on a rising edge of WR, the WEN input should be tied to its active state, (LOW).

The output port can be selected as either a Synchronous (clocked) interface, or Asynchronous interface. During Synchronous operation the output port is controlled by a Read Clock (RCLK) input and Read Enable (REN) input. Data is read from the FIFO on every rising edge of RCLK when REN is asserted. During Asynchronous operation only the RD input is used to read data from the FIFO. Data is read on a rising edge of RD, the REN input should be tied to its active state, LOW. When Asynchronous operation is selected on the output port the FIFO must be configured for Standard IDT mode, also the RCS should be tied LOW and the OE input used to provide three-state control of the outputs, Qn.

The output port can be selected for either 2.5V LVTTL or HSTL operation, this operation is selected by the state of the RHSTL input during a master reset.

An Output Enable (OE) input is provided for three-state control of the outputs. A Read Chip Select (RCS) input is also provided, the RCS input is synchronized to the read clock, and also provides three-state control of the Qn data outputs. When RCS is disabled, the data outputs will be high impedance. During Asynchronous operation of the output port, RCS should be enabled, held LOW.

Echo Read Enable, EREN and Echo Read Clock, ERCLK outputs are provided. These are outputs from the read port of the FIFO that are required for high speed data communication, to provide tighter synchronization between the data being transmitted from the Qn outputs and the data being received by the input device. Data read from the read port is available on the output bus with respect to EREN and ERCLK, this is very useful when data is being read at high speed. The ERCLK and EREN outputs are non-functional when the Read port is setup for Asynchronous mode.

The frequencies of both the RCLK and the WCLK signals may vary from 0 to fMAX with complete independence. There are no restrictions on the frequency of the one clock input with respect to the other.

There are two possible timing modes of operation with these devices: IDT Standard mode and First Word Fall Through (FWFT) mode.

In IDT Standard mode, the first word written to an empty FIFO will not appear on the data output lines unless a specific read operation is performed. A read

n) and a data output port (Qn), both of

operation, which consists of activating REN and enabling a rising RCLK edge, will shift the word from internal memory to the data output lines.

In FWFT mode, the first word written to an empty FIFO is clocked directly to the data output lines after three transitions of the RCLK signal. A REN does not have to be asserted for accessing the first word. However, subsequent words written to the FIFO do require a LOW on REN for access. The state of the FWFT/SI input during Master Reset determines the timing mode in use.

For applications requiring more data storage capacity than a single FIFO can provide, the FWFT timing mode permits depth expansion by chaining FIFOs in series (i.e. the data outputs of one FIFO are connected to the corresponding data inputs of the next). No external logic is required.

These FIFOs have five flag pins, EF/OR (Empty Flag or Output Ready), FF/IR (Full Flag or Input Ready), HF (Half-full Flag), PAE (Programmable Almost-Empty flag) and PAF (Programmable Almost-Full flag). The EF and FF functions are selected in IDT Standard mode. The IR and OR functions are selected in FWFT mode. HF, PAE and PAF are always available for use, irrespective of timing mode.

PAE and PAF can be programmed independently to switch at any point in memory. Programmable offsets determine the flag switching threshold and can be loaded by two methods: parallel or serial. Eight default offset settings are also provided, so that PAE can be set to switch at a predefined number of locations from the empty boundary and the PAF threshold can also be set at similar predefined values from the full boundary. The default offset values are set during Master Reset by the state of the FSEL0, FSEL1, and LD pins.

For serial programming, SEN together with LD on each rising edge of SCLK, are used to load the offset registers via the Serial Input (SI). For parallel programming, WEN together with LD on each rising edge of WCLK, are used to load the offset registers via D

n. REN together with LD on each rising edge

of RCLK can be used to read the offsets in parallel from Qn regardless of whether serial or parallel offset loading has been selected.

During Master Reset (MRS) the following events occur: the read and write pointers are set to the first location of the FIFO. The FWFT pin selects IDT Standard mode or FWFT mode.

The Partial Reset (PRS) also sets the read and write pointers to the first location of the memory. However, the timing mode, programmable flag programming method, and default or programmed offset settings existing before Partial Reset remain unchanged. The flags are updated according to the timing mode and offsets in effect. PRS is useful for resetting a device in mid-operation, when reprogramming programmable flags would be undesirable.

It is also possible to select the timing mode of the PAE (Programmable AlmostEmpty flag) and PAF (Programmable Almost-Full flag) outputs. The timing modes can be set to be either asynchronous or synchronous for the PAE and PAF flags.

If asynchronous PAE/PAF configuration is selected, the PAE is asserted LOW on the LOW-to-HIGH transition of RCLK. PAE is reset to HIGH on the LOWto-HIGH transition of WCLK. Similarly, the PAF is asserted LOW on the LOWto-HIGH transition of WCLK and PAF is reset to HIGH on the LOW-to-HIGH transition of RCLK.

If synchronous PAE/PAF configuration is selected , the PAE is asserted and updated on the rising edge of RCLK only and not WCLK. Similarly, PAF is asserted and updated on the rising edge of WCLK only and not RCLK. The mode desired is configured during Master Reset by the state of the Programmable Flag Mode (PFM) pin.

This device includes a Retransmit from Mark feature that utilizes two control inputs, MARK and , RT (Retransmit). If the MARK input is enabled with respect to the RCLK, the memory location being read at that point will be marked. Any subsequent retransmit operation, RT goes LOW, will reset the read pointer to this ‘marked’ location.

IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync 16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72



 72-BIT FIFO



COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

DESCRIPTION (CONTINUED)

The device can be configured with different input and output bus widths as

shown in Table 1.

A Big-Endian/Little-Endian data word format is provided. This function is useful when data is written into the FIFO in long word format (x36/x18) and read out of the FIFO in small word (x18/x9) format. If Big-Endian mode is selected, then the most significant byte (word) of the long word written into the FIFO will be read out of the FIFO first, followed by the least significant byte. If Little-Endian format is selected, then the least significant byte of the long word written into the FIFO will be read out first, followed by the most significant byte. The mode desired is configured during master reset by the state of the Big-Endian (BE) pin. See Figure 5 for Bus-Matching Byte Arrangement.

The Interspersed/Non-Interspersed Parity (IP) bit function allows the user to select the parity bit in the word loaded into the parallel port (D0-Dn) when programming the flag offsets. If Interspersed Parity mode is selected, then the FIFO will assume that the parity bit is located in bit positions D8, D17, D26 and D35 during the parallel programming of the flag offsets. If Non-Interspersed Parity mode is selected, then D8 and D17 are assumed to be valid bits. IP mode is selected during Master Reset by the state of the IP input pin.

If, at any time, the FIFO is not actively performing an operation, the chip will automatically power down. Once in the power down state, the standby supply current consumption is minimized. Initiating any operation (by activating control inputs) will immediately take the device out of the power down state.

Both an Asynchronous Output Enable pin (OE) and Synchronous Read Chip Select pin (RCS) are provided on the FIFO. The Synchronous Read Chip Select is synchronized to the RCLK. Both the output enable and read chip select control the output buffer of the FIFO, causing the buffer to be either HIGH impedance or LOW impedance.

A JTAG test port is provided, here the FIFO has fully functional Boundary Scan feature, compliant with IEEE 1449.1 Standard Test Access Port and Boundary Scan Architecture.

The TeraSync FIFO has the capability of operating its ports (write and/or read) in either LVTTL or HSTL mode, each ports selection independent of the other. The write port selection is made via WHSTL and the read port selection via RHSTL. An additional input SHSTL is also provided, this allows the user to select HSTL operation for other pins on the device (not associated with the write or read ports).

The IDT72T7285/72T7295/72T72105/72T72115 are fabricated using IDT’s high speed submicron CMOS technology.

IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync 16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72



 72-BIT FIFO



COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

PARTIAL RESET (PRS)

WRITE CLOCK (WCLK/WR)

WRITE ENABLE (WEN)

WRITE CHIP SELECT (WCS)

LOAD (LD)

SERIAL CLOCK (SCLK)

SERIAL ENABLE(SEN)

FIRST WORD FALL THROUGH/

SERIAL INPUT (FWFT/SI)

FULL FLAG/INPUT READY (FF/IR)

PROGRAMMABLE ALMOST-FULL (PAF)

INPUT WIDTH (IW)

MASTER RESET (MRS)

READ CLOCK (RCLK/RD) READ ENABLE (REN)

IDT 72T7285 72T7295

72T72105 72T72115

(x72, x36, x18) DATA OUT (Q0 - Qn)(x72, x36, x18) DATA IN (D0 - Dn)

RCLK ECHO, ERCLK

REN ECHO, EREN

MARK RETRANSMIT (RT) EMPTY FLAG/OUTPUT READY (EF/OR)

PROGRAMMABLE ALMOST-EMPTY (PAE) HALF-FULL FLAG (HF) BIG-ENDIAN/LITTLE-ENDIAN (BE)

INTERSPERSED/ NON-INTERSPERSED PARITY (IP)

BUS-

OUTPUT WIDTH (OW)

MATCHING

(BM)

OUTPUT ENABLE (OE)

READ CHIP SELECT (RCS)

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Figure 1. Single Device Configuration Signal Flow Diagram

TABLE 1 — BUS-MATCHING CONFIGURATION MODES

BM I W OW Write Port Width Read Port Width

L L L x72 x72 H L L x72 x36 H L H x72 x18 H H L x36 x72 H H H x18 x72

NOTE:

1. Pin status during Master Reset.

IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync 16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72



 72-BIT FIFO



COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

PIN DESCRIPTION

Symbol Name I/O TYPE Description

(1)

ASYR

ASYW

EF/OR Empty Flag/ HSTL-LVTTL In the IDT Standard mode, the EF function is selected. EF indicates whether or not the FIFO memory is empty.

ERCLK RCLK Echo HSTL-LVTTL Read clock Echo output, only available when the Read is setup for Synchronous mode.

EREN Read Enable Echo HSTL-LVTTL Read Enable Echo output, only available when the Read is setup for Synchronous mode.

FF/IR Full Flag/ HSTL-LVTTL In the IDT Standard mode, the FF function is selected. FF indicates whether or not the FIFO memory is

FSEL0

FSEL1

FWFT/ First Word Fall HSTL-LVTTL During Master Reset, selects First Word Fall Through or IDT Standard mode. After Master Reset, this pin

SI Through/Serial In INPUT functions as a serial input for loading offset registers. If Asynchronous operation of the read port has been

HF Half-Full Flag HSTL-LVTTL HF indicates whether the FIFO memory is more or less than half-full.

LD Load HSTL-LVTTL This is a dual purpose pin. During Master Reset, the state of the LD input along with FSEL0 and FSEL1,

MARK Mark for Retransmit HSTL-LVTTL When this pin is asserted the current location of the read pointer will be marked. Any subsequent Retransmit

MRS Master Reset HSTL-LVTTL MRS initializes the read and write pointers to zero and sets the output register to all zeroes. During Master

OE Output Enable HSTL-LVTTL OE provides Asynchronous three-state control of the data outputs, Q

Asynchronous LVTTL A HIGH on this input during Master Reset will select Synchronous read operation for the output port. A LOW Read Port INPUT will select Asynchronous operation. If Asynchronous is selected the FIFO must operate in IDT Standard mode.

(1)

Asynchronous LVTTL A HIGH on this input during Master Reset will select Synchronous write operation for the input port. A LOW Write Port INPUT will select Asynchronous operation.

(1)

Big-Endian/ LVTTL During Master Reset, a LOW on BE will select Big-Endian operation. A HIGH on BE during Master Reset Little-Endian INPUT will select Little-Endian format.

(1)

Bus-Matching LVTTL BM works with IW and OW to select the bus sizes for both write and read ports. See Table 1 for bus size

INPUT configuration.

0–D71 Data Inputs HSTL-LVTTL Data inputs for a 72-, 36- or 18-bit bus. When in 36- or 18-bit mode, the unused input pins are in a don’t care

INPUT state.

Output Ready OUTPUT In FWFT mode, the OR function is selected. OR indicates whether or not there is valid data available at the

outputs.

OUTPUT

Input Ready OUTPUT full. In the FWFT mode, the IR function is selected. IR indicates whether or not there is space available for

writing to the FIFO memory.

(1)

Flag Select Bit 0 LVTTL During Master Reset, this input along with FSEL1 and the LD pin, will select the default offset values for the

INPUT programmable flags PAE and PAF. There are up to eight possible settings available.

(1)

Flag Select Bit 1 LVTTL During Master Reset, this input along with FSEL0 and the LD pin will select the default offset values for the

INPUT programmable flags PAE and PAF. There are up to eight possible settings available.

selected then the FIFO must be set-up in IDT Standard mode.

OUTPUT

(1)

Interspersed Parity LVTTL During Master Reset, a LOW on IP will select Non-Interspersed Parity mode. A HIGH will select Interspersed

INPUT Parity mode.

(1)

Input Width LVTTL This pin, along with OW and BM, selects the bus width of the write port. See Table 1 for bus size configuration.

INPUT

INPUT determines one of eight default offset values for the PAE and PAF flags, along with the method by which these

offset registers can be programmed, parallel or serial (see Table 2). After Master Reset, this pin enables writing to and reading from the offset registers. THIS PIN MUST BE HIGH AFTER MASTER RESET TO WRITE OR READ DATA TO/FROM THE FIFO MEMORY.

INPUT operation will reset the read pointer to this position.

INPUT Reset, the FIFO is configured for either FWFT or IDT Standard mode, Bus-Matching configurations,

Synchronous/Asynchronous operation of the read or write port, one of eight programmable flag default settings, serial or parallel programming of the offset settings, Big-Endian/Little-Endian format, zero latency timing mode, interspersed parity, and synchronous versus asynchronous programmable flag timing modes.

n. During a Master or Partial Reset the

INPUT OE input is the only input that provide High-Impedance control of the data outputs.

(1)

Output Width LVTTL This pin, along with IW and BM, selects the bus width of the read port. See Table 1 for bus size configuration.

INPUT

IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync 16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72



 72-BIT FIFO



COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

PIN DESCRIPTION (CONTINUED)

Symbol Name I/O TYPE Description

PAE Programmable HSTL-LVTTL PAE goes LOW if the number of words in the FIFO memory is less than offset n, which is stored in the

Almost-Empty Flag OUTPUT Empty Offset register. PAE goes HIGH if the number of words in the FIFO memory is greater than or equal

to offset n.

PAF Programmable HSTL-LVTTL PAF goes HIGH if the number of free locations in the FIFO memory is more than offset m, which is stored in

Almost-Full Flag OUTPUT the Full Offset register. PAF goes LOW if the number of free locations in the FIFO memory is less than or equal

to m.

(1)

PFM

PRS Partial Reset HSTL-LVTTL PRS initializes the read and write pointers to zero and sets the output register to all zeroes. During Partial Reset,

0–Q71 Data Outputs HSTL-LVTTL Data outputs for an 72-, 36- or 18-bit bus. When in 36- or 18-bit mode, any unused output pins should not

RCLK/ Read Clock/ HSTL-LVTTL If Synchronous operation of the read port has been selected, when enabled by REN, the rising edge of RCLK RD Read Strobe INPUT reads data from the FIFO memory and offsets from the programmable registers. If LD is LOW, the values loaded

RCS Read Chip Select HSTL-LVTTL RCS provides synchronous control of the read port and output impedance of Qn, synchronous to RCLK. During

REN Read Enable HSTL-LVTTL If Synchronous operation of the read port has been selected, REN enables RCLK for reading data from the

RHSTL

RT Retransmit HSTL-LVTTL RT asserted on the rising edge of RCLK initializes the READ pointer to zero, sets the EF flag to LOW (OR to

SCLK Serial Clock HSTL-LVTTL A rising edge on SCLK will clock the serial data present on the SI input into the offset registers providing that

SEN Serial Enable HSTL-LVTTL SEN enables serial loading of programmable flag offsets.

SHSTL System HSTL LVTTL All inputs not associated with the write or read port can be selected for HSTL operation via the SHSTL input.

TCK

TDI

TDO

TMS

Programmable LVTTL During Master Reset, a LOW on PFM will select Asynchronous Programmable flag timing mode. A HIGH on Flag Mode INPUT PFM will select Synchronous Programmable flag timing mode.

INPUT the existing mode (IDT or FWFT), programming method (serial or parallel), and programmable flag settings

are all retained.

OUTPUT be connected. Outputs are not 3.3V tolerant regardless of the state of OE and RCS.

into the offset registers is output on a rising edge of RCLK. If Asynchronous operation of the read port has been selected, a rising edge on RD reads data from the FIFO in an Asynchronous manner. REN should be tied LOW.

INPUT a Master Reset or Partial Reset the RCS input is don’t care, if OE is LOW the data outputs will be Low-Impedance

regardless of RCS.

INPUT FIFO memory and offset registers. If Asynchronous operation of the read port has been selected, the REN

input should be tied LOW.

(1)

Read Port HSTL LVTTL This pin is used to select HSTL or 2.5V LVTTL outputs for the FIFO. If HSTL or eHSTL outputs are Select INPUT required, this input must be tied HIGH. Otherwise it should be tied LOW.

INPUT HIGH in FWFT mode) and doesn’t disturb the write pointer, programming method, existing timing mode or

programmable flag settings. If a mark has been set via the MARK input pin, then the read pointer will jump to the ‘mark’ location.

INPUT SEN is enabled.

INPUT

Select INPUT

(2)

JTAG Clock HSTL-LVTTL Clock input for JTAG function. One of four terminals required by IEEE Standard 1149.1-1990. Test operations

INPUT of the device are synchronous to TCK. Data from TMS and TDI are sampled on the rising edge of TCK and

outputs change on the falling edge of TCK. If the JTAG function is not used this signal needs to be tied to GND.

(2)

JTAG Test Data HSTL-LVTTL One of four terminals required by IEEE Standard 1149.1-1990. During the JTAG boundary scan operation, Input INPUT test data serially loaded via the TDI on the rising edge of TCK to either the Instruction Register, ID Register

and Bypass Register. An internal pull-up resistor forces TDI HIGH if left unconnected.

(2)

JTAG Test Data HSTL-LVTTL One of four terminals required by IEEE Standard 1149.1-1990. During the JTAG boundary scan operation, Output OUTPUT test data serially loaded output via the TDO on the falling edge of TCK from either the Instruction Register, ID

Register and Bypass Register. This output is high impedance except when shifting, while in SHIFT-DR and SHIFT-IR controller states.

(2)

JTAG Mode HSTL-LVTTL TMS is a serial input pin. One of four terminals required by IEEE Standard 1149.1-1990. TMS directs the Select INPUT the device through its TAP controller states. An internal pull-up resistor forces TMS HIGH if left unconnected.

IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync 16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72



 72-BIT FIFO



COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

PIN DESCRIPTION (CONTINUED)

Symbol Name I/O TYPE Description

(2)

TRST

WEN Write Enable HSTL-LVTTL When Synchronous operation of the write port has been selected, WEN enables WCLK for writing data into

WCS Write Chip Select HSTL-LVTTL This pin disables the write port data inputs when the device write port is configured for HSTL mode. This

WCLK/ Write Clock/ HSTL-LVTTL If Synchronous operation of the write port has been selected, when enabled by WEN, the rising edge of WCLK W R Write Strobe INPUT writes data into the FIFO. If Asynchronous operation of the write port has been selected, WR writes data into

WHSTL

VCC +2.5v Supply I These are Vcc supply inputs and must be connected to the 2.5V supply rail. GND Ground Pin I These are Ground pins and must be connected to the GND rail. Vref Reference I This is a Voltage Reference input and must be connected to a voltage level determined from the table,

DDQ O/P Rail Voltage I This pin should be tied to the desired voltage rail for providing power to the output drivers.

JTAG Reset HSTL-LVTTL TRST is an asynchronous reset pin for the JTAG controller. The JTAG TAP controller does not automatically

INPUT reset upon power-up, thus it must be reset by either this signal or by setting TMS= HIGH for five TCK cycles.

If the TAP controller is not properly reset then the FIFO outputs will always be in high-impedance. If the JTAG function is used but the user does not want to use TRST, then TRST can be tied with MRS to ensure proper FIFO operation. If the JTAG function is not used then this signal needs to be tied to GND.

INPUT the FIFO memory and offset registers. If Asynchronous operation of the write port has been selected, the

WEN input should be tied LOW.

INPUT provides added power savings.

the FIFO on a rising edge in an Asynchronous manner, (WEN should be tied to its active state).

(1)

Write Port HSTL LVTTL This pin is used to select HSTL or 2.5V LVTTL inputs for the FIFO. If HSTL inputs are required, this input must Select INPUT be tied HIGH. Otherwise it should be tied LOW.

Voltage “Recommended DC Operating Conditions”. This provides the reference voltage when using HSTL class

inputs. If HSTL class inputs are not being used, this pin should be tied LOW.

NOTES:

1. Inputs should not change state after Master Reset.

2. These pins are for the JTAG port. Please refer to pages 29-31 and Figures 6-8.

IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync 16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72



 72-BIT FIFO



COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

ABSOLUTE MAXIMUM RATINGS

Symbol Rating Commercial Unit

TERM Terminal Voltage –0.5 to +3.6

with respect to GND

STG Storage Temperature –55 to +125 °C

OUT DC Output Current –50 to +50 mA

NOTES:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

2. Compliant with JEDEC JESD8-5. V

CC terminal only.

(2)

CAPACITANCE (TA = +25°C, f = 1.0MHz)

Symbol Parameter

(2,3)

Input VIN = 0V 10 Capacitance

(1,2)

OUT

Output VOUT = 0V 10 pF Capacitance

NOTES:

1. With output deselected, (OE ≥ V

2. Characterized values, not currently tested.

IN for Vref is 20pF.

3. C

(1)

Conditions Max. Unit

IH).

RECOMMENDED DC OPERATING CONDITIONS

Symbol Parameter Min. Typ. Max. Unit

CC Supply Voltage 2.375 2.5 2.625 V

GND Supply Voltage 0 0 0 V

IH Input High Voltage  LVTTL 1.7 — 3.45 V

 eHSTL V  HSTL V

IL Input Low Voltage  LVTTL -0.3 — 0.7 V

 eHSTL -0.3 — V  HSTL -0.3 — V

(1)

REF

Voltage Reference Input  eHSTL 0.8 0.9 1.0 V

 HSTL 0.68 0.75 0.9 V

A Operating Temperature Commercial 0 — 7 0 °C

A Operating Temperature Industrial -40 — 8 5 °C

NOTE:

1. V

REF is only required for HSTL or eHSTL inputs. VREF should be tied LOW for LVTTL operation.

2. Outputs are not 3.3V tolerant.

REF+0.2 — VDDQ+0.3 V REF+0.2 — VDDQ+0.3 V

REF-0.2 V REF-0.2 V

(3)

DC ELECTRICAL CHARACTERISTICS

(Commercial: VCC = 2.5V ± 0.125V, TA = 0°C to +70°C;Industrial: VCC = 2.5V ± 0.125V, TA = -40°C to +85°C)

Symbol Parameter Min. Max. Unit

LI Input Leakage Current –1 0 1 0 µA LO Output Leakage Current –1 0 1 0 µA

(5)

OL Output Logic “0” Voltage, IOL = 8 mA @V DDQ = 2.5V ± 0.125V (LVTTL) — 0.4V V

(1,2)

CC1

(1)

CC2

NOTES:

1. Both WCLK and RCLK toggling at 20MHz. Data inputs toggling at 10MHz. WCS = HIGH, REN or RCS = HIGH.

2. Typical I

3. Typical I

4. Total Power consumed: PT = (V

5. Outputs are not 3.3V tolerant.

Output Logic “1” Voltage, IOH = –8 mA @VDDQ = 2.5V ± 0.125V (LVTTL) VDDQ -0.4 — V

OH = –8 mA @VDDQ = 1.8V ± 0.1V (eHSTL) VDDQ -0.4 — V

OH = –8 mA @VDDQ = 1.5V ± 0.1V (HSTL) VDDQ -0.4 — V

OL = 8 mA @VDDQ = 1.8V ± 0.1V (eHSTL) — 0.4V V

OL = 8 mA @VDDQ = 1.5V ± 0.1V (HSTL) — 0.4V V

Active VCC Current (VCC = 2.5V) I/O = LVTTL — 8 0 mA

I/O = HSTL — 130 m A I/O = eHSTL — 130 mA

Standby VCC Current (VCC = 2.5V) I/O = LVTTL — 20 mA

I/O = HSTL — 90 mA I/O = eHSTL — 90 mA

CC1 calculation: for LVTTL I/O ICC1 (mA) = 2.24mA x fs, fs = WCLK frequency = RCLK frequency (in MHz) DDQ calculation: With Data Outputs in High-Impedance: IDDQ (mA) = 0.15mA x fs

for HSTL or eHSTL I/O I With Data Outputs in Low-Impedance: I

fs = WCLK frequency = RCLK frequency (in MHz), V

A = 25°C, CL = capacitive load (pf).

CC x ICC) + VDDQ x IDDQ).

CC1 (mA) = 55mA + (2.24mA x fs), fs = WCLK frequency = RCLK frequency (in MHz)

DDQ (mA) = (CL x VDDQ x fs x N)/2000

DDQ = 2.5V for LVTTL; 1.5V for HSTL; 1.8V for eHSTL, N = Number of outputs switching.

IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync 16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72



 72-BIT FIFO



COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

AC ELECTRICAL CHARACTERISTICS

(1)

— SYNCHRONOUS TIMING

(Commercial: VCC = 2.5V ± 5%, TA = 0°C to +70°C;Industrial: VCC = 2.5V ± 5%, TA = -40°C to +85°C)

Commercial Com’l & Ind’l Commercial

IDT72T7285L4-4 IDT72T7285L5 IDT72T7285L6-7 IDT72T7285L10

IDT72T7295L4-4 IDT72T7295L5 IDT72T7295L6-7 IDT72T7295L10 IDT72T72105L4-4 IDT72T72105L5 IDT72T72105L6-7 IDT72T72105L10 IDT72T72115L4-4 IDT72T72115L5 IDT72T72115L6-7 IDT72T72115L10

Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Unit

fC Clock Cycle Frequency (Synchronous) — 22 5 — 200 — 1 50 100 MHz tA Data Access Time 0.6 3.4 0.6 3.6 0.6 3.8 0.6 4.5 ns tCLK Clock Cycle Time 4.44 — 5 — 6.7 — 10 — ns tCLKH Clock High Time 2. 0 — 2.3 — 2. 8 — 4. 5 — ns tCLKL Clock Low Time 2.0 — 2.3 — 2.8 — 4.5 — ns tDS Data Setup Time 1.2 — 1.5 — 2.0 — 3.0 — ns tDH Data Hold Time 0.5 — 0.5 — 0.5 — 0. 5 — ns tENS Enable Setup Time 1.2 — 1.5 — 2.0 — 3.0 — ns tENH Enable Hold Time 0.5 — 0.5 — 0.5 — 0.5 — ns tLDS Load Setup Time 1.2 — 1.5 — 2.0 — 3.0 — ns tLDH Load Hold Time 0 .5 — 0.5 — 0.5 — 0.5 — ns tWCSS WCS setup time 1. 2 — 1.5 — 2.0 — 3.0 — ns tWCSH WCS hold time 0.5 — 0.5 — 0. 5 — 0.5 — ns fS Clock Cycle Frequency (SCLK) — 10 — 10 — 10 — 10 M Hz tSCLK Serial Clock Cycle 100 — 100 — 100 — 100 — ns tSCKH Serial Clock High 4 5 — 45 — 45 — 4 5 — ns tSCKL Serial Clock Low 45 — 45 — 45 — 45 — ns tSDS Serial Data In Setup 1 5 — 15 — 15 — 15 — ns tSDH Serial Data In Hold 5 — 5 — 5 — 5 — ns tSENS Serial Enable Setup 5 — 5 — 5 — 5 — ns tSENH Serial Enable Hold 5 — 5 — 5 — 5 — ns tRS Reset Pulse Width tRSS Reset Setup Time 15 — 15 — 15 — 15 — ns tHRSS HSTL Reset Setup Time 4 — 4 — 4 — 4 — µs tRSR Reset Recovery Time 1 0 — 10 — 1 0 — 1 0 — ns tRSF Reset to Flag and Output Time — 10 — 12 — 15 — 15 ns tWFF Write Clock to FF or IR — 3.4 — 3.6 — 3.8 — 4.5 ns tREF Read Clock to EF or OR — 3.4 — 3.6 — 3.8 — 4.5 ns tPAFS Write Clock to Synchronous Programmable Almost-Full Flag — 3.4 — 3.6 — 3.8 — 4.5 ns tPAES Read Clock to Synchronous Programmable Almost-Empty Flag — 3.4 — 3.6 — 3.8 — 4.5 ns tERCLK RCLK to Echo RCLK output — 3.8 — 4 — 4. 3 — 5 ns tCLKEN RCLK to Echo REN output — 3.4 — 3.6 — 3.8 — 4.5 ns tRCSLZ RCLK to Active from High-Z tRCSHZ RCLK to High-Z tSKEW1 Skew time between RCLK and WCLK for EF/OR and FF/IR 3.5— 4 —5 —7 —ns

SKEW2 Skew time between RCLK and WCLK for PAE and PAF 4—5—6 —8—ns

NOTES:

1. All AC timings apply to both Standard IDT mode and First Word Fall Through mode.

2. Pulse widths less than minimum values are not allowed.

3. Values guaranteed by design, not currently tested.

4. Industrial temperature range product for the 5ns speed grade is available as a standard device. All other speed grades are available by special order.

(2)

(3)

30 — 30 — 30 — 30 — ns

— 3.4 — 3.6 — 3.8 — 4.5 ns — 3.4 — 3.6 — 3.8 — 4.5 ns

IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync 16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72



 72-BIT FIFO



COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

AC ELECTRICAL CHARACTERISTICS — ASYNCHRONOUS TIMING

(Commercial: VCC = 2.5V ± 5%, TA = 0°C to +70°C;Industrial: VCC = 2.5V ± 5%, TA = -40°C to +85°C)

Commercial Com’l & Ind’l Commercial

IDT72T7285L4-4 IDT72T7285L5 IDT72T7285L6-7 IDT72T7285L10

IDT72T7295L4-4 IDT72T7295L5 IDT72T7295L6-7 IDT72T7295L10 IDT72T72105L4-4 IDT72T72105L5 IDT72T72105L6-7 IDT72T72105L10 IDT72T72115L4-4 IDT72T72115L5 IDT72T72115L6-7 IDT72T72115L10

Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Unit

fA Cycle Frequency (Asynchronous) — 10 0 — 83 — 66 — 50 MHz tAA Data Access Time 0.6 8 0.6 10 0.6 1 2 0.6 14 ns tCYC Cycle Time 1 0 — 12 — 1 5 — 2 0 — ns tCYH Cycle HIGH Time 4.5 — 5 — 7 — 8 — ns tCYL Cycle LOW Time 4.5 — 5 — 7 — 8 — ns tRPE Read Pulse after EF HIGH 8 — 10 — 12 — 1 4 — ns tFFA Clock to Asynchronous FF —8—10—12—14ns tEFA Clock to Asynchronous EF —8—10—12—14ns tPAFA Clock to Asynchronous Programmable Almost-Full Flag — 8 — 1 0 — 12 — 14 ns tPAEA Clock to Asynchronous Programmable Almost-Empty Flag — 8 — 10 — 1 2 — 14 ns tOLZ Output Enable to Output in Low Z tOE Output Enable to Output Valid — 3.4 — 3.6 — 3.8 — 4.5 ns tOHZ Output Enable to Output in High Z

HF Clock to HF —8—10—12—14ns

(1)

0—0—0— 0—ns

— 3.4 — 3.6 — 3.8 — 4.5 ns

NOTES:

1. Values guaranteed by design, not currently tested.

2. Industrial temperature range product for the 5ns speed grade is available as a standard device. All other speed grades are available by special order.

IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync

5994 drw04a

20 30 50 80 100 200

Capacitance (pF)

(Typical, ns)

16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72



 72-BIT FIFO



COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

HSTL

1.5V AC TEST CONDITIONS

Input Pulse Levels 0.25 to 1.25V Input Rise/Fall Times 0.4ns Input Timing Reference Levels 0.75 Output Reference Levels V

NOTE:

DDQ = 1.5V±.

1. V

DDQ/2

EXTENDED HSTL

1.8V AC TEST CONDITIONS

Input Pulse Levels 0.4 to 1.4V Input Rise/Fall Times 0.4ns Input Timing Reference Levels 0.9 Output Reference Levels V

DDQ/2

AC TEST LOADS

I/O

Figure 2a. AC Test Load

Z0 = 50

DDQ

Ω

5994 drw04

NOTE:

DDQ = 1.8V±.

1. V

2.5V LVTTL

2.5V AC TEST CONDITIONS

Input Pulse Levels GND to 2.5V Input Rise/Fall Times 1ns Input Timing Reference Levels V Output Reference Levels V

NOTE:

1. For LVTTL V

CC = VDDQ.

DDQ/2

Figure 2b. Lumped Capacitive Load, Typical Derating

CC/2

IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync



 72-BIT FIFO



16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72

OUTPUT ENABLE & DISABLE TIMING

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

NOTES:

1. REN is HIGH.

2. RCS is LOW.

Output

Normally

LOW

Output

Normally

HIGH

Output

Enable

OE & tOLZ

100mV

Output

Disable

100mV

OHZ

100mV

5994 drw04b

VIL

VOH

READ CHIP SELECT ENABLE & DISABLE TIMING

100mV

ENH

RCSLZ

NOTES:

1. REN is HIGH.

2. OE is LOW.

Output

Normally

LOW

Output

Normally

HIGH

RCS

RCLK

ENS

100mV

RCSHZ

5994 drw04c

VIL

VOH

IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync 16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72



 72-BIT FIFO



COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

FUNCTIONAL DESCRIPTION

TIMING MODES: IDT STANDARD vs FIRST WORD FALL THROUGH (FWFT) MODE

The IDT72T7285/72T7295/72T72105/72T72115 support two different timing modes of operation: IDT Standard mode or First Word Fall Through (FWFT) mode. The selection of which mode will operate is determined during Master Reset, by the state of the FWFT/SI input.

If, at the time of Master Reset, FWFT/SI is LOW, then IDT Standard mode will be selected. This mode uses the Empty Flag (EF) to indicate whether or not there are any words present in the FIFO. It also uses the Full Flag function (FF) to indicate whether or not the FIFO has any free space for writing. In IDT Standard mode, every word read from the FIFO, including the first, must be requested using the Read Enable (REN) and RCLK.

If, at the time of Master Reset, FWFT/SI is HIGH, then FWFT mode will be selected. This mode uses Output Ready (OR) to indicate whether or not there is valid data at the data outputs (Qn). It also uses Input Ready (IR) to indicate whether or not the FIFO has any free space for writing. In the FWFT mode, the first word written to an empty FIFO goes directly to Qn after three RCLK rising edges, REN = LOW is not necessary. Subsequent words must be accessed using the Read Enable (REN) and RCLK.

Various signals, both input and output signals operate differently depending

on which timing mode is in effect.

IDT STANDARD MODE

In this mode, the status flags, FF, PAF, HF, PAE, and EF operate in the manner outlined in Table 3. To write data into to the FIFO, Write Enable (WEN) must be LOW. Data presented to the DATA IN lines will be clocked into the FIFO on subsequent transitions of the Write Clock (WCLK). After the first write is performed, the Empty Flag (EF) will go HIGH. Subsequent writes will continue to fill up the FIFO. The Programmable Almost-Empty flag (PAE) will go HIGH after n + 1 words have been loaded into the FIFO, where n is the empty offset value. The default setting for these values are stated in the footnote of Table 2. This parameter is also user programmable. See section on Programmable Flag Offset Loading.

If one continued to write data into the FIFO, and we assumed no read operations were taking place, the Half-Full flag (HF) would toggle to LOW once the 8,193rd word for IDT72T7285, 16,385th word for IDT72T7295, 32,769th word for IDT72T72105 and 65,537th word for IDT72T72115, respectively was written into the FIFO. Continuing to write data into the FIFO will cause the Programmable Almost-Full flag (PAF) to go LOW. Again, if no reads are performed, the PAF will go LOW after (16,384-m) writes for the IDT72T7285, (32,768-m) writes for the IDT72T7295, (65,536-m) writes for the IDT72T72105 and (131,072-m) writes for the IDT72T72115. The offset “m” is the full offset value. The default setting for these values are stated in the footnote of Table 2. This parameter is also user programmable. See section on Programmable Flag Offset Loading.

When the FIFO is full, the Full Flag (FF) will go LOW, inhibiting further write operations. If no reads are performed after a reset, FF will go LOW after D writes to the FIFO. D = 16,384 writes for the IDT72T7285, 32,768 writes for the IDT72T7295, 65,536 writes for the IDT72T72105 and 131,072 writes for the IDT72T72115, respectively.

If the FIFO is full, the first read operation will cause FF to go HIGH. Subsequent read operations will cause PAF and HF to go HIGH at the conditions described in Table 3. If further read operations occur, without write operations, PAE will go LOW when there are n words in the FIFO, where n is the empty offset value. Continuing read operations will cause the FIFO to become empty. When the last word has been read from the FIFO, the EF will go LOW inhibiting further read operations. REN is ignored when the FIFO is empty.

When configured in IDT Standard mode, the EF and FF outputs are double register-buffered outputs.

Relevant timing diagrams for IDT Standard mode can be found in Figure 11, 12, 13 and 18.

FIRST WORD FALL THROUGH MODE (FWFT)

In this mode, the status flags, IR, PAF, HF, PAE, and OR operate in the manner outlined in Table 4. To write data into to the FIFO, WEN must be LOW. Data presented to the DATA IN lines will be clocked into the FIFO on subsequent transitions of WCLK. After the first write is performed, the Output Ready (OR) flag will go LOW. Subsequent writes will continue to fill up the FIFO. PAE will go HIGH after n + 2 words have been loaded into the FIFO, where n is the empty offset value. The default setting for these values are stated in the footnote of Table 2. This parameter is also user programmable. See section on Programmable Flag Offset Loading.

If one continued to write data into the FIFO, and we assumed no read operations were taking place, the HF would toggle to LOW once the 8,194th word for the IDT72T7285, 16,386th word for the IDT72T7295, 32,770th word for the IDT72T72105 and 65,538th word for the IDT72T72115, respectively was written into the FIFO. Continuing to write data into the FIFO will cause the PAF to go LOW. Again, if no reads are performed, the PAF will go LOW after (16,385-m) writes for the IDT72T7285, (32,769-m) writes for the IDT72T7295, (65,537-m) writes for the IDT72T72105 and (131,073-m) writes for the IDT72T72115, where m is the full offset value. The default setting for these values are stated in the footnote of Table 2.

When the FIFO is full, the Input Ready (IR) flag will go HIGH, inhibiting further write operations. If no reads are performed after a reset, IR will go HIGH after D writes to the FIFO. D = 16,385 writes for the IDT72T7285, 32,769 writes for the IDT72T7295, 65,537 writes for the IDT72T72105 and 131,073 writes for the IDT72T72115, respectively. Note that the additional word in FWFT mode is due to the capacity of the memory plus output register.

If the FIFO is full, the first read operation will cause the IR flag to go LOW. Subsequent read operations will cause the PAF and HF to go HIGH at the conditions described in Table 4. If further read operations occur, without write operations, the PAE will go LOW when there are n + 1 words in the FIFO, where n is the empty offset value. Continuing read operations will cause the FIFO to become empty. When the last word has been read from the FIFO, OR will go HIGH inhibiting further read operations. REN is ignored when the FIFO is empty.

When configured in FWFT mode, the OR flag output is triple registerbuffered, and the IR flag output is double register-buffered.

Relevant timing diagrams for FWFT mode can be found in Figure 14, 15, 16 and 19.

IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync 16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72



 72-BIT FIFO



COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

TABLE 2 — DEFAULT PROGRAMMABLE FLAG OFFSETS

IDT72T7285,72T7295,72T72105,72T72115

*LD FSEL1 FSEL0 Offsets n,m

H L L 1,023

LH L511 L L H 255 L L L 127

LHH63 HH L31 HLH15 HH H7

*LD FSEL1 FSEL0 Program Mode

H X X Serial

L X X Parallel

*THIS PIN MUST BE HIGH AFTER MASTER RESET T O WRITE OR READ DATA TO/FROM THE FIFO MEMORY.

NOTES:

1. n = empty offset for PAE.

2. m = full offset for PAF.

3. As well as selecting serial programming mode, one of the default values will also be loaded depending on the state of FSEL0 & FSEL1.

4. As well as selecting parallel programming mode, one of the default values will also be loaded depending on the state of FSEL0 & FSEL1.

(3)

(4)

PROGRAMMING FLAG OFFSETS

Full and Empty Flag offset values are user programmable. The IDT72T7285/ 72T7295/72T72105/72T72115 have internal registers for these offsets. There are eight default offset values selectable during Master Reset. These offset values are shown in Table 2. Offset values can also be programmed into the FIFO in one of two ways; serial or parallel loading method. The selection of the loading method is done using the LD (Load) pin. During Master Reset, the state of the LD input determines whether serial or parallel flag offset programming is enabled. A HIGH on LD during Master Reset selects serial loading of offset values. A LOW on LD during Master Reset selects parallel loading of offset values.

In addition to loading offset values into the FIFO, it is also possible to read the current offset values. Offset values can be read via the parallel output port Q0-Qn, regardless of the programming mode selected (serial or parallel). It is not possible to read the offset values in serial fashion.

Figure 3, Programmable Flag Offset Programming Sequence, summaries the control pins and sequence for both serial and parallel programming modes. For a more detailed description, see discussion that follows.

The offset registers may be programmed (and reprogrammed) any time after Master Reset, regardless of whether serial or parallel programming has been selected. Valid programming ranges are from 0 to D-1.

SYNCHRONOUS vs ASYNCHRONOUS PROGRAMMABLE FLAG TIMING SELECTION

The IDT72T7285/72T7295/72T72105/72T72115 can be configured during the Master Reset cycle with either synchronous or asynchronous timing for PAF and PAE flags by use of the PFM pin.

If synchronous PAF/PAE configuration is selected (PFM, HIGH during MRS), the PAF is asserted and updated on the rising edge of WCLK only and not RCLK. Similarly, PAE is asserted and updated on the rising edge of RCLK only and not WCLK. For detail timing diagrams, see Figure 23 for synchronous PAF timing and Figure 24 for synchronous PAE timing.

If asynchronous PAF/PAE configuration is selected (PFM, LOW during

MRS), the PAF is asserted LOW on the LOW-to-HIGH transition of WCLK and PAF is reset to HIGH on the LOW-to-HIGH transition of RCLK. Similarly, PAE

is asserted LOW on the LOW-to-HIGH transition of RCLK. PAE is reset to HIGH on the LOW-to-HIGH transition of WCLK. For detail timing diagrams, see Figure 25 for asynchronous PAF timing and Figure 26 for asynchronous PAE timing.

IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync



 72-BIT FIFO



16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72

TABLE 3  STATUS FLAGS FOR IDT STANDARD MODE

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

IDT72T7285 IDT72T7295

(1)

1 to n

(n+1) to 16,384

32,768

Number of Words in FIFO

(1)

1 to n

(n+1) to 8,192

8,193 to (16,384-(m+1))

(16,384-m) to 16,383

16,384

16,385 to (32,768-(m+1))

(32,768-m) to 32,767

NOTE:

1. See table 2 for values for n, m.

TABLE 4  STATUS FLAGS FOR FWFT MODE

IDT72T7285 IDT72T7295

00 0

1 to n+1

(n+2) to 16,385

32,769 65,537 131,073

Number of Words in FIFO

1 to n+1

(n+2) to 8,193

8,194 to (16,385-(m+1))

(16,385-m) to 16,384

16,385

NOTE:

1. See table 2 for values for n, m.

16,386 to (32,769-(m+1)) 32,770 to (65,537-(m+1))

(32,769-m) to 32,768

IDT72T72105

(1)

1 to n

(n+1) to 32,768

32,769 to (65,536-(m+1))

(65,536-m) to 65,535

65,536

IDT72T72115

(1)

1 to n

(n+1) to 65,536

65,537 to (131,072-(m+1))

(131,072-m) to 131,071

131,072

IDT72T72105 IDT72T72115

1 to n+1

(n+2) to 32,769 (n+2) to 65,537

(65,537-m) to 65,536 (131,073-m) to 131,072

1 to n+1

65,538 to (131,073-(m+1))

FF PAF

HHL HH

IR PAF

LHHHL

LHLHL

PAE EF

HL L

LHH

HL H

LH L

PAE OR

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IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync 16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72

WEN

REN

SEN

WCLK RCLK



 72-BIT FIFO



SCLK

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

IDT72T7285 IDT72T7295 IDT72T72105 IDT72T72115

Parallel write to registers: Empty Offset (LSB) Empty Offset (MSB) Full Offset (LSB) Full Offset (MSB)

Parallel read from registers: Empty Offset (LSB) Empty Offset (MSB) Full Offset (LSB) Full Offset (MSB)

Serial shift into registers:

28 bits for the IDT72T7285 30 bits for the IDT72T7295 32 bits for the IDT72T72105 34 bits for the IDT72T72115

1 bit for each rising SCLK edge

Starting with Empty Offset (LSB) Ending with Full Offset (MSB)

No Operation

Write Memory

Read Memory

NOTES:

1. The programming method can only be selected at Master Reset.

2. Parallel reading of the offset registers is always permitted regardless of which programming method has been selected.

3. The programming sequence applies to both IDT Standard and FWFT modes.

Figure 3. Programmable Flag Offset Programming Sequence

No Operation

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D/Q71 D/Q19

D/Q35 D/Q19

1st Parallel Offset Write/Read Cycle

D/Q17

D/Q8

EMPTY OFFSET REGISTER (PAE)

1415

910111213

2nd Parallel Offset Write/Read Cycle

D/Q17

D/Q8

FULL OFFSET REGISTER (PAF)

1415

910111213

x72 Bus Width

1st Parallel Offset Write/Read Cycle

D/Q17

D/Q8

EMPTY OFFSET REGISTER (PAE)

910111213

1415

2nd Parallel Offset Write/Read Cycle

D/Q17

D/Q8

FULL OFFSET REGISTER (PAF)

910111213

1415

x36 Bus Width

# of Bits Used

D/Q0

Non-Interspersed

56781213

234

234 234

D/Q0

1 1

D/Q0

1 1

D/Q0

Parity

Interspersed Parity

Non-Interspersed Parity

Interspersed Parity

Non-Interspersed Parity

Interspersed Parity

Non-Interspersed Parity

Interspersed Parity

1st Parallel Offset Write/Read Cycle

D/Q17

1415

Data Inputs/Outputs

EMPTY OFFSET (LSB) REGISTER (PAE)

56789101112131415

1213

D/Q8

5678

# of Bits Used

D/Q0D/Q16

1234

Non-Interspersed Parity

Interspersed Parity

2nd Parallel Offset Write/Read Cycle

D/Q17

D/Q16

Data Inputs/Outputs

D/Q0

EMPTY OFFSET (MSB) REGISTER (PAE)

3rd Parallel Offset Write/Read Cycle

D/Q17

D/Q16

Data Inputs/Outputs

D/Q0

FULL OFFSET (LSB) REGISTER (PAF)

1112

1011121314

D/Q8

16 15

1415

4th Parallel Offset Write/Read Cycle

D/Q17

D/Q16

Data Inputs/Outputs

FULL OFFSET (MSB) REGISTER (PAF)

12345678910 1

2345678

# of Bits Used:

D/Q0

14 bits for the IDT72T7285 15 bits for the IDT72T7295 16 bits for the IDT72T72105 17 bits for the IDT72T72115 Note: All unused input bits are don’t care.

x18 Bus Width

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NOTE:

1. Consecutive reads of the offset registers is not permitted. The read operation must be disabled for a minimum of one RCLK cycle in between offset register accesses. (Please refer to Figure 22, Parallel Read of Programmable Flag Registers (IDT Standard and FWFT Modes) for more details).

Figure 3. Programmable Flag Offset Programming Sequence (Continued)

IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync 16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72

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 72-BIT FIFO

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SERIAL PROGRAMMING MODE

If Serial Programming mode has been selected, as described above, then

programming of PAE and PAF values can be achieved by using a combination of the LD, SEN, SCLK and SI input pins. Programming PAE and PAF proceeds as follows: when LD and SEN are set LOW, data on the SI input are written, one bit for each SCLK rising edge, starting with the Empty Offset LSB and ending with the Full Offset MSB. A total of 28 bits for the IDT72T7285, 30 bits for the IDT72T7295, 32 bits for the IDT72T72105 and 34 bits for the IDT72T72115. See Figure 20, Serial Loading of Programmable Flag Registers, for the timing diagram for this mode.

Using the serial method, individual registers cannot be programmed selec-

tively. PAE and PAF can show a valid status only after the complete set of bits (for all offset registers) has been entered. The registers can be reprogrammed as long as the complete set of new offset bits is entered. When LD is LOW and SEN is HIGH, no serial write to the registers can occur.

Write operations to the FIFO are allowed before and during the serial

programming sequence. In this case, the programming of all offset bits does not have to occur at once. A select number of bits can be written to the SI input and then, by bringing LD and SEN HIGH, data can be written to FIFO memory via Dn by toggling WEN. When WEN is brought HIGH with LD and SEN restored to a LOW, the next offset bit in sequence is written to the registers via SI. If an interruption of serial programming is desired, it is sufficient either to set LD LOW and deactivate SEN or to set SEN LOW and deactivate LD. Once LD and SEN are both restored to a LOW level, serial offset programming continues.

From the time serial programming has begun, neither programmable flag will

be valid until the full set of bits required to fill all the offset registers has been written. Measuring from the rising SCLK edge that achieves the above criteria; PAF will be valid after three more rising WCLK edges plus tPAF, PAE will be valid after the next three rising RCLK edges plus tPAE.

It is only possible to read the flag offset values via the parallel output port Qn.

PARALLEL MODE

If Parallel Programming mode has been selected, as described above, then

programming of PAE and PAF values can be achieved by using a combination of the LD, WCLK , WEN and Dn input pins. Programming PAE and PAF proceeds as follows: LD and WEN must be set LOW. For x72, x36 or x18 data on the inputs Dn are written into the Empty Offset Register on the first LOW-toHIGH transition of WCLK. Upon the second LOW-to-HIGH transition of WCLK, data are written into the Full Offset Register. The third transition of WCLK writes, once again, to the Empty Offset Register. See Figure 3, Programmable Flag

Offset Programming Sequence. See Figure 21, Parallel Loading of Programmable Flag Registers, for the timing diagram for this mode.

The act of writing offsets in parallel employs a dedicated write offset register

pointer. The act of reading offsets employs a dedicated read offset register pointer. The two pointers operate independently; however, a read and a write should not be performed simultaneously to the offset registers. A Master Reset initializes both pointers to the Empty Offset (LSB) register. A Partial Reset has no effect on the position of these pointers.

Write operations to the FIFO are allowed before and during the parallel

programming sequence. In this case, the programming of all offset registers does not have to occur at one time. One, two or more offset registers can be written and then by bringing LD HIGH, write operations can be redirected to the FIFO memory. When LD is set LOW again, and WEN is LOW, the next offset register in sequence is written to. As an alternative to holding WEN LOW and toggling LD, parallel programming can also be interrupted by setting LD LOW and toggling WEN.

Note that the status of a programmable flag (PAE or PAF) output is invalid

during the programming process. From the time parallel programming has

begun, a programmable flag output will not be valid until the appropriate offset word has been written to the register(s) pertaining to that flag. Measuring from the rising WCLK edge that achieves the above criteria; PAF will be valid after two more rising WCLK edges plus t

PAF, PAE will be valid after the next two rising

RCLK edges plus tPAE plus tSKEW2.

The act of reading the offset registers employs a dedicated read offset register

pointer. The contents of the offset registers can be read on the Q

0-Qn pins when

LD is set LOW and REN is set LOW. It is important to note that consecutive reads of the offset registers is not permitted. The read operation must be disabled for a minimum of one RCLK cycle in between offset register accesses. For x72, x36 and x18 output bus width, 2 read cycles are required to obtain the values of the offset registers. Starting with the Empty Offset Registers LSB and finishing with the Full Offset Registers MSB. See Figure 3, Programmable Flag Offset

Programming Sequence. See Figure 22, Parallel Read of Programmable Flag Registers, for the timing diagram for this mode.

It is permissible to interrupt the offset register read sequence with reads or writes to the FIFO. The interruption is accomplished by deasserting REN, LD, or both together. When REN and LD are restored to a LOW level, reading of the offset registers continues where it left off. It should be noted, and care should be taken from the fact that when a parallel read of the flag offsets is performed, the data word that was present on the output lines Qn will be overwritten.

Parallel reading of the offset registers is always permitted regardless of which timing mode (IDT Standard or FWFT modes) has been selected.

RETRANSMIT FROM MARK OPERATION

The Retransmit from Mark feature allows FIFO data to be read repeatedly starting at a user-selected position. The FIFO is first put into retransmit mode that will ‘mark’ a beginning word and also set a pointer that will prevent ongoing FIFO write operations from over-writing retransmit data. The retransmit data can be read repeatedly any number of times from the ‘marked’ position. The FIFO can be taken out of retransmit mode at any time to allow normal device operation. The ‘mark’ position can be selected any number of times, each selection overwriting the previous mark location. Retransmit operation is available in both IDT standard and FWFT modes.

During IDT standard mode the FIFO is put into retransmit mode by a Lowto-High transition on RCLK when the ‘MARK’ input is HIGH and EF is HIGH. The rising RCLK edge ‘marks’ the data present in the FIFO output register as the first retransmit data. The FIFO remains in retransmit mode until a rising edge on RCLK occurs while MARK is LOW.

Once a ‘marked’ location has been set (and the device is still in retransmit mode, MARK is HIGH), a retransmit can be initiated by a rising edge on RCLK while the retransmit input (RT) is LOW. REN must be HIGH (reads disabled) before bringing RT LOW. The device indicates the start of retransmit setup by setting EF LOW, also preventing reads. When EF goes HIGH, retransmit setup is complete and read operations may begin starting with the first data at the MARK location. Since IDT standard mode is selected, every word read including the first ‘marked’ word following a retransmit setup requires a LOW on REN (read enabled).

Note, write operations may continue as normal during all retransmit functions, however write operations to the ‘marked’ location will be prevented. See Figure 18, Retransmit from Mark (IDT standard mode), for the relevant timing diagram.

During FWFT mode the FIFO is put into retransmit mode by a rising RCLK edge when the ‘MARK’ input is HIGH and OR is LOW. The rising RCLK edge ‘marks’ the data present in the FIFO output register as the first retransmit data. The FIFO remains in retransmit mode until a rising RCLK edge occurs while MARK is LOW.

IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync 16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72



 72-BIT FIFO



COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

Once a marked location has been set (and the device is still in retransmit mode, MARK is HIGH), a retransmit can be initiated by a rising RCLK edge while the retransmit input (RT) is LOW. REN must be HIGH (reads disabled) before bringing RT LOW. The device indicates the start of retransmit setup by setting

and read pointer when the MARK is asserted. (32 bytes = 16 word = 8 long words). Also, once the MARK is set, the write pointer will not increment past the “marked” location until the MARK is deasserted. This prevents “overwriting” of retransmit data.

OR HIGH.

When OR goes LOW, retransmit setup is complete and on the next rising RCLK edge after retransmit setup is complete, (RT goes HIGH), the contents of the first retransmit location are loaded onto the output register. Since FWFT mode is selected, the first word appears on the outputs regardless of REN, a LOW on REN is not required for the first word. Reading all subsequent words requires a LOW on REN to enable the rising RCLK edge. See Figure 19, Retransmit from Mark timing (FWFT mode), for the relevant timing diagram.

Note, there must be a minimum of 32 bytes of data between the write pointer

HSTL/LVTTL I/O

Both the write port and read port are user selectable between HSTL or LVTTL I/O, via two select pins, WHSTL and RHSTL respectively. All other control pins are selectable via SHSTL, see Table 5 for details of groupings.

Note, that when the write port is selected for HSTL mode, the user can reduce the power consumption (in stand-by mode by utilizing the WCS input).

All “Static Pins” must be tied to V

CC or GND. These pins are LVTTL only,

and are purely device configuration pins.

TABLE 5 — I/O CONFIGURATION

WHSTL SELECT RHSTL SELECT SHSTL SELECT STATIC PINS

WHSTL: HIGH = HSTL RHSTL: HIGH = HSTL SHSTL: HIGH = HSTL LVTTL ONL Y

LOW = LVTTL LOW = L VTTL LOW = LVTTL

Dn (I/P) RCLK/RD (I/P) EF/OR (O/P) SCLK (I/P) PRS (I/P) IW (I/P) OW (I/P) WCLK/WR (I/P) RCS (I/P) PAF (O/P) LD (I/P) TRST (I/P) BM (I/P) ASYW (I/P)

WEN (I/P) MARK (I/P) EREN (O/P) MRS (I/P) TDI (I/P) ASYR (I/P) BE (I/P) WCS (I/P) REN (I/P) PAE (O/P) TCK (I/P) IP (I/P) FSEL0 (I/P)

OE (I/P) FF/IR (O/P) TMS (I/P) FSEL1 (I/P) PFM (I/P) RT (I/P) HF (O/P) SEN (I/P) SHSTL (I/P) WHSTL (I/P)

Qn (O/P) ERCLK (O/P) FWFT/SI (I/P) RHSTL (I/P)

TDO (O/P)

IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync 16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72



 72-BIT FIFO



COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

SIGNAL DESCRIPTION

INPUTS:

DATA IN (D0 - Dn)

Data inputs for 72-bit wide data (D0 - D71), data inputs for 36-bit wide data

(D0 - D35) or data inputs for 18-bit wide data (D0 - D17).

CONTROLS:

MASTER RESET ( MRS )

A Master Reset is accomplished whenever the MRS input is taken to a LOW state. This operation sets the internal read and write pointers to the first location of the RAM array. PAE will go LOW, PAF will go HIGH, and HF will go HIGH.

If FWFT/SI is LOW during Master Reset then the IDT Standard mode, along with EF and FF are selected. EF will go LOW and FF will go HIGH. If FWFT/SI is HIGH, then the First Word Fall Through mode (FWFT), along with IR and OR, are selected. OR will go HIGH and IR will go LOW.

All control settings such as OW, IW, BM, BE, RM, PFM and IP are defined during the Master Reset cycle.

During a Master Reset, the output register is initialized to all zeroes. A Master Reset is required after power up, before a write operation can take place. MRS is asynchronous.

See Figure 9, Master Reset Timing, for the relevant timing diagram.

PARTIAL RESET (PRS)

A Partial Reset is accomplished whenever the PRS input is taken to a LOW state. As in the case of the Master Reset, the internal read and write pointers are set to the first location of the RAM array, PAE goes LOW, PAF goes HIGH, and HF goes HIGH.

Whichever mode is active at the time of Partial Reset, IDT Standard mode or First Word Fall Through, that mode will remain selected. If the IDT Standard mode is active, then FF will go HIGH and EF will go LOW. If the First Word Fall Through mode is active, then OR will go HIGH, and IR will go LOW.

Following Partial Reset, all values held in the offset registers remain unchanged. The programming method (parallel or serial) currently active at the time of Partial Reset is also retained. The output register is initialized to all zeroes. PRS is asynchronous.

A Partial Reset is useful for resetting the device during the course of operation, when reprogramming programmable flag offset settings may not be convenient.

See Figure 10, Partial Reset Timing, for the relevant timing diagram.

Asynchronous operation of the read port will be selected. During Asynchronous operation of the read port the RCLK input becomes RD input, this is the Asynchronous read strobe input. A rising edge on RD will read data from the FIFO via the output register and Qn port. (REN must be tied LOW during Asynchronous operation of the read port).

The OE input provides three-state control of the Qn output bus, in an asynchronous manner. (RCS, provides three-state control of the read port in Synchronous mode).

When the read port is configured for Asynchronous operation the device must be operating on IDT standard mode, FWFT mode is not permissible if the read port is Asynchronous. The Empty Flag (EF) operates in an Asynchronous manner, that is, the empty flag will be updated based on both a read operation and a write operation. Refer to figures 32, 33, 34 and 35 for relevant timing and operational waveforms.

RETRANSMIT (RT)

The Retransmit (RT) input is used in conjunction with the MARK input, together they provide a means by which data previously read out of the FIFO can be reread any number of times. If retransmit operation has been selected (i.e. the MARK input is HIGH), a rising edge on RCLK while RT is LOW will reset the read pointer back to the memory location set by the user via the MARK input.

If IDT standard mode has been selected the EF flag will go LOW and remain LOW for the time that RT is held LOW. RT can be held LOW for any number of RCLK cycles, the read pointer being reset to the marked location. The next rising edge of RCLK after RT has returned HIGH, will cause EF to go HIGH, allowing read operations to be performed on the FIFO. The next read operation will access data from the ‘marked’ memory location.

Subsequent retransmit operations may be performed, each time the read pointer returning to the ‘marked’ location. See Figure 18, Retransmit from Mark (IDT Standard mode) for the relevant timing diagram.

If FWFT mode has been selected the OR flag will go HIGH and remain HIGH for the time that RT is held LOW. RT can be held LOW for any number of RCLK cycles, the read pointer being reset to the ‘marked’ location. The next RCLK rising edge after RT has returned HIGH, will cause OR to go LOW and due to FWFT operation, the contents of the marked memory location will be loaded onto the output register, a read operation being required for all subsequent data reads.

Subsequent retransmit operations may be performed each time the read pointer returning to the ‘marked’ location. See Figure 19, Retransmit from Mark (FWFT mode) for the relevant timing diagram.

ASYNCHRONOUS WRITE (ASYW)

The write port can be configured for either Synchronous or Asynchronous mode of operation. If during Master Reset the ASYW input is LOW, then Asynchronous operation of the write port will be selected. During Asynchronous operation of the write port the WCLK input becomes WR input, this is the Asynchronous write strobe input. A rising edge on WR will write data present on the Dn inputs into the FIFO. (WEN must be tied LOW when using the write port in Asynchronous mode).

When the write port is configured for Asynchronous operation the full flag (FF) operates in an asynchronous manner, that is, the full flag will be updated based in both a write operation and read operation. Note, if Asynchronous mode is selected, FWFT is not permissable. Refer to Figures 30, 31, 34 and 35 for relevant timing and operational waveforms.

ASYNCHRONOUS READ (ASYR)

The read port can be configured for either Synchronous or Asynchronous mode of operation. If during a Master Reset the ASYR input is LOW, then

MARK

The MARK input is used to select Retransmit mode of operation. An RCLK rising edge while MARK is HIGH will mark the memory location of the data currently present on the output register, the device will also be placed into retransmit mode. Note, for the IDT72T7285/72T7295/72T72105, there must be a minimum of 128 bytes of data between the write pointer and read pointer when the MARK is asserted. For the IDT72T72115, there must be a minimum of 256 bytes of data between the write pointer and read pointer when the MARK is asserted. Remember, 8 (x9) bytes = 4 (x18) words = 2 (x36) words = 1 (x72) word. Also, once the MARK is set, the write pointer will not increment past the “marked” location until the MARK is deasserted. This prevents “overwriting” of retransmit data.

The MARK input must remain HIGH during the whole period of retransmit mode, a falling edge of RCLK while MARK is LOW will take the device out of retransmit mode and into normal mode. Any number of MARK locations can be set during FIFO operation, only the last marked location taking effect. Once a mark location has been set the write pointer cannot be incremented past this

IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync 16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72

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 72-BIT FIFO

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COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

marked location. During retransmit mode write operations to the device may continue without hindrance.

FIRST WORD FALL THROUGH/SERIAL IN (FWFT/SI)

This is a dual purpose pin. During Master Reset, the state of the FWFT/ SI input determines whether the device will operate in IDT Standard mode or First Word Fall Through (FWFT) mode.

If, at the time of Master Reset, FWFT/SI is LOW, then IDT Standard mode will be selected. This mode uses the Empty Flag (EF) to indicate whether or not there are any words present in the FIFO memory. It also uses the Full Flag function (FF) to indicate whether or not the FIFO memory has any free space for writing. In IDT Standard mode, every word read from the FIFO, including the first, must be requested using the Read Enable (REN) and RCLK.

If, at the time of Master Reset, FWFT/SI is HIGH, then FWFT mode will be selected. This mode uses Output Ready (OR) to indicate whether or not there is valid data at the data outputs (Q

n). It also uses Input Ready (IR) to indicate

whether or not the FIFO memory has any free space for writing. In the FWFT mode, the first word written to an empty FIFO goes directly to Q

n after three RCLK

rising edges, REN = LOW is not necessary. Subsequent words must be accessed using the Read Enable (REN) and RCLK.

After Master Reset, FWFT/SI acts as a serial input for loading PAE and PAF offsets into the programmable registers. The serial input function can only be used when the serial loading method has been selected during Master Reset. Serial programming using the FWFT/SI pin functions the same way in both IDT Standard and FWFT modes.

WRITE STROBE & WRITE CLOCK (WR/WCLK)

If Synchronous operation of the write port has been selected via ASYW, this input behaves as WCLK.

A write cycle is initiated on the rising edge of the WCLK input. Data setup and hold times must be met with respect to the LOW-to-HIGH transition of the WCLK. It is permissible to stop the WCLK. Note that while WCLK is idle, the FF/ IR, PAF and HF flags will not be updated. (Note that WCLK is only capable of updating HF flag to LOW). The Write and Read Clocks can either be independent or coincident.

If Asynchronous operation has been selected this input is WR (write strobe). Data is Asynchronously written into the FIFO via the Dn inputs whenever there is a rising edge on WR. In this mode the WEN input must be tied LOW.

WRITE ENABLE (WEN)

When the WEN input is LOW, data may be loaded into the FIFO RAM array on the rising edge of every WCLK cycle if the device is not full. Data is stored in the RAM array sequentially and independently of any ongoing read operation.

When WEN is HIGH, no new data is written in the RAM array on each WCLK cycle.

To prevent data overflow in the IDT Standard mode, FF will go LOW, inhibiting further write operations. Upon the completion of a valid read cycle, FF will go HIGH allowing a write to occur. The FF is updated by two WCLK cycles + t

SKEW after the RCLK cycle.

To prevent data overflow in the FWFT mode, IR will go HIGH, inhibiting further write operations. Upon the completion of a valid read cycle, IR will go LOW allowing a write to occur. The IR flag is updated by two WCLK cycles + tSKEW after the valid RCLK cycle.

WEN is ignored when the FIFO is full in either FWFT or IDT Standard mode.

If Asynchronous operation of the write port has been selected, then WEN must be held active, (tied LOW).

READ STROBE & READ CLOCK (RD/RCLK)

If Synchronous operation of the read port has been selected via ASYR, this input behaves as RCLK. A read cycle is initiated on the rising edge of the RCLK input. Data can be read on the outputs, on the rising edge of the RCLK input. It is permissible to stop the RCLK. Note that while RCLK is idle, the EF/OR, PAE and HF flags will not be updated. (Note that RCLK is only capable of updating the HF flag to HIGH). The Write and Read Clocks can be independent or coincident.

If Asynchronous operation has been selected this input is RD (Read Strobe) . Data is Asynchronously read from the FIFO via the output register whenever there is a rising edge on RD. In this mode the REN and RCS inputs must be tied LOW. The OE input is used to provide Asynchronous control of the three-state Qn outputs.

WRITE CHIP SELECT (WCS)

The WCS disables all Write Port inputs (data only) if it is held HIGH. To perform normal operations on the write port, the WCS must be enabled, held LOW.

READ ENABLE (REN)

When Read Enable is LOW, data is loaded from the RAM array into the output register on the rising edge of every RCLK cycle if the device is not empty.

When the REN input is HIGH, the output register holds the previous data and no new data is loaded into the output register. The data outputs Q

0-Qn

maintain the previous data value.

In the IDT Standard mode, every word accessed at Qn, including the first word written to an empty FIFO, must be requested using REN provided that RCS is LOW. When the last word has been read from the FIFO, the Empty Flag (EF) will go LOW, inhibiting further read operations. REN is ignored when the FIFO is empty. Once a write is performed, EF will go HIGH allowing a read to occur. The EF flag is updated by two RCLK cycles + tSKEW after the valid WCLK cycle. Both RCS and REN must be active, LOW for data to be read out on the rising edge of RCLK.

In the FWFT mode, the first word written to an empty FIFO automatically goes to the outputs Qn, on the third valid LOW-to-HIGH transition of RCLK + tSKEW after the first write. REN and RCS do not need to be asserted LOW for the First Word to fall through to the output register. In order to access all other words, a read must be executed using REN and RCS. The RCLK LOW-to-HIGH transition after the last word has been read from the FIFO, Output Ready (OR) will go HIGH with a true read (RCLK with REN = LOW; RCS = LOW), inhibiting further read operations. REN is ignored when the FIFO is empty.

If Asynchronous operation of the Read port has been selected, then REN must be held active, (tied LOW).

SERIAL ENABLE ( SEN )

The SEN input is an enable used only for serial programming of the offset registers. The serial programming method must be selected during Master Reset. SEN is always used in conjunction with LD. When these lines are both LOW, data at the SI input can be loaded into the program register one bit for each LOW-to-HIGH transition of SCLK.

When SEN is HIGH, the programmable registers retains the previous settings and no offsets are loaded. SEN functions the same way in both IDT Standard and FWFT modes.

OUTPUT ENABLE ( OE )

When Output Enable is enabled (LOW), the parallel output buffers receive data from the output register. When OE is HIGH, the output data bus (Qn) goes

IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync 16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72



 72-BIT FIFO



COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

into a high impedance state. During Master or a Partial Reset the OE is the only input that can place the output bus Qn, into High-Impedance. During Reset the RCS input can be HIGH or LOW, it has no effect on the Qn outputs.

READ CHIP SELECT ( RCS )

The Read Chip Select input provides synchronous control of the Read output port. When RCS goes LOW, the next rising edge of RCLK causes the Qn outputs to go to the Low-Impedance state. When RCS goes HIGH, the next RCLK rising edge causes the Qn outputs to return to HIGH Z. During a Master or Partial Reset the RCS input has no effect on the Qn output bus, OE is the only input that provides High-Impedance control of the Qn outputs. If OE is LOW the Qn data outputs will be Low-Impedance regardless of RCS until the first rising edge of RCLK after a Reset is complete. Then if RCS is HIGH the data outputs will go to High-Impedance.

The RCS input does not effect the operation of the flags. For example, when the first word is written to an empty FIFO, the EF will still go from LOW to HIGH based on a rising edge of RCLK, regardless of the state of the RCS input.

Also, when operating the FIFO in FWFT mode the first word written to an empty FIFO will still be clocked through to the output register based on RCLK, regardless of the state of RCS. For this reason the user must take care when a data word is written to an empty FIFO in FWFT mode. If RCS is disabled when an empty FIFO is written into, the first word will fall through to the output register, but will not be available on the Qn outputs which are in HIGH-Z. The user must take RCS active LOW to access this first word, place the output bus in LOW-Z. REN must remain disabled HIGH for at least one cycle after RCS has gone LOW. A rising edge of RCLK with RCS and REN active LOW, will read out the next word. Care must be taken so as not to lose the first word written to an empty FIFO when RCS is HIGH. Refer to Figure 17,

RCS

and

REN

Read Operation (FWFT Mode). The RCS pin must also be active (LOW) in order to perform a Retransmit. See Figure 13 for Read Cycle and Read Chip Select Timing (IDT Standard Mode). See Figure 16 for Read Cycle and Read Chip Select Timing (First Word Fall Through Mode).

If Asynchronous operation of the Read port has been selected, then RCS

must be held active, (tied LOW). OE provides three-state control of Qn.

WRITE PORT HSTL SELECT (WHSTL)

The control inputs, data inputs and flag outputs associated with the write port can be setup to be either HSTL or LVTTL. If WHSTL is HIGH during the Master Reset, then HSTL operation of the write port will be selected. If WHSTL is LOW at Master Reset, then LVTTL will be selected.

The inputs and outputs associated with the write port are listed in Table 5.

READ PORT HSTL SELECT (RHSTL)

The control inputs, data inputs and flag outputs associated with the read port can be setup to be either HSTL or LVTTL. If RHSTL is HIGH during the Master Reset, then HSTL operation of the read port will be selected. If RHSTL is LOW at Master Reset, then LVTTL will be selected for the read port, then echo clock and echo read enable will not be provided.

The inputs and outputs associated with the read port are listed in Table 5.

SYSTEM HSTL SELECT (SHSTL)

All inputs not associated with the write and read port can be setup to be either HSTL or LVTTL. If SHSTL is HIGH during Master Reset, then HSTL operation of all the inputs not associated with the write and read port will be selected. If SHSTL is LOW at Master Reset, then LVTTL will be selected. The inputs associated with SHSTL are listed in Table 5.

LOAD (LD)

This is a dual purpose pin. During Master Reset, the state of the LD input, along with FSEL0 and FSEL1, determines one of eight default offset values for the PAE and PAF flags, along with the method by which these offset registers can be programmed, parallel or serial (see Table 2). After Master Reset, LD enables write operations to and read operations from the offset registers. Only the offset loading method currently selected can be used to write to the registers. Offset registers can be read only in parallel.

After Master Reset, the LD pin is used to activate the programming process of the flag offset values PAE and PAF. Pulling LD LOW will begin a serial loading or parallel load or read of these offset values. THIS PIN MUST BE HIGH AFTER MASTER RESET TO WRITE OR READ DATA TO/FROM THE FIFO MEMORY.

BUS-MATCHING (BM, IW, OW)

The pins BM, IW and OW are used to define the input and output bus widths. During Master Reset, the state of these pins is used to configure the device bus sizes. See Table 1 for control settings. All flags will operate on the word/byte size boundary as defined by the selection of bus width. See Figure 5 for Bus- Matching Byte Arrangement.

BIG-ENDIAN/LITTLE-ENDIAN ( BE )

During Master Reset, a LOW on BE will select Big-Endian operation. A HIGH on BE during Master Reset will select Little-Endian format. This function is useful when the following input to output bus widths are implemented: x72 to x36, x72 to x18, x36 to x72 and x18 to x72. If Big-Endian mode is selected, then the most significant byte (word) of the long word written into the FIFO will be read out of the FIFO first, followed by the least significant byte. If Little-Endian format is selected, then the least significant byte of the long word written into the FIFO will be read out first, followed by the most significant byte. The mode desired is configured during master reset by the state of the Big-Endian (BE) pin. See Figure 5 for Bus-Matching Byte Arrangement.

PROGRAMMABLE FLAG MODE (PFM)

During Master Reset, a LOW on PFM will select Asynchronous Programmable flag timing mode. A HIGH on PFM will select Synchronous Programmable flag timing mode. If asynchronous PAF/PAE configuration is selected (PFM, LOW during MRS), the PAE is asserted LOW on the LOW-to-HIGH transition of RCLK. PAE is reset to HIGH on the LOW-to-HIGH transition of WCLK. Similarly, the PAF is asserted LOW on the LOW-to-HIGH transition of WCLK and PAF is reset to HIGH on the LOW-to-HIGH transition of RCLK.

If synchronous PAE/PAF configuration is selected (PFM, HIGH during MRS) , the PAE is asserted and updated on the rising edge of RCLK only and not WCLK. Similarly, PAF is asserted and updated on the rising edge of WCLK only and not RCLK. The mode desired is configured during master reset by the state of the Programmable Flag Mode (PFM) pin.

INTERSPERSED PARITY (IP)

During Master Reset, a LOW on IP will select Non-Interspersed Parity mode. A HIGH will select Interspersed Parity mode. The IP bit function allows the user to select the parity bit in the word loaded into the parallel port (D

0-Dn)

when programming the flag offsets. If Interspersed Parity mode is selected, then the FIFO will assume that the parity bits are located in bit position D8, D17, D26, D35, D44, D53, D62 and D71 during the parallel programming of the flag offsets. If Non-Interspersed Parity mode is selected, then D8, D17 and D28 are is assumed to be valid bits and D64, D65, D66, D67, D68, D69, D70 and D71 are ignored. IP mode is selected during Master Reset by the state of the IP input pin.

IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync 16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72



 72-BIT FIFO

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COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

OUTPUTS:

FULL FLAG ( FF/IR )

This is a dual purpose pin. In IDT Standard mode, the Full Flag (FF) function is selected. When the FIFO is full, FF will go LOW, inhibiting further write operations. When FF is HIGH, the FIFO is not full. If no reads are performed after a reset (either MRS or PRS), FF will go LOW after D writes to the FIFO (D =16,384 for the IDT72T7285, 32,768 for the IDT72T7295, 65,536 for the IDT72T72105 and 131,072 for the IDT72T72115). See Figure 11, Write Cycle and Full Flag Timing (IDT Standard Mode), for the relevant timing information.

In FWFT mode, the Input Ready (IR) function is selected. IR goes LOW when memory space is available for writing in data. When there is no longer any free space left, IR goes HIGH, inhibiting further write operations. If no reads are performed after a reset (either MRS or PRS), IR will go HIGH after D writes to the FIFO (D =16,385 for the IDT72T7285, 32,769 for the IDT72T7295, 65,537 for the IDT72T72105 and 131,073 for the IDT72T72115). See Figure 14, Write Timing (FWFT Mode), for the relevant timing information.

The IR status not only measures the contents of the FIFO memory, but also counts the presence of a word in the output register. Thus, in FWFT mode, the total number of writes necessary to deassert IR is one greater than needed to assert FF in IDT Standard mode.

FF/IR is synchronous and updated on the rising edge of WCLK. FF/IR are double register-buffered outputs.

Note, when the device is in Retransmit mode, this flag is a comparison of the write pointer to the ‘marked’ location. This differs from normal mode where this flag is a comparison of the write pointer to the read pointer.

EMPTY FLAG ( EF/OR )

This is a dual purpose pin. In the IDT Standard mode, the Empty Flag (EF) function is selected. When the FIFO is empty, EF will go LOW, inhibiting further read operations. When EF is HIGH, the FIFO is not empty. See Figure 12, Read Cycle, Empty Flag and First Word Latency Timing (IDT Standard Mode), for the relevant timing information.

In FWFT mode, the Output Ready (OR) function is selected. OR goes LOW at the same time that the first word written to an empty FIFO appears valid on the outputs. OR stays LOW after the RCLK LOW to HIGH transition that shifts the last word from the FIFO memory to the outputs. OR goes HIGH only with a true read (RCLK with REN = LOW). The previous data stays at the outputs, indicating the last word was read. Further data reads are inhibited until OR goes LOW again. See Figure 15, Read Timing (FWFT Mode), for the relevant timing information.

EF/OR is synchronous and updated on the rising edge of RCLK.

In IDT Standard mode, EF is a double register-buffered output. In FWFT

mode, OR is a triple register-buffered output.

PROGRAMMABLE ALMOST-FULL FLAG ( PAF )

The Programmable Almost-Full flag (PAF) will go LOW when the FIFO reaches the almost-full condition. In IDT Standard mode, if no reads are performed after reset (MRS), PAF will go LOW after (D - m) words are written to the FIFO. The PAF will go LOW after (16,384-m) writes for the IDT72T7285, (32,768-m) writes for the IDT72T7295, (65,536-m) writes for the IDT72T72105 and (131,072-m) writes for the IDT72T72115. The offset “m” is the full offset

value. The default setting for this value is stated in the footnote of Table 3.

In FWFT mode, the PAF will go LOW after (16,385-m) writes for the IDT72T7285, (32,769-m) writes for the IDT72T7295, (65,537-m) writes for the IDT72T72105 and (131,073-m) writes for the IDT72T72115, where m is the full offset value. The default setting for this value is stated in Table 4.

See Figure 23, Synchronous Programmable Almost-Full Flag Timing (IDT Standard and FWFT Mode), for the relevant timing information.

If asynchronous PAF configuration is selected, the PAF is asserted LOW on the LOW-to-HIGH transition of the Write Clock (WCLK). PAF is reset to HIGH on the LOW-to-HIGH transition of the Read Clock (RCLK). If synchronous PAF configuration is selected, the PAF is updated on the rising edge of WCLK. See Figure 25, Asynchronous Almost-Full Flag Timing (IDT Standard and FWFT Mode).

PROGRAMMABLE ALMOST-EMPTY FLAG ( PAE )

The Programmable Almost-Empty flag (PAE) will go LOW when the FIFO reaches the almost-empty condition. In IDT Standard mode, PAE will go LOW when there are n words or less in the FIFO. The offset “n” is the empty offset value. The default setting for this value is stated in the footnote of Table 1.

In FWFT mode, the PAE will go LOW when there are n+1 words or less in the FIFO. The default setting for this value is stated in Table 2.

See Figure 24, Synchronous Programmable Almost-Empty Flag Timing

(IDT Standard and FWFT Mode), for the relevant timing information.

If asynchronous PAE configuration is selected, the PAE is asserted LOW on the LOW-to-HIGH transition of the Read Clock (RCLK). PAE is reset to HIGH on the LOW-to-HIGH transition of the Write Clock (WCLK). If synchronous PAE configuration is selected, the PAE is updated on the rising edge of RCLK. See Figure 26, Asynchronous Programmable Almost-Empty Flag Timing (IDT Standard and FWFT Mode).

HALF-FULL FLAG ( HF )

This output indicates a half-full FIFO. The rising WCLK edge that fills the FIFO beyond half-full sets HF LOW. The flag remains LOW until the difference between the write and read pointers becomes less than or equal to half of the total depth of the device; the rising RCLK edge that accomplishes this condition sets HF HIGH.

In IDT Standard mode, if no reads are performed after reset (MRS or PRS), HF will go LOW after (D/2 + 1) writes to the FIFO, where D = 16,384 for the IDT72T7285, 32,768 for the IDT72T7295, 65,536 for the IDT72T72105 and 131,072 for the IDT72T72115.

In FWFT mode, if no reads are performed after reset (MRS or PRS), HF will go LOW after (D-1/2 + 2) writes to the FIFO, where D = 16,385 for the IDT72T7285, 32,769 for the IDT72T7295, 65,537 for the IDT72T72105 and 131,073 for the IDT72T72115.

See Figure 27, Half-Full Flag Timing (IDT Standard and FWFT Modes), for the relevant timing information. Because HF is updated by both RCLK and WCLK, it is considered asynchronous.

IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync 16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72



 72-BIT FIFO



COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

ECHO READ CLOCK (ERCLK)

The Echo Read Clock output is provided in both HSTL and LVTTL mode, selectable via RHSTL. The ERCLK is a free-running clock output, it will always follow the RCLK input regardless of REN and RCS.

The ERCLK output follows the RCLK input with an associated delay. This delay provides the user with a more effective read clock source when reading data from the Qn outputs. This is especially helpful at high speeds when variables within the device may cause changes in the data access times. These variations in access time maybe caused by ambient temperature, supply voltage, device characteristics. The ERCLK output also compensates for any trace length delays between the Qn data outputs and receiving devices inputs.

Any variations effecting the data access time will also have a corresponding effect on the ERCLK output produced by the FIFO device, therefore the ERCLK output level transitions should always be at the same position in time relative to the data outputs. Note, that ERCLK is guaranteed by design to be slower than the slowest Qn, data output. Refer to Figure 4, Echo Read Clock and Data Output Relationship, Figure 28, Echo Read Clock & Read Enable Operation and Figure 29, Echo RCLK & Echo

RCLK

ERCLK

REN

Operation for timing information.

ERCLK

ECHO READ ENABLE (EREN)

The Echo Read Enable output is provided in both HSTL and LVTTL mode,

selectable via RHSTL.

The EREN output is provided to be used in conjunction with the ERCLK output and provides the reading device with a more effective scheme for reading data from the Qn output port at high speeds. The EREN output is controlled by internal logic that behaves as follows: The EREN output is active LOW for the RCLK cycle that a new word is read out of the FIFO. That is, a rising edge of RCLK will cause EREN to go active, LOW if both REN and RCS are active, LOW and the FIFO is NOT empty.

SERIAL CLOCK (SCLK)

During serial loading of the programming flag offset registers, a rising edge on the SCLK input is used to load serial data present on the SI input provided that the SEN input is LOW.

DATA OUTPUTS (Q

0-Q71) are data outputs for 72-bit wide data, (Q0 - Q35) are data outputs

(Q for 36-bit wide data or (Q

0-Qn)

0-Q17) are data outputs for 18-bit wide data.

(3)

SLOWEST

NOTES:

1. REN is LOW.

ERCLK > tA, guaranteed by design.

2. t

3. Qslowest is the data output with the slowest access time, t

D is greater than zero, guaranteed by design.

4. Time, t

Figure 4. Echo Read Clock and Data Output Relationship

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IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync 16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72



 72-BIT FIFO



COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

BYTE ORDER ON INPUT PORT:

BYTE ORDER ON OUTPUT PORT:

BE BM IW OW

X L X X

BE BM IW OW

L H L L

BE BM IW OW

H H L L

D71-D54 D53-D36 D35-D18 D17-D0

Q71-Q54 Q53-Q36 Q35-Q18 Q17-Q0

(a) x72 INPUT to x72 OUTPUT

Q71-Q54 Q53-Q36 Q35-Q18 Q17-Q0

(b) x72 INPUT to x36 OUTPUT - BIG-ENDIAN

Q71-Q54 Q53-Q36 Q35-Q18 Q17-Q0

Write to FIFO

Read from FIFO

1st: Read from FIFO

2nd: Read from FIFO

1st: Read from FIFO

2nd: Read from FIFO

BE BM IW OW

L H L H

BE BM IW OW

H H L H

Q71-Q54 Q53-Q36 Q35-Q18 Q17-Q0

(d) x72 INPUT to x18 OUTPUT - BIG-ENDIAN

Q71-Q54 Q53-Q36 Q35-Q18 Q17-Q0

1st: Read from FIFO

2nd: Read from FIFO

3rd: Read from FIFO

4th: Read from FIFO

1st: Read from FIFO

2nd: Read from FIFO

3rd: Read from FIFO

4th: Read from FIFO

(e) x72 INPUT to x18 OUTPUT - LITTLE-ENDIAN

Figure 5. Bus-Matching Byte Arrangement

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IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync 16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72



 72-BIT FIFO



COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

BYTE ORDER ON INPUT PORT:

BYTE ORDER ON OUTPUT PORT:

BE BM IW OW

L H H L

BE BM IW OW

H H H L

BYTE ORDER ON INPUT PORT:

D71-D54 D53-D36 D35-D18 D17-D0

Q71-Q54 Q53-Q36 Q35-Q18 Q17-Q0

(a) x36 INPUT to x72 OUTPUT - BIG-ENDIAN

Q71-Q54 Q53-Q36 Q35-Q18 Q17-Q0

(b) x36 INPUT to x72 OUTPUT - LITTLE-ENDIAN

Q71-Q54 Q53-Q36 Q35-Q18 Q17-Q0

1st: Write to FIFO

2nd: Write to FIFO

Read from FIFO

1st: Write to FIFO

BYTE ORDER ON OUTPUT PORT:

BE BM IW OW

L H H H

BE BM IW OW

H H H H

Q71-Q54 Q53-Q36 Q35-Q18 Q17-Q0

ABCD

(a) x18 INPUT to x72 OUTPUT - BIG-ENDIAN

Q71-Q54 Q53-Q36 Q35-Q18 Q17-Q0

(b) x18 INPUT to x72 OUTPUT - LITTLE-ENDIAN

2nd: Write to FIFO

3rd: Write to FIFO

4th: Write to FIFO

Read from FIFO

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Figure 5. Bus-Matching Byte Arrangement (Continued)

IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync 16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72

JTAG TIMING SPECIFICATION

TCK

TDI/ TMS



 72-BIT FIFO



COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

TDO

TRST

TDO

Notes to diagram:

TCKLOW

t1 = t2 = t

TCKHIGH

t3 = t

TCKFALL

t4 = t

TCKRISE

t5 = tRST t6 = tRSR (reset recovery)

(reset pulse width)

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Figure 6. Standard JTAG Timing

JTAG AC ELECTRICAL CHARACTERISTICS

(vcc = 2.5V ± 5%; Tcase = 0°C to +85°C)

SYSTEM INTERFACE PARAMETERS

IDT72T7285

IDT72T7295 IDT72T72105 IDT72T72115

Parameter Symbol Test Conditions Min. Max. Units

(1)

Data Output t

Data Output Hold tDOH

(1)

Data Input tDS trise=3ns 10 - ns

tDH tfall=3ns 10 -

NOTE:

1. 50pf loading on external output signals.

-20ns 0-ns

Parameter Symbol Test

Conditions

Min. Max. Units JTAG Clock Input Period tTCK - 100 - ns JTAG Clock HIGH tTCKHIGH -40-ns JTAG Clock Low tTCKLOW -40-ns JTAG Clock Rise Time tTCKRISE --5 JTAG Clock Fall Time tTCKFALL --5

(1)

ns JTAG Reset tRST -50-ns JTAG Reset Recovery tRSR -50-ns

NOTE:

1. Guaranteed by design.

IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync 16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72



 72-BIT FIFO



COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

JTAG INTERFACE

Five additional pins (TDI, TDO, TMS, TCK and TRST) are provided to support the JTAG boundary scan interface. The IDT72T7285/72T7295/ 72T72105/72T72115 incorporates the necessary tap controller and modified pad cells to implement the JTAG facility.

Note that IDT provides appropriate Boundary Scan Description Language program files for these devices.

The Standard JTAG interface consists of four basic elements:

• Test Access Port (TAP)

• TAP controller

• Instruction Register (IR)

• Data Register Port (DR)

The following sections provide a brief description of each element. For a complete description refer to the IEEE Standard Test Access Port Specification (IEEE Std. 1149.1-1990).

The Figure below shows the standard Boundary-Scan Architecture

DeviceID Reg.

Boundary Scan Reg.

Mux

TDO TDI

TMS TCLK

TRST

Bypass Reg.

clkDR, ShiftDR

UpdateDR

TAP

Controller

clklR, ShiftlR

UpdatelR

Instruction Register

Control Signals

Instruction Decode

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Figure 7. Boundary Scan Architecture

TEST ACCESS PORT (TAP)

The Tap interface is a general-purpose port that provides access to the internal of the processor. It consists of four input ports (TCLK, TMS, TDI, TRST) and one output port (TDO).

THE TAP CONTROLLER

The Tap controller is a synchronous finite state machine that responds to TMS and TCLK signals to generate clock and control signals to the Instruction and Data Registers for capture and update of data.

IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync 16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72

Test-Logic Reset

Run-Test/ Idle



 72-BIT FIFO



SelectDR-Scan

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

SelectIR-Scan

Capture-DR

Shift-DR

Input = TMS

NOTES:

1. Five consecutive TCK cycles with TMS = 1 will reset the TAP.

2. TAP controller does not automatically reset upon power-up. The user must provide a reset to the TAP controller (either by TRST or TMS).

3. TAP controller must be reset before normal FIFO operations can begin.

EXit1-DR

Pause-DR

Exit2-DR

Update-DR

Capture-IR

Shift-IR

Exit1-IR

Pause-IR

Exit2-IR

Update-IR

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Figure 8. TAP Controller State Diagram

Refer to the IEEE Standard Test Access Port Specification (IEEE Std.

1149.1) for the full state diagram All state transitions within the TAP controller occur at the rising edge of the

TCLK pulse. The TMS signal level (0 or 1) determines the state progression that occurs on each TCLK rising edge. The TAP controller takes precedence over the FIFO memory and must be reset after power up of the device. See TRST description for more details on TAP controller reset.

Test-Logic-Reset All test logic is disabled in this controller state enabling the normal operation of the IC. The TAP controller state machine is designed in such a way that, no matter what the initial state of the controller is, the Test-Logic-Reset state can be entered by holding TMS at high and pulsing TCK five times. This is the reason why the Test Reset (TRST) pin is optional.

Run-Test-Idle In this controller state, the test logic in the IC is active only if certain instructions are present. For example, if an instruction activates the self test, then it will be executed when the controller enters this state. The test logic in the IC is idles otherwise.

Select-DR-Scan This is a controller state where the decision to enter the Data Path or the Select-IR-Scan state is made.

Select-IR-Scan This is a controller state where the decision to enter the Instruction Path is made. The Controller can return to the Test-Logic-Reset state other wise.

Capture-IR In this controller state, the shift register bank in the Instruction Register parallel loads a pattern of fixed values on the rising edge of TCK. The last two significant bits are always required to be “01”.

Shift-IR In this controller state, the instruction register gets connected between TDI and TDO, and the captured pattern gets shifted on each rising edge of TCK. The instruction available on the TDI pin is also shifted in to the instruction register.

Exit1-IR This is a controller state where a decision to enter either the PauseIR state or Update-IR state is made.

Pause-IR This state is provided in order to allow the shifting of instruction register to be temporarily halted.

Exit2-DR This is a controller state where a decision to enter either the ShiftIR state or Update-IR state is made.

Update-IR In this controller state, the instruction in the instruction register is latched in to the latch bank of the Instruction Register on every falling edge of TCK. This instruction also becomes the current instruction once it is latched.

Capture-DR In this controller state, the data is parallel loaded in to the data registers selected by the current instruction on the rising edge of TCK.

Shift-DR, Exit1-DR, Pause-DR, Exit2-DR and Update-DR These controller states are similar to the Shift-IR, Exit1-IR, Pause-IR, Exit2-IR and Update-IR states in the Instruction path.

IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync 16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72



 72-BIT FIFO



COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

THE INSTRUCTION REGISTER

The Instruction register allows an instruction to be shifted in serially into the

processor at the rising edge of TCLK.

The Instruction is used to select the test to be performed, or the test data register to be accessed, or both. The instruction shifted into the register is latched at the completion of the shifting process when the TAP controller is at UpdateIR state.

The instruction register must contain 4 bit instruction register-based cells which can hold instruction data. These mandatory cells are located nearest the serial outputs they are the least significant bits.

TEST DATA REGISTER

The Test Data register contains three test data registers: the Bypass, the Boundary Scan register and Device ID register.

These registers are connected in parallel between a common serial input and a common serial data output.

The following sections provide a brief description of each element. For a complete description, refer to the IEEE Standard Test Access Port Specification (IEEE Std. 1149.1-1990).

TEST BYPASS REGISTER

The register is used to allow test data to flow through the device from TDI to TDO. It contains a single stage shift register for a minimum length in serial path. When the bypass register is selected by an instruction, the shift register stage is set to a logic zero on the rising edge of TCLK when the TAP controller is in the Capture-DR state.

The operation of the bypass register should not have any effect on the operation of the device in response to the BYPASS instruction.

THE BOUNDARY-SCAN REGISTER

The Boundary Scan Register allows serial data TDI be loaded in to or read out of the processor input/output ports. The Boundary Scan Register is a part of the IEEE 1149.1-1990 Standard JTAG Implementation.

THE DEVICE IDENTIFICATION REGISTER

The Device Identification Register is a Read Only 32-bit register used to specify the manufacturer, part number and version of the processor to be determined through the TAP in response to the IDCODE instruction.

IDT JEDEC ID number is 0xB3. This translates to 0x33 when the parity is dropped in the 11-bit Manufacturer ID field.

For the IDT72T7285/72T7295/72T72105/72T72115, the Part Number field contains the following values:

Device Part# Field IDT72T7285 0493 IDT72T7295 0492

IDT72T72105 0491 IDT72T72115 0490

31(MSB) 28 27 12 11 1 0(LSB) Version (4 bits) Part Number (16-bit) Manufacturer ID (11-bit)

0X0 0X33 1

IDT72T7285/95/105/115 JTAG Device Identification Register

JTAG INSTRUCTION REGISTER

The Instruction register allows instruction to be serially input into the device when the TAP controller is in the Shift-IR state. The instruction is decoded to perform the following:

• Select test data registers that may operate while the instruction is current.

The other test data registers should not interfere with chip operation and the selected data register.

• Define the serial test data register path that is used to shift data between

TDI and TDO during data register scanning.

The Instruction Register is a 4 bit field (i.e. IR3, IR2, IR1, IR0) to decode 16 different possible instructions. Instructions are decoded as follows.

Hex Value Instruction Function

0x00 EXTEST Select Boundary Scan Register 0x02 IDCODE Select Chip Identification data register 0x01 SAMPLE/PRELOAD Select Boundary Scan Register 0x03 HIGH-IMPEDANCE JTAG 0x0F BYPASS Select Bypass Register

JTAG Instruction Register Decoding

The following sections provide a brief description of each instruction. For a complete description refer to the IEEE Standard Test Access Port Specification (IEEE Std. 1149.1-1990).

EXTEST

The required EXTEST instruction places the IC into an external boundarytest mode and selects the boundary-scan register to be connected between TDI and TDO. During this instruction, the boundary-scan register is accessed to drive test data off-chip via the boundary outputs and receive test data off-chip via the boundary inputs. As such, the EXTEST instruction is the workhorse of IEEE. Std 1149.1, providing for probe-less testing of solder-joint opens/shorts and of logic cluster function.

IDCODE

The optional IDCODE instruction allows the IC to remain in its functional mode and selects the optional device identification register to be connected between TDI and TDO. The device identification register is a 32-bit shift register containing information regarding the IC manufacturer, device type, and version code. Accessing the device identification register does not interfere with the operation of the IC. Also, access to the device identification register should be immediately available, via a TAP data-scan operation, after power-up of the IC or after the TAP has been reset using the optional TRST pin or by otherwise moving to the Test-Logic-Reset state.

SAMPLE/PRELOAD

The required SAMPLE/PRELOAD instruction allows the IC to remain in a normal functional mode and selects the boundary-scan register to be connected between TDI and TDO. During this instruction, the boundary-scan register can be accessed via a date scan operation, to take a sample of the functional data entering and leaving the IC. This instruction is also used to preload test data into the boundary-scan register before loading an EXTEST instruction.

HIGH-IMPEDANCE

The optional High-Impedance instruction sets all outputs (including two-state as well as three-state types) of an IC to a disabled (high-impedance) state and selects the one-bit bypass register to be connected between TDI and TDO. During this instruction, data can be shifted through the bypass register from TDI to TDO without affecting the condition of the IC outputs.

BYPASS

The required BYPASS instruction allows the IC to remain in a normal functional mode and selects the one-bit bypass register to be connected between TDI and TDO. The BYPASS instruction allows serial data to be transferred through the IC from TDI to TDO without affecting the operation of the IC.

IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync 16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72

MRS

REN

WEN

FWFT/SI

FSEL0,

FSEL1

OW,

IW, BM

WHSTL

RHSTL

HRSS

RSS



 72-BIT FIFO



RSR

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

SHSTL

PFM

SEN

EF/OR

FF/IR

PAE

PAF, HF

- Q

HRSS

RSS

RSF

If FWFT = HIGH, OR = HIGH

If FWFT = LOW, EF = LOW

RSF

If FWFT = LOW, FF = HIGH

If FWFT = HIGH, IR = LOW

RSF

(1)

OE = HIGH

OE = LOW

5994 drw14

NOTE:

1. During Master Reset the High-Impedance control of the Qn data outputs is provided by OE only, RCS can be HIGH or LOW until the first rising edge of RCLK after Master Reset is complete.

Figure 9. Master Reset Timing

IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync 16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72

PRS

RSS

REN

RSS

WEN

RSS

SEN



 72-BIT FIFO



RSR

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

If FWFT = HIGH, OR = HIGH

If FWFT = LOW, EF = LOW

If FWFT = LOW, FF = HIGH

If FWFT = HIGH, IR = LOW

EF/OR

FF/IR

RSF

PAE

RSF

PAF, HF

RSF

(1)

- Q

NOTE:

1. During Partial Reset the High-Impedance control of the Qn data outputs is provided by OE only, RCS can be HIGH or LOW until the first rising edge of RCLK after Master Reset is complete.

OE = HIGH

OE = LOW

5994 drw15

Figure 10. Partial Reset Timing

IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync 16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72

CLKH

tDS

WFF

WCLK

D0 - Dn

WEN

RCLK

REN

RCS

Q0 - Qn

tENS

SKEW1

tRCSLZ

NO WRITE

ENH

(1)



 72-BIT FIFO



CLK

CLKL

WFF

DATA READ

ENS

SKEW1

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

NO WRITE

(1)

ENH

tDS

WFF

NEXT DATA READ

X+1

WFF

5994 drw16

NOTES:

SKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH (after one WCLK cycle pus tWFF). If the time between the

1. t rising edge of the RCLK and the rising edge of the WCLK is less than t

SKEW1, then the FF deassertion may be delayed one extra WCLK cycle.

2. LD = HIGH, OE = LOW, EF = HIGH.

3. WCS = LOW.

Figure 11. Write Cycle and Full Flag Timing (IDT Standard Mode)

CLKH

REF

CLK

CLKL

ENS

ENH

ENS

REF

ENH

RCLK

REN

ENS

ENH

REF

NO OPERATION

Q0 - Qn

WCLK

LAST WORD

OLZ

(1)

SKEW1

ENS

ENH

OHZ

ENS

ENH

tOLZ

LAST WORD

WEN

WCS

D0 - Dn

WCSS

WCSH

NOTES:

SKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH (after one RCLK cycle plus tREF). If the time between the

1. t rising edge of WCLK and the rising edge of RCLK is less than t

SKEW1, then EF deassertion may be delayed one extra RCLK cycle.

2. LD = HIGH.

3. First data word latency = t

SKEW1 + 1*TRCLK + tREF.

4. RCS is LOW.

Figure 12. Read Cycle, Output Enable, Empty Flag and First Data Word Latency (IDT Standard Mode)

5994 drw17

IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync 16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72



 72-BIT FIFO



COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

RCLK

ENS

REN

ENS

ENH

ENS

RCS

Q0 - Qn

RCSLZ

REF

LAST DATA-1

RCSHZ

RCSLZ

LAST DATA

tSKEW1

RCSHZ

(1)

REF

WCLK

ENS

ENH

WEN

NOTES:

SKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH (after one RCLK cycle plus tREF). If the time between the

1. t rising edge of WCLK and the rising edge of RCLK is less than t

SKEW1, then EF deassertion may be delayed one extra RCLK cycle.

2. LD = HIGH.

3. First data word latency = t

SKEW1 + 1*TRCLK + tREF.

4. OE is LOW.

5994 drw18

Figure 13. Read Cycle and Read Chip Select (IDT Standard Mode)

IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync 16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72

ENH

[D-1]

[D-m+2]

[D-m+1]

[D-m]

[D-m-1]

[D-m-2]

][

D-1

][

D-1

][

D-1



 72-BIT FIFO



PAFS

WFF

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

5994 drw19

WCLK

ENS

WEN

[n+4]

(2)

PAES

SKEW2, then the PAE deassertion may be delayed one extra RCLK cycle.

SKEW1, then OR assertion may be delayed one extra RCLK cycle.

PAE

PAF

SKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that OR will go LOW after two RCLK cycles plus tREF. If the time between the rising edge of WCLK and the rising edge of RCLK

SKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that PAE will go HIGH after one RCLK cycle plus tPAES. If the time between the rising edge of WCLK and the rising edge of RCLK

is less than t

3. LD = HIGH, OE = LOW

4. n = PAE offset, m = PAF offset and D = maximum FIFO depth.

NOTES:

1. t

2. t

5. D = 16,385 for IDT72T7285, 32,769 for IDT72T7295, 65,537 for IDT72T72105 and 131,073 for IDT72T72115.

Figure 14. Write Timing (First Word Fall Through Mode)

SKEW1 + 2*TRCLK + tREF.

6. First data word latency = t

[n+3]

SKEW2

[n +2]

(1)

SKEW1

D0 - Dn

RCLK

ENS

RCS

REN

REF

RCSLZ

PREVIOUS DATA IN OUTPUT REGISTER

Q0 - Qn

IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync 16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72



 72-BIT FIFO



COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

5994 drw20

tENS

tREF

W[D-1]

W[D-n+1]W[m+4] W[D-n+2]

tPAES

W[D-n]W[D-n-1]

(2)

tSKEW2

(1)

tSKEW1

tENH

tDH

tDS

tENS

WEN

WCLK

D0 - Dn

RCLK

tENS

REN

tA tA

tOE tA

tOHZ

][

D-1

][

D-1

W[m+3]

Wm+2

W1 W1 W2 W3

Q0 - Qn

PAE

tHF

tPAFS

Figure 15. Read Timing (First Word Fall Through Mode)

tWFF

SKEW2, then the PAF deassertion may be delayed one extra WCLK cycle.

SKEW1, then the IR assertion may be delayed one extra WCLK cycle.

PAF

SKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that IR will go LOW after one WCLK cycle plus tWFF. If the time between the rising edge of RCLK and the rising edge of WCLK

SKEW2 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that PAF will go HIGH after one WCLK cycle plus tPAFS. If the time between the rising edge of RCLK and the rising edge of WCLK

is less than t

NOTES:

1. t

3. LD = HIGH.

4. n = PAE Offset, m = PAF offset and D = maximum FIFO depth.

5. D = 16,385 for IDT72T7285, 32,769 for IDT72T7295, 65,537 for IDT72T72105 and 131,073 for IDT72T72115.

2. t

6. RCS = LOW.

IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync 16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72



 72-BIT FIFO



COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

5994 drw21

ENS

REF

[D-1]

[D-n+2]

[D-n+1]

PAES

[D-n]

[D-n-1]

][

D-1

][

D-1

(2)

SKEW2

(1)

SKEW1

ENH

ENS

WEN

WCLK

D0 - Dn

RCLK

ENS

REN

ENH

RCS

RCSLZ

RCSHZ

[m+4]

[m+3]

m+2

Q0 - Qn

PAE

PAFS

PAF

WFF

Figure 16. Read Cycle and Read Chip Select Timing (First Word Fall Through Mode)

SKEW2, then the PAF deassertion may be delayed one extra WCLK cycle.

SKEW1, then the IR assertion may be delayed one extra WCLK cycle.

is less than t

NOTES:

1. t

3. LD = HIGH.

4. n = PAE Offset, m = PAF offset and D = maximum FIFO depth.

5. D = 16,385 for IDT72T7285, 32,769 for IDT72T7295, 65,537 for IDT72T72105 and 131,073 for IDT72T72115.

2. t

6. OE = LOW.

IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync 16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72

5994 drw22

REF

RCSLZ

ENS



 72-BIT FIFO



COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

ENH

ENS

ENH

ENS

RCSHZ

RCSLZ

W1 W2

1st Word falls through to

O/P register on this cycle

Read Operation (FWFT Mode)

REN

and

RCS

REF

HIGH-Z

REN

RCLK

SKEW

WCLK

ENH

ENS

WEN

Figure 17 .

bus goes to LOW-Z.

NOTES:

1. It is very important that the REN be held HIGH for at least one cycle after RCS has gone LOW. If REN goes LOW on the same cycle as RCS or earlier, then Word, W1 will be lost, Word, W2 will be read on the output when the

2. The 1st Word will fall through to the output register regardless of REN and RCS. However, subsequent reads require that both REN and RCS be active, LOW.

IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync 16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72



 72-BIT FIFO



COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

MK+1

ENS

REF

MK+n

ENH

ENS

REF

ENS

(6)

PAES

SKEW2

ENS

PAFS

5994 drw23

ENS

MK+1

MK-1

ENH

ENS

Figure 18. Retransmit from Mark (IDT Standard Mode)

RCLK

REN

MARK

PAE

WCLK

WEN

PAF

NOTES:

Remember, 8 bytes = 4 (x16) words = 2 (x36) words = 1 (x72) word.

1. Retransmit setup is complete when EF returns HIGH.

2. OE = LOW; RCS = LOW.

3. RT must be HIGH when reading from FIFO.

6. A transition in the PAE flag may occur one RCLK cycle earlier than shown, (on cycle 2).

4. Once MARK is set, the write pointer will not increment past the ‘marked’ location, preventing overwrites of Retransmit data.

5. Before a “MARK” can be set there must be at least x number of bytes of data between the Write Pointer and Read Pointer locations. For the IDT72T7285/72T7295/72T72105 x = 128, for the IDT72T72115 x = 256.

IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync 16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72



 72-BIT FIFO



COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

MK+2

ENS

MK+1

REF

MK+n

ENH

ENS

REF

ENS

(6)

PAES

SKEW2

ENS

PAFS

5994 drw24

ENS

MK+1

Figure 19. Retransmit from Mark (First Word Fall Through Mode)

MK-1

ENH

ENS

RCLK

REN

MARK

PAE

WCLK

WEN

PAF

NOTES:

Remember, 8 bytes = 4 (x16) words = 2 (x36) words = 1 (x72) word.

1. Retransmit setup is complete when OR returns LOW.

2. OE = LOW; RCS = LOW.

3. RT must be HIGH when reading from FIFO.

4. Once MARK is set, the write pointer will not increment past the ‘marked’ location, preventing overwrites of Retransmit data.

6. A transition in the PAE flag may occur one RCLK cycle earlier than shown, (on cycle 2).

IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync



 72-BIT FIFO



16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72

SCLK

SCKHtSCKL

SCLK

SENS

SENH

SEN

LDS

SDS

BIT 1

EMPTY OFFSET

BIT X

(1)

BIT 1

NOTE:

1. X = 14 for the IDT72T7285, X = 15 for the IDT72T7295, X = 16 for the IDT72T72105, X = 17 for the IDT72T72115.

Figure 20. Serial Loading of Programmable Flag Registers (IDT Standard and FWFT Modes)

CLK

CLKH

CLKL

WCLK

LDS

LDH

ENS

ENH

WEN

- D

OFFSET

NOTE:

1. This timing diagram illustrates programming with an input bus width of 72 bits.

PAE

PAF

OFFSET

Figure 21. Parallel Loading of Programmable Flag Registers (IDT Standard and FWFT Modes)

FULL OFFSET

LDH

ENH

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

ENH

LDH

SDH

(1)

BIT X

5994 drw25

5994 drw26

CLK

CLKH

CLKL

RCLK

LDS

LDH

LDS

LDH

LDS

LDH

ENS

ENH

ENS

ENH

ENS

ENH

REN

- Q

DATA IN OUTPUT REGISTER PAE OFFSET VALUE PAF OFFSET VALUE

PAE OFFSET

5994 drw27

NOTES:

1. OE = LOW; RCS = LOW.

2. The timing diagram illustrates reading of offset registers with an output bus width of 72 bits.

3. The offset registers cannot be read on consecutive RCLK cycles. The read must be disabled (REN = HIGH) for a minimum of one RCLK cycle in between register accesses.

Figure 22. Parallel Read of Programmable Flag Registers (IDT Standard and FWFT Modes)

IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync 16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72

CLKL



 72-BIT FIFO



COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

WCLK

ENS

ENH

WEN

PAFS

PAF

D - (m +1) words in FIFO

(2)

D - m words in FIFO

(3)

SKEW2

(2)

RCLK

ENS

ENH

REN

NOTES:

1. m = PAF offset.

2. D = maximum FIFO depth. In IDT Standard mode: D = 16,384 for the IDT72T7285, 32,768 for the IDT72T7295, 65,536 for the IDT72T72105 and 131,072 for the IDT72T72115. In FWFT mode: D = 16,385 for the IDT72T7285, 32,769 for the IDT72T7295, 65,537 for the IDT72T72105 and 131,073 for the IDT72T72115. t

SKEW2

is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that PAF will go HIGH (after one WCLK cycle plus t

3. rising edge of RCLK and the rising edge of WCLK is less than t

SKEW2

, then the PAF deassertion time may be delayed one extra WCLK cycle.

4. PAF is asserted and updated on the rising edge of WCLK only.

5. Select this mode by setting PFM HIGH during Master Reset.

Figure 23. Synchronous Programmable Almost-Full Flag Timing (IDT Standard and FWFT Modes)

PAFS

D-(m+1) words

in FIFO

5994 drw28

PAFS

). If the time between the

(2)

CLKH

CLKL

WCLK

ENS

ENH

WEN

PAE

RCLK

REN

n words in FIFO

n + 1 words in FIFO

(2)

(3)

(4)

SKEW2

12 12

PAES

ENS

n + 1 words in FIFO

n + 2 words in FIFO

ENH

(2)

(3)

PAES

n words in FIFO

n + 1 words in FIFO

(2)

5994 drw29

NOTES:

1. n = PAE offset.

2. For IDT Standard mode

3. For FWFT mode.

tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that PAE will go HIGH (after one RCLK cycle plus tPAES). If the time between the

rising edge of WCLK and the rising edge of RCLK is less than t

SKEW2, then the PAE deassertion may be delayed one extra RCLK cycle.

5. PAE is asserted and updated on the rising edge of WCLK only.

6. Select this mode by setting PFM HIGH during Master Reset.

7. RCS = LOW.

Figure 24. Synchronous Programmable Almost-Empty Flag Timing (IDT Standard and FWFT Modes)

(3)

IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync



 72-BIT FIFO



COMMERCIAL AND INDUSTRIAL

16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72

CLKH

CLKL

WCLK

ENS

ENH

WEN

PAFA

PAF

D - (m + 1) words in FIFO

D - m words

in FIFO

PAFA

RCLK

ENS

REN

NOTES:

1. m = PAF offset.

2. D = maximum FIFO Depth. In IDT Standard Mode:

D= 16,384 for the IDT72T7285, 32,768 for the IDT72T7295, 65,536 for the IDT72T72105 and 131,072 for the IDT72T72115.

In FWFT Mode: D= 16,385 for the IDT72T7285, 32,769 for the IDT72T7295, 65,537 for the IDT72T72105 and 131,073 for the IDT72T72115.

3. PAF is asserted to LOW on WCLK transition and reset to HIGH on RCLK transition.

4. Select this mode by setting PFM LOW during Master Reset.

5. RCS = LOW.

TEMPERATURE RANGES

D - (m + 1) words

in FIFO

5994 drw30

Figure 25. Asynchronous Programmable Almost-Full Flag Timing (IDT Standard and FWFT Modes)

ENS

CLKL

CLKH

WCLK

WEN

PAE

n words in FIFO

n + 1 words in FIFO

(2)

(3)

RCLK

REN

NOTES:

1. n = PAE offset.

2. For IDT Standard Mode.

3. For FWFT Mode.

4. PAE is asserted LOW on RCLK transition and reset to HIGH on WCLK transition.

5. Select this mode by setting PFM LOW during Master Reset.

6. RCS = LOW.

ENH

PAEA

n + 1 words in FIFO

n + 2 words in FIFO

ENS

PAEA

(2)

(3)

n words in FIFO

n + 1 words in FIFO

(2)

(3)

5994 drw31

Figure 26. Asynchronous Programmable Almost-Empty Flag Timing (IDT Standard and FWFT Modes)

IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync 16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72

CLKH



 72-BIT FIFO



CLKL

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

WCLK

ENS

ENH

WEN

D/2 words in FIFO

D-1

[

+ 1] words in FIFO

(1)

(2)

D/2 + 1 words in FIFO

D-1

[

+ 2] words in FIFO

(1)

(2)

D/2 words in FIFO

D-1

[

+ 1] words in FIFO

(1)

(2)

RCLK

ENS

REN

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NOTES:

1. In IDT Standard mode: D = maximum FIFO depth. D = 16,384 for the IDT72T7285, 32,768 for the IDT72T7295, 65,536 for the IDT72T72105 and 131,072 for the IDT72T72115.

2. In FWFT mode: D = maximum FIFO depth. D = 16,385 for the IDT72T7285, 32,769 for the IDT72T7295, 65,537 for the IDT72T72105 and 131,073 for the IDT72T72115.

3. RCS = LOW.

Figure 27. Half-Full Flag Timing (IDT Standard and FWFT Modes)

IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync 16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72

5994 drw33



 72-BIT FIFO



COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

ENS

ENH

ENS

CLKEN

REF

Last Word, W

D-1

D-2

OLZ

D-3

RCLK

ERCLK

REN

ENH

ENS

RCS

CLKEN

EREN

Figure 28. Echo Read Clock & Read Enable Operation (IDT Standard Mode Only)

OHZ

D-3

OLZ

D-4

NOTES:

1. The EREN output is an “ANDed” function of RCS and REN and will follow these inputs provided that the FIFO is not empty. If the FIFO is empty, EREN will go HIGH, thus preventing any reads.

2. The EREN output is synchronous to RCLK.

IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync 16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72

WCLK

WEN

D0 - Dn

RCLK

ERCLK

REN

RCS

EREN

O/P

Reg.

HIGH-Z

ENS

n+1

ERCLK

tDHt

SKEW1

Wn Last Word

n+2

ENH

n+3

CLKEN

REF



 72-BIT FIFO



CLKEN

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

ENS

RCSLZ

n+1

CLKEN

n+2

ENH

CLKEN

n+3

REF

n+3

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NOTE:

1. The O/P Register is the internal output register. Its contents are available on the Qn output bus only when RCS and OE are both active, LOW, that is the bus is not in HighImpedance state.

2. OE is LOW.

Cycle:

a&b. At this point the FIFO is empty, OR is HIGH.

RCS and REN are both disabled, the output bus is High-Impedance.

c. Word Wn+1 falls through to the output register, OR goes active, LOW.

RCS is HIGH, therefore the Qn outputs are High-Impedance. EREN goes LOW to indicate that a new word has been placed on the output register.

d. EREN goes HIGH, no new word has been placed on the output register on this cycle. e. No Operation. f. RCS is LOW on this cycle, therefore the Qn outputs go to Low-Impedance and the contents of the output register (Wn+1) are made available.

NOTE: In FWFT mode is important to take RCS active LOW at least one cycle ahead of REN, this ensures the word (Wn+1) currently in the output register is made

available for at least one cycle.

g. REN goes active LOW, this reads out the second word, Wn+2.

EREN goes active LOW to indicate a new word has been placed into the output register.

h. Word Wn+3 is read out, EREN remains active, LOW indicating a new word has been read out.

NOTE: Wn+3 is the last word in the FIFO.

i. This is the next enabled read after the last word, Wn+3 has been read out. OR flag goes HIGH and EREN goes HIGH to indicate that there is no new word available.

Figure 29. Echo RCLK and Echo

REN

Operation (FWFT Mode Only)

IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync 16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72

RCLK

REN

FFA

NOTE:

1. OE = LOW, WEN = LOW and RCS = LOW.

Figure 30. Asynchronous Write, Synchronous Read, Full Flag Operation (IDT Standard Mode)



 72-BIT FIFO



ENS

CYC

ENH

FFA

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

FFA

CYH

D+1

5994 drw35

RCLK

REN

Last Word

SKEW

CYH

NOTE:

1. OE = LOW, WEN = LOW and RCS = LOW.

Figure 31. Asynchronous Write, Synchronous Read, Empty Flag Operation (IDT Standard Mode)

CYC

CYL

REF

ENS

ENH

REF

5994 drw36

IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync 16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72

No Write

WCLK

WEN



 72-BIT FIFO



COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

tSKEW

tCYL tCYH

tCYC

tAA

Last Word

NOTE:

1. OE = LOW, RCS = LOW and REN = LOW.

2. Asynchronous Read is available in IDT Standard Mode only.

Figure 32. Synchronous Write, Asynchronous Read, Full Flag Operation (IDT Standard Mode)

tAA

WX+1

DF+1

tWFFtWFF

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WCLK

ENS

ENH

WEN

EFA

RPE

Last Word in Output Register

NOTE:

1. OE = LOW, REN = LOW and RCS = LOW.

2. Asynchronous Read is available in IDT Standard Mode only.

Figure 33. Synchronous Write, Asynchronous Read, Empty Flag Operation (IDT Standard Mode)

EFA

CYH

5994 drw38

IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync 16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72

CYH

CYC

CYL

Last Word in O/P Register

EFA

RPE

NOTES:

1. OE = LOW, WEN = LOW, REN = LOW and RCS = LOW

2. Asynchronous Read is available in IDT Standard Mode only.

Figure 34. Asynchronous Write, Asynchronous Read, Empty Flag Operation (IDT Standard Mode)



 72-BIT FIFO



COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

EFA

5994 drw39

CYC

CYH

CYL

FFA

x+1

NOTES:

1. OE = LOW, WEN = LOW, REN = LOW and RCS = LOW.

2. Asynchronous Read is available in IDT Standard Mode only.

Figure 35. Asynchronous Write, Asynchronous Read, Full Flag Operation (IDT Standard Mode)

CYC

CYH

x+2

CYL

y+1

FFA

5994 drw40

IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync 16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72



 72-BIT FIFO



COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

OPTIONAL CONFIGURATIONS

WIDTH EXPANSION CONFIGURATION

Word width may be increased simply by connecting together the control signals of multiple devices. Status flags can be detected from any one device. The exceptions are the EF and FF functions in IDT Standard mode and the IR and OR functions in FWFT mode. Because of variations in skew between RCLK and WCLK, it is possible for EF/FF deassertion and IR/OR assertion to vary by one cycle between FIFOs. In IDT Standard mode, such problems can be

SERIAL CLOCK (SCLK)

PARTIAL RESET (PRS)

MASTER RESET (MRS)

FIRST WORD FALL THROUGH/

SERIAL INPUT (FWFT/SI)

GATE

DATA IN

(1)

RETRANSMIT (RT)

m + n

FULL FLAG/INPUT READY (FF/IR)

FULL FLAG/INPUT READY (FF/IR) #2

D0 - D

WRITE CLOCK (WCLK)

WRITE ENABLE (WEN)

PROGRAMMABLE (PAF)

HALF-FULL FLAG (HF)

LOAD (LD)

IDT 72T7285 72T7295

72T72105 72T72115

FIFO

m+1

avoided by creating composite flags, that is, ANDing EF of every FIFO, and separately ANDing FF of every FIFO. In FWFT mode, composite flags can be created by ORing OR of every FIFO, and separately ORing IR of every FIFO.

Figure 36 demonstrates a width expansion using two IDT72T7285/

72T7295/72T72105/72T72115 devices. D

0 - D71 from each device form a

144-bit wide input bus and Q0-Q71 from each device form a 144-bit wide output bus. Any word width can be attained by adding additional IDT72T7285/ 72T7295/72T72105/72T72115 devices.

- D

READ CLOCK (RCLK) READ CHIP SELECT (RCS)

READ ENABLE (REN)

IDT 72T7285 72T7295

72T72105 72T72115

FIFO

Q0 - Qm

OUTPUT ENABLE (OE)

PROGRAMMABLE (PAE)

EMPTY FLAG/OUTPUT READY (EF/OR) #1

EMPTY FLAG/OUTPUT READY (EF/OR) #2

m+1 - Qn

m + n

DATA OUT

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GATE

(1)

NOTES:

1. Use an AND gate in IDT Standard mode, an OR gate in FWFT mode.

2. Do not connect any output control signals directly together.

3. FIFO #1 and FIFO #2 must be the same depth, but may be different word widths.

Figure 36. Block Diagram of 16,384 x 144, 32,768 x 144, 65,536 x 144 and 131,072 x 144 Width Expansion

IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync 16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72

FWFT/SI

TRANSFER CLOCK



 72-BIT FIFO



COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

WRITE CLOCK

WRITE ENABLE

INPUT READY

DATA IN

n n

WCLK

WEN

FWFT/SI FWFT/SI

IDT 72T7285 72T7295

72T72105 72T72115

RCLK

REN RCS

GND

Figure 37. Block Diagram of 32,768 x 72, 65,536 x 72, 131,072 x 72 and 262,144 x 72 Depth Expansion

DEPTH EXPANSION CONFIGURATION (FWFT MODE ONLY)

The IDT72T7285 can easily be adapted to applications requiring depths greater than 16,384, 32,768 for the IDT72T7295, 65,536 for the IDT72T72105 and 131,072 for the IDT72T72115 with an 72-bit bus width. In FWFT mode, the FIFOs can be connected in series (the data outputs of one FIFO connected to the data inputs of the next) with no external logic necessary. The resulting configuration provides a total depth equivalent to the sum of the depths associated with each single FIFO. Figure 37 shows a depth expansion using two IDT72T7285/72T7295/72T72105/72T72115 devices.

Care should be taken to select FWFT mode during Master Reset for all FIFOs in the depth expansion configuration. The first word written to an empty configuration will pass from one FIFO to the next ("ripple down") until it finally appears at the outputs of the last FIFO in the chain – no read operation is necessary but the RCLK of each FIFO must be free-running. Each time the data word appears at the outputs of one FIFO, that device's OR line goes LOW, enabling a write to the next FIFO in line.

For an empty expansion configuration, the amount of time it takes for OR of the last FIFO in the chain to go LOW (i.e. valid data to appear on the last FIFO's outputs) after a word has been written to the first FIFO is the sum of the delays for each individual FIFO:

(N – 1)*(4*transfer clock) + 3*TRCLK

where N is the number of FIFOs in the expansion and TRCLK is the RCLK period. Note that extra cycles should be added for the possibility that the tSKEW1

WCLK

WEN

IDT 72T7285 72T7295

72T72105 72T72115

RCLK

RCS

REN

READ CLOCK

READ CHIP SELECT

READ ENABLE

OUTPUT READY

OUTPUT ENABLE

DATA OUT

5994 drw42

specification is not met between WCLK and transfer clock, or RCLK and transfer clock, for the OR flag.

The "ripple down" delay is only noticeable for the first word written to an empty depth expansion configuration. There will be no delay evident for subsequent words written to the configuration.

The first free location created by reading from a full depth expansion configuration will "bubble up" from the last FIFO to the previous one until it finally moves into the first FIFO of the chain. Each time a free location is created in one FIFO of the chain, that FIFO's IR line goes LOW, enabling the preceding FIFO to write a word to fill it.

For a full expansion configuration, the amount of time it takes for IR of the first FIFO in the chain to go LOW after a word has been read from the last FIFO is the sum of the delays for each individual FIFO:

(N – 1)*(3*transfer clock) + 2 TWCLK

where N is the number of FIFOs in the expansion and TWCLK is the WCLK period. Note that extra cycles should be added for the possibility that the tSKEW1 specification is not met between RCLK and transfer clock, or WCLK and transfer clock, for the IR flag.

The Transfer Clock line should be tied to either WCLK or RCLK, whichever is faster. Both these actions result in data moving, as quickly as possible, to the end of the chain and free locations to the beginning of the chain.

ORDERING INFORMATION

IDT XXXXX

Device TypeXPowerXXSpeed

Package

Process /

Temperature

Range

BLANK

(1)

Commercial (0°C to +70°C) Industrial (-40°C to +85°C)

4-4 5 6-7 10

72T7285 16,384 x 72  2.5V TeraSync FIFO 72T7295 32,768 x 72  2.5V TeraSync FIFO 72T72105 65,536 x 72  2.5V TeraSync FIFO 72T72115 131,072 x 72  2.5V TeraSync FIFO

NOTE:

1. Industrial temperature range product for 5ns speed grade is available as a standard device. All other speed grades are available by special order.

Plastic Ball Grid Array (PBGA, BB324-1)

Commercial Only Commercial and Industrial Commercial Only Commercial Only

Low Power

Clock Cycle Time (t Speed in Nanoseconds

5994 drw43

CLK

)

DATASHEET DOCUMENT HISTORY

05/25/2001 pgs. 1, and 8. 07/19/2001 pgs. 1, and 8. 10/22/2001 pgs. 1-52. 11/19/2001 pgs. 1, 9, 12, 39, and 40. 11/29/2001 pgs. 1, 39, and 40. 01/15/2002 pg. 41. 03/04/2002 pgs. 9, and 27. 06/05/2002 pgs. 9, and 13. 06/10/2002 pg. 9. 02/11/2003 pgs. 7, 8, and 30. 03/03/2003 pgs. 1, 9-11, 28, and 30-31. 09/02/2003 pgs. 6, 15, and 23.

CORPORATE HEADQUARTERS for SALES: for Tech Support:

2975 Stender Way 800-345-7015 or 408-727-6116 408-330-1753 Santa Clara, CA 95054 fax: 408-492-8674 email: F IFO help @idt .com

www.idt.com

Datasheet IDT72T7285, IDT72T7295, IDT72T72105, IDT72T72115 Datasheet (IDT)

Specifications and Main Features

Frequently Asked Questions

User Manual