Datasheet IDT72200L12TC, IDT72200L12TP, IDT72200L15TC, IDT72200L15TP, IDT72200L20TC Datasheet (Integrated Device Technology Inc)

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Integrated Device Technology, Inc.

CMOS SyncFIFO 64 x 8, 256 x 8, 512 x 8, 1024 x 8, 2048 x 8 and 4096 x 8

IDT72420 IDT72200 IDT72210 IDT72220 IDT72230 IDT72240

FEATURES:

• 64 x 8-bit organization (IDT72420)

• 256 x 8-bit organization (IDT72200)

• 512 x 8-bit organization (IDT72210)

• 1024 x 8-bit organization (IDT72220)

• 2048 x 8-bit organization (IDT72230)

• 4096 x 8-bit organization (IDT72240)

• 12 ns read/write cycle time (IDT72420/72200/72210)

• 15 ns read/write cycle time (IDT72220/72230/72240)

• Read and write clocks can be asynchronous or coincidental

• Dual-Ported zero fall-through time architecture

• Empty and Full flags signal FIFO status

• Almost-empty and almost-full flags set to Empty+7 and Full-7, respectively

• Output enable puts output data bus in high-impedance state

• Produced with advanced submicron CMOS technology

• Available in 28-pin 300 mil plastic DIP and 300 mil ceramic DIP

• For surface mount product please see the IDT72421/ 72201/72211/72221/72231/72241 data sheet

• Military product compliant to MIL-STD-883, Class B

• Industrial temperature range (-40 available, tested to military electrical specifications

C to +85OC) is

DESCRIPTION:

The IDT72420/72200/72210/72220/72230/72240 SyncFIFO are very high-speed, low-power First-In, FirstOut (FIFO) memories with clocked read and write controls. The IDT72420/72200/72210/72220/72230/72240 have a 64, 256, 512, 1024, 2048, and 4096 x 8-bit memory array, respectively. These FIFOs are applicable for a wide variety of data buffering needs, such as graphics, Local Area Networks (LANs), and interprocessor communication.

These FIFOs have 8-bit input and output ports. The input port is controlled by a free-running clock (WCLK), and a write enable pin (WEN). Data is written into the Synchronous FIFO on every clock when WEN is asserted. The output port is controlled by another clock pin (RCLK) and a read enable pin (REN). The read clock can be tied to the write clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation. An output enable pin (OE) is provided on the read port for three-state control of the output.

These Synchronous FIFOs have two end-point flags, Empty (EF) and Full (FF). Two partial flags, Almost-Empty (AE) and Almost-Full (AF), are provided for improved system control. The partial ( AE) flags are set to Empty+7 and Full-7 for AE and AF respectively.

The IDT72420/72200/72210/72220/72230/72240 are fabricated using IDT’s high-speed submicron CMOS technology. Military grade product is manufactured in compliance with the latest revision of MIL-STD-883, Class B.

FUNCTIONAL BLOCK DIAGRAM

WCLK

WEN

•

WRITE CONTROL

LOGIC

WRITE POINTER

RESET LOGIC

The IDT logo is a registered trademark and SyncFIFO is a trademark of Integrated Device Technology, Inc.

D0 - D7

INPUT REGISTER

•

RAM ARRAY

64 x 8 256 x 8 512 x 8

•

OUTPUT REGISTER

Q0 - Q7

FLAG

LOGIC

READ POINTER

READ CONTROL

LOGIC

•

RCLK

REN

EF AE AF FF

2680 drw 01

MILITARY AND COMMERCIAL TEMPERATURE RANGES NOVEMBER 1996

1996 Integrated Device Technology, Inc. DSC-2680/6

For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.

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IDT72420/72200/72210/72220/72230/72240 CMOS SyncFIFO 64 X 8, 256 X 8, 512 X 8, 1024 X 8, 2048 X 8 and 4096 X 8 MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN CONFIGURATION

D4 D3 D2 D1 D0

AF AE

GND

RCLK

REN

1 2 3 4 5 6 7 8 9 10 11 12 13 14

P28-2 C28-1

DIP TOP

VIEW

28 27 26 25 24 23 22 21 20 19 18 17 16 15

D5 D6 D7

RS WEN

WCLK VCC Q7 Q6 Q5 Q4 Q3 Q2 Q1

2680 drw 02

PIN DESCRIPTIONS

Symbol Name I/O Description

0 - D7 Data Inputs I Data inputs for a 8-bit bus.

WCLK Write Clock I Data is written into the FIFO on a LOW-to-HIGH transition of WCLK when

WEN

0 - Q7 Data Outputs O Data outputs for a 8-bit bus.

Q RCLK Read Clock I Data is read from the FIFO on a LOW-to-HIGH transition of RCLK when

REN

CC Power One +5 volt power supply pin.

V GND Ground One 0 volt ground pin.

Reset I When RS is set LOW, internal read and write pointers are set to the first location of the RAM

array, FF and AF go HIGH, and AE and EF go LOW. A reset is required before an initial WRITE after power-up.

Write Enable I When

WEN

is LOW, data is written into the FIFO on every LOW-to-HIGH transition of WCLK.

Data will not be written into the FIFO if the FF is LOW.

Read Enable I When

REN

is LOW, data is read from the FIFO on every LOW-to-HIGH transition of RCLK.

Data will not be read from the FIFO if the EF is LOW.

Output Enable I When OE is LOW, the data output bus is active. If OE is HIGH, the output data bus will be in a

high-impedance state.

Empty Flag O When EF is LOW, the FIFO is empty and further data reads from the output are inhibited. When

is HIGH, the FIFO is not empty. EF is synchronized to RCLK.

Almost-Empty O When AE is LOW, the FIFO is almost empty based on the offset Empty+7. AE is synchronized Flag to RCLK.

Almost-Full Flag O When AF is LOW, the FIFO is almost full based on the offset Full-7. AF is synchronized to

WCLK.

Full Flag O When FF is LOW, the FIFO is full and further data writes into the input are inhibited. When FF is

HIGH, the FIFO is not full. FF is synchronized to WCLK.

WEN

REN

is asserted.

2680 tbl 01

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IDT72420/72200/72210/72220/72230/72240 CMOS SyncFIFO 64 X 8, 256 X 8, 512 X 8, 1024 X 8, 2048 X 8 and 4096 X 8 MILITARY AND COMMERCIAL TEMPERATURE RANGES

ABSOLUTE MAXIMUM RATINGS

(1)

Symbol Rating Commercial Military Unit

TERM Terminal Voltage –0.5 to + 7.0 –0.5 to + 7.0 V

with Respect to GND

A Operating 0 to + 70 –55 to + 125 °C

Temperature

BIAS Temperature –55 to + 125 –65 to + 135 °C

Under Bias

STG Storage –55 to + 125 –65 to + 135 °C

Temperature

OUT DC Output 50 50 mA

Current

NOTE:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

2680 tbl 02

RECOMMENDED OPERATING CONDITIONS

Symbol Parameter Min. Typ. Max. Unit

CCM Military Supply Voltage 4.5 5.0 5.5 V

CCC Commercial Supply 4.5 5.0 5.5 V

Voltage

GND Supply Voltage 0 0 0 V

IH Input High Voltage 2.0 — — V

Commercial

IH Input High Voltage 2.2 — — V

Military

IL Input Low Voltage — — 0.8 V

Commercial & Military

CAPACITANCE (TA = +25°C, f = 1.0 MHz)

Symbol Parameter Conditions Max. Unit

(2)

IN Input Capacitance V IN = 0V 10 pF

(1, 2)

OUT Output Capacitance VOUT = 0V 10 pF

NOTES:

1. With output deselected. (OE = HIGH)

2. Characterized values, not currently tested.

DC ELECTRICAL CHARACTERISTICS

(Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C; Military: VCC = 5V ± 10%, TA = –55°C to +125 °C)

IDT72420 IDT72420 IDT72200 IDT72200 IDT72210 IDT72210

CLK = 12, 15, 20, 25, 35, 50 ns tCLK = 20, 25,35, 50 ns

Symbol Parameter Min. Typ. Max. Min. Typ. Max. Units

(1)

Input Leakage Current (any input) –1 — 1 –10 — 10 µA

(2)

Output Leakage Current –10 — 10 –10 — 10 µA

Commercial Military

2680 tbl 03

2680 tbl 04

OH Output Logic “1” Voltage, IOH = –2 mA 2.4 — — 2.4 — — V

V V

OL Output Logic “0” Voltage, IOL = 8 mA — — 0.4 — — 0.4 V

(3)

CC1

Active Power Supply Current — — 80 — — 100 mA

IDT72220 IDT72220 IDT72230 IDT72230 IDT72240 IDT72240

Commercial Military

CLK = 15, 20, 25, 35, 50 ns tCLK = 25, 35, 50 ns

Symbol Parameter Min. Typ. Max. Min. Typ. Max. Units

(1)

I I

OH Output Logic “1” Voltage, IOH = –2 mA 2.4 — — 2.4 — — V

V V

OL Output Logic “0” Voltage, IOL = 8 mA — — 0.4 — — 0.4 V

CC1

NOTES:

1. Measurements with 0.4 ≤ V

2.OE ≥ V 3 & 4. Measurements are made with outputs unloaded. Tested at f

Input Leakage Current (any input) –1 — 1 –10 — 10 µA

(2)

Output Leakage Current –10 — 10 –10 — 10 µA

(4)

Active Power Supply Current — — 80 — — 100 mA

IH, 0.4 ≤ VOUT ≤ VCC.

(3) Typical I (4) Typical I

CLK = 1 / tCLK

f CL = external capacitive load (30 pF typical)

CC1 = 30 + (fCLK*0.5/MHz) + (fCLK*CL*0.02/MHz-pF) mA CC1 = 32 + (fCLK*0.6/MHz) + (fCLK*CL*0.02/MHz-pF) mA

IN ≤ VCC.

CLK = 20 MHZ.

2680 tbl 05

2680 tbl 06

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IDT72420/72200/72210/72220/72230/72240 CMOS SyncFIFO 64 X 8, 256 X 8, 512 X 8, 1024 X 8, 2048 X 8 and 4096 X 8 MILITARY AND COMMERCIAL TEMPERATURE RANGES

AC ELECTRICAL CHARACTERISTICS

(Commercial: VCC = 5V ± 10%, TA = 0°C to + 70°C; Military: VCC = 5V ± 10%, TA = –55°C to +125°C)

Commercial Comm. & Mil. Comm. Comm/Mil

72200L12 72200L15 72200L20 72200L25 72200L35 72200L50 72210L12 72210L15 72210L20 72210L25 72210L35 72210L50 72420L12 72420L15 72420L20 72420L25 72420L35 72420L50

Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min.Max. Unit

S Clock Cycle Frequency — 83.3 — 66.7 — 50 — 40 — 28.6 — 20 MHz

f t

A Data Access Time 2 8 2 10 2 12 3 15 3 20 3 25 ns

CLK Clock Cycle Time 12 — 15 — 20 — 25 — 35 — 50 — ns

CLKH Clock High Time 5 — 6 — 8 — 10 — 14 — 20 — ns

CLKL Clock Low Time 5 — 6 — 8 — 10 — 14 — 20 — ns

DS Data Set-up Time 3 — 4 — 5 — 6 — 8 — 10 — ns

DH Data Hold Time 0.5 — 1 — 1 — 1 — 2 — 2 — ns

ENS Enable Set-up Time 3 — 4 — 5 — 6 — 8 — 10 — ns

ENH Enable Hold Time 0.5 — 1 — 1 — 1 — 2 — 2 — ns

RS Reset Pulse Width

RSS Reset Set-up Time 12 — 15 — 20 — 25 — 35 — 50 — ns

RSR Reset Recovery Time 12 — 15 — 20 — 25 — 35 — 50 — ns

RSF Reset to Flag and Output Time — 12 — 15 — 20 — 25 — 35 — 50 ns

OLZ Output Enable to Output in Low-Z

OE Output Enable to Output Valid 3 7 3 8 3 10 3 13 3 15 3 28 ns

OHZ Output Enable to Output in High-Z

WFF Write Clock to Full Flag — 8 — 10 — 12 — 15 — 20 — 30 ns

REF Read Clock to Empty Flag — 8 — 10 — 12 — 15 — 20 — 30 ns

AF Write Clock to Almost-Full Flag — 8 — 10 — 12 — 15 — 20 — 30 ns

AE Read Clock to Almost-Empty Flag — 8 — 10 — 12 — 15 — 20 — 30 ns

SKEW1 Skew time between Read Clock & 5 — 6 — 8 — 10 — 12 — 15 — ns

Write Clock for Empty Flag & Full Flag

SKEW2 Skew time between Read Clock & 22 — 28 — 35 — 40 — 42 — 45 — ns

Write Clock for Almost-Empty Flag & Almost-Full Flag

NOTES: 2680 tbl 07

1. Pulse widths less than minimum values are not allowed.

2. Values guaranteed by design, not currently tested.

(1)

(2)

12 — 15 — 20 — 25 — 35 — 50 — ns

0— 0— 0 — 0— 0— 0— ns

3 7 3 8 3 10 3 13 3 15 3 28 ns

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IDT72420/72200/72210/72220/72230/72240 CMOS SyncFIFO 64 X 8, 256 X 8, 512 X 8, 1024 X 8, 2048 X 8 and 4096 X 8 MILITARY AND COMMERCIAL TEMPERATURE RANGES

AC ELECTRICAL CHARACTERISTICS

(Commercial: VCC = 5V ± 10%, TA = 0°C to + 70°C; Military: VCC = 5V ± 10%, TA = –55°C to +125°C)

Commercial Commercial & Military Comm. Comm./Mil. 72220L12 72220L15 72220L20 72220L25 72220L35 72220L50 72230L12 72230L15 72230L20 72230L25 72230L35 72230L50

Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit

fS Clock Cycle Frequency — 83.3 — 66.7 — 50 — 40 — 28.6 — 20 MHz tA Data Access Time 2 8 2 10 2 12 3 15 3 20 3 25 ns tCLK Clock Cycle Time 12 — 15 — 20 — 25 — 35 — 50 — ns tCLKH Clock High Time 5 — 6 — 8 — 10 — 1 4 — 20 — ns tCLKL Clock Low Time 5 — 6 — 8 — 10 — 14 — 20 — ns tDS Data Set-up Time 3 — 4 — 5 — 6 — 8 — 10 — ns tDH Data Hold Time .5 — 1 — 1 — 1 — 2 — 2 — ns tENS Enable Set-up Time 3 — 4 — 5 — 6 — 8 — 10 — ns tENH Enable Hold Time .5 — 1 — 1 — 1 — 2 — 2 — ns tRS Reset Pulse Width tRSS Reset Set-up Time 12 — 15 — 20 — 25 — 35 — 50 — ns tRSR Reset Recovery Time 12 — 15 — 20 — 25 — 35 — 50 — ns tRSF Reset to Flag and Output Time — 12 — 15 — 20 — 25 — 35 — 50 ns tOLZ Output Enable to Output in Low-Z tOE Output Enable to Output Valid 3 7 3 8 3 10 3 13 3 15 3 23 ns tOHZ Output Enable to Output in High-Z tWFF Write Clock to Full Flag — 8 — 10 — 12 — 15 — 20 — 30 ns tREF Read Clock to Empty Flag — 8 — 10 — 12 — 15 — 20 — 30 ns tAF Write Clock to Almost-Full Flag — 8 — 10 — 12 — 15 — 20 — 3 0 ns tAE Read Clock to Almost-Empty Flag — 8 — 10 — 12 — 15 — 20 — 30 ns tSKEW1 Skew time between Read Clock 5 — 6 — 8 — 10 — 12 — 15 — ns

& Write Clock for Empty Flag & Full Flag

tSKEW2 Skew time between Read Clock & 22 — 28 — 35 — 40 — 42 — 45 — ns

Write Clock for Almost-Empty Flag & Almost-Full Flag

NOTES:

1. Pulse widths less than minimum values are not allowed.

2. Values guaranteed by design, not currently tested.

(1)

72240L12 72240L15 72240L20 72240L25 72240L35 72240L50

12 — 15 — 20 — 25 — 35 — 50 — ns

(2)

0—0—0—0—0—0— ns

(2)

3738310313315323ns

2680 tbl 08

AC TEST CONDITIONS

Input Pulse Levels GND to 3.0V Input Rise/Fall Times 3ns Input Timing Reference Levels 1.5V Output Reference Levels 1.5V Output Load See Figure 1

1.1K

D.U.T.

30pF*

2680 drw 03

2680 tbl 09

680

Ω

or equivalent circuit

Figure 1. Output Load

*Includes jig and scope capacitances.

5.12 5

Ω

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IDT72420/72200/72210/72220/72230/72240 CMOS SyncFIFO 64 X 8, 256 X 8, 512 X 8, 1024 X 8, 2048 X 8 and 4096 X 8 MILITARY AND COMMERCIAL TEMPERATURE RANGES

SIGNAL DESCRIPTIONS

INPUTS: Data In (D

CONTROLS: Reset (

(RS) input is taken to a LOW state. During reset, both internal read and write pointers are set to the first location. A reset is required after power up before a write operation can take place. The Full Flag (FF) and Almost Full Flag (AF) will be reset to HIGH after t Flag (AE) will be reset to LOW after tRSF. During reset, the output register is initialized to all zeros.

Write Clock (WCLK) — A write cycle is initiated on the LOWto-HIGH transition of the write clock (WCLK). Data set-up and hold times must be met in respect to the LOW-to-HIGH transition of the write clock (WCLK). The Full Flag (FF) and Almost Full Flag (AF) are synchronized with respect to the LOW-to-HIGH transition of the write clock (WCLK).

The write and read clocks can be asynchronous or coinci-

dent.

Write Enable (

data can be loaded into the input register and RAM array on the LOW-to-HIGH transition of every write clock (WCLK). Data is stored in the RAM array sequentially and independently of any on-going read operation.

When Write Enable ( the previous data and no new data is allowed to be loaded into the register.

To prevent data overflow, the Full Flag (FF) will go LOW, inhibiting further write operations. Upon the completion of a valid read cycle, the Full Flag (FF) will go HIGH after t allowing a valid write to begin. Write Enable ( when the FIFO is full.

Read Clock (RCLK) — Data can be read on the outputs on the LOW-to-HIGH transition of the read clock (RCLK). The Empty Flag (EF) and Almost-Empty Flag (AE) are synchronized with respect to the LOW-to-HIGH transition of the read clock (RCLK).

The write and read clocks can be asynchronous or coincident.

Read Enable (

data is read from the RAM array to the output register on the LOW-to-HIGH transition of the read clock (RCLK).

0–D7) — Data inputs for 8-bit wide data.

RSRS) — Reset is accomplished whenever the Reset

RSF. The Empty Flag (

WEN

) — When Write Enable (

WEN

) is HIGH, the input register holds

REN

) — When Read Enable (

REN

) and Almost Empty

WEN

) is LOW,

WEN

) is ignored

REN

) is LOW,

WFF,

When Read Enable (

REN

) is HIGH, the output register holds the previous data and no new data is allowed to be loaded into the register.

When all the data has been read from the FIFO, the Empty Flag (EF) will go LOW, inhibiting further read operations. Once a valid write operation has been accomplished, the Empty Flag (EF) will go HIGH after tREF and a valid read can begin. Read Enable (

Output Enable (

REN

) is ignored when the FIFO is empty.

OEOE) — When Output Enable (OE) is enabled

(LOW), the parallel output buffers receive data from the output register. When Output Enable (OE) is disabled (HIGH), the Q output data bus is in a high-impedance state.

OUTPUTS: Full Flag (

FFFF) — The Full Flag (FF) will go LOW, inhibiting

further write operation, when the device is full. If no reads are performed after Reset (RS), the Full Flag (FF) will go LOW after 64 writes for the IDT72420, 256 writes for the IDT72200, 512 writes for the IDT72210, 1024 writes for the IDT72220, 2048 writes for the IDT72230, and 4096 writes for the IDT72240.

The Full Flag (FF) is synchronized with respect to the LOWto-HIGH transition of the write clock (WCLK).

Empty Flag (

EFEF) — The Empty Flag (EF) will go LOW,

inhibiting further read operations, when the read pointer is equal to the write pointer, indicating the device is empty.

The Empty Flag (EF) is synchronized with respect to the LOW-to-HIGH transition of the read clock (RCLK).

Almost Full Flag (

AFAF) — The Almost Full Flag (AF) will go

LOW when the FIFO reaches the Almost-Full condition. If no reads are performed after Reset (RS), the Almost Full Flag (AF) will go LOW after 57 writes for the IDT72420, 249 writes for the IDT72200, 505 writes for the IDT72210, 1017 writes for the IDT72220, 2041 writes for the IDT72230 and 4089 writes for the IDT72240.

The Almost Full Flag (AF) is synchronized with respect to the LOW-to-HIGH transition of the write clock (WCLK).

Almost Empty Flag (

AEAE) — The Almost Empty Flag (AE) will

go LOW when the FIFO reaches the Almost-Empty condition. If no reads are performed after Reset (RS), the Almost Empty Flag (AE) will go HIGH after 8 writes for the IDT72420, IDT72200, IDT72210, IDT72220, IDT72230 and IDT72240.

The Almost Empty Flag (AE) is synchronized with respect to the LOW-to-HIGH transition of the read clock (RCLK).

Data Outputs (Q

0–Q7) — Data outputs for a 8-bit wide data.

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IDT72420/72200/72210/72220/72230/72240 CMOS SyncFIFO 64 X 8, 256 X 8, 512 X 8, 1024 X 8, 2048 X 8 and 4096 X 8 MILITARY AND COMMERCIAL TEMPERATURE RANGES

TABLE 1: STATUS FLAGS

Number of Words in FIFO

IDT72420 IDT72200 IDT72210 IDT72220 IDT72230 IDT72240

000000HHLL

1 to 7 1 to 7 1 to 7 1 to 7 1 to 7 1 to 7 H H L H

8 to 56 8 to 248 8 to 504 8 to 1016 8 to 2040 8 to 4088 H H H H

57 to 63 249 to 255 505 to 511 1017 to 1023 2041 to 2047 4089 to 4095 H L H H

64 256 512 1024 2048 4096 L L H H

tRS

2680 tbl 10

tRSS

REN

WEN

tRSF

EF, AE

tRSF

FF, AF

tRSF

Q0 - Q7

NOTE:

1. After reset, the outputs will be LOW if OE = 0 and tri-state if OE = 1.

2. The clocks (RCLK, WCLK) can be free-running during reset.

tRSR

tRSRtRSS

= 1

= 0

(1)

2680 drw 04

Figure 2. Reset Timing

5.12 7

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IDT72420/72200/72210/72220/72230/72240 CMOS SyncFIFO 64 X 8, 256 X 8, 512 X 8, 1024 X 8, 2048 X 8 and 4096 X 8 MILITARY AND COMMERCIAL TEMPERATURE RANGES

tCLK

tCLKH tCLKL

WCLK

D0 - D7

WEN

RCLK

REN

tDS

DATAIN VALID

tENS

tWFF tWFF

(1)

tSKEW1

tDH

tENH

NO OPERATION

2680 drw 05

NOTE:

SKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge for

1. t the rising edge of RCLK and the rising edge of WCLK is less than t

Figure 3. Write Cycle Timing

SKEW1, then

to change during the curent clock cycle. If the time between

may not change state until the next WCLK edge.

5.12 8

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IDT72420/72200/72210/72220/72230/72240 CMOS SyncFIFO 64 X 8, 256 X 8, 512 X 8, 1024 X 8, 2048 X 8 and 4096 X 8 MILITARY AND COMMERCIAL TEMPERATURE RANGES

tCLK

tCLKH tCLKL

RCLK

REN

Q0 - Q 7

WCLK

tENS

tENH

tREF

tOLZ

tOE

NO OPERATION

tREF

VALID DATA

tSKEW1

(1)

tOHZ

WEN

NOTE:

1. t

SKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge for

the rising edge of WCLK and the rising edge of RCLK is less than t

Figure 4. Read Cycle Timing

SKEW1, then

to change during the curent clock cycle. If the time between

may not change state until the next RCLK edge.

2680 drw 06

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IDT72420/72200/72210/72220/72230/72240 CMOS SyncFIFO 64 X 8, 256 X 8, 512 X 8, 1024 X 8, 2048 X 8 and 4096 X 8 MILITARY AND COMMERCIAL TEMPERATURE RANGES

WCLK

D0 - D7

(first valid write)

D1 D2 D3

tENS

WEN

(1)

tSKEW1

tFRL

RCLK

tREF

REN

0 - Q7

tOLZ

tOE

NOTE:

1. When t

SKEW1 ≥ minimum specification, tFRL maximum = tCLK + tSKEW1

When tSKEW1 < minimum specification, tFRL maximum = 2tCLK + tSKEW1 or tCLK + tSKEW1

The Latency Timing apply only at the Empty Boundry (EF = LOW).

Figure 5. First Data Word Latency Timing

D0 D1

2680 drw 07

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IDT72420/72200/72210/72220/72230/72240 CMOS SyncFIFO 64 X 8, 256 X 8, 512 X 8, 1024 X 8, 2048 X 8 and 4096 X 8 MILITARY AND COMMERCIAL TEMPERATURE RANGES

NO WRITE NO WRITE

WCLK

D0 - D7

tSKEW1

tDS

DATA WRITE

tSKEW1

DATA WRITE

tDS

WEN

RCLK

REN

tENH

tENS

LOW

DATA IN OUTPUT REGISTER

tWFF

tENH

tENS

DATA READQ0 - Q7

NEXT DATA READ

Figure 6. Full Flag Timing

2680 drw 08

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IDT72420/72200/72210/72220/72230/72240 CMOS SyncFIFO 64 X 8, 256 X 8, 512 X 8, 1024 X 8, 2048 X 8 and 4096 X 8 MILITARY AND COMMERCIAL TEMPERATURE RANGES

WCLK

tDS

D0 - D7

WEN

RCLK

REN

tENS

DATA WRITE 1

tENH

SKEW1

LOW

tREF

tFRL

(1)

tREF

tENS

DATA WRITE 2

tENH

SKEW1

tREF

tFRL

(1)

0 - Q7

NOTE:

1. When t

SKEW1 ≥ minimum specification, tFRL maximum = tCLK + tSKEW1

When tSKEW1 < minimum specification, tFRL maximum = 2tCLK + tSKEW1 or tCLK + tSKEW1

The Latency Timing apply only at the Empty Boundry (EF = LOW).

DATA IN OUTPUT REGISTER

Figure 7. Empty Flag Timing

DATA READ

2680 drw 09

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IDT72420/72200/72210/72220/72230/72240 CMOS SyncFIFO 64 X 8, 256 X 8, 512 X 8, 1024 X 8, 2048 X 8 and 4096 X 8 MILITARY AND COMMERCIAL TEMPERATURE RANGES

WCLK

WEN

RCLK

REN

tCLKH

tCLKL

tENS

Full - 8 words in FIFO

tENH

(2)

tAF

Full - 7 words in FIFO

tSKEW2

tENS

(1)

tENH

2680 drw 10

NOTES:

SKEW2 is the minimum time between a rising RCLK edge and a rising WCLK edge for

1. t the rising edge of RCLK and the rising edge of WCLK is less than t

2. If a write is performed on this rising edge of the write clock, there will be Full - 6 words in the FIFO when AF goes LOW.

Figure 8. Almost Full Flag Timing

SKEW2, then

to change during the curent clock cycle. If the time between

may not change state until the next WCLK edge.

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IDT72420/72200/72210/72220/72230/72240 CMOS SyncFIFO 64 X 8, 256 X 8, 512 X 8, 1024 X 8, 2048 X 8 and 4096 X 8 MILITARY AND COMMERCIAL TEMPERATURE RANGES

CLKH

CLKL

WCLK

ENS

ENH

WEN

Empty+8

Empty+7

SKEW2

(1)

RCLK

ENS

ENH

REN

NOTES:

1. t

SKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge for

the rising edge of WCLK and the rising edge of RCLK is less than t

2. If a read is performed on this rising edge of the read clock, there will be Empty - 6 words in the FIFO when AE goes LOW.

Figure 9. Almost Empty Flag Timing

SKEW2, then

to change during the curent clock cycle. If the time between

may not change state until the next RCLK edge.

(2)

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IDT72420/72200/72210/72220/72230/72240 CMOS SyncFIFO 64 X 8, 256 X 8, 512 X 8, 1024 X 8, 2048 X 8 and 4096 X 8 MILITARY AND COMMERCIAL TEMPERATURE RANGES

OPERATING CONFIGURATIONS

SINGLE DEVICE CONFIGURATION - A single IDT72420/

72200/72210/72220/72230/72240 may be used when the

WRITE CLOCK (WCLK) READ CLOCK (RCLK)

WRITE ENABLE (

WEN

)

72420/72200/

DATA IN (D

0-D7) DATA OUT (Q0- Q7)

FULL FLAG (FF)

ALMOST FULL (AF)

Figure 10. Block Diagram of Single 64 x 8/256 x 8/512 x 8/1024 x 8/2048 x 8/4096 x 8 Synchronous FIFO

WIDTH EXPANSION CONFIGURATION - Word width may

be increased simply by connecting the corresponding input control signals of multiple devices. A composite flag should be created for each of the end-point status flags (EF and FF) The partial status flags (AE and AF) can be detected from any one

application requirements are for 64/256/512/1024/2048/4096 words or less. See Figure 10.

RESET (RS)

IDT

READ ENABLE ( OUTPUT ENABLE (OE)

REN

)

72210/ 72220/ 72230/

72240

EMPTY FLAG (EF) ALMOST EMPTY(AE)

device. Figure 11 demonstrates a 16-bit word width by using two IDT72420/72200/72210/72220/72230/72240s. Any word width can be attained by adding additional IDT72420/72200/ 72210/72220/72230/72240s.

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DATA IN (D)

WRITE CLOCK (WCLK)

WRITE ENABLE (

ALMOST FULL (AF)

FULL FLAG (FF) #1

FULL FLAG (FF) #2

Figure 11. Block Diagram of 64 x 16/256 x 16/512 x 16/1024 x 16/2048 x 16/4096 x 16 Synchronous FIFO

WEN

RESET (RS) RESET (RS)

READ CLOCK (RCLK)

)

IDT 72420/ 72200/ 72210/ 72220/ 72230/

72240

Used in a Width Expansion Configuration

IDT 72420/ 72200/ 72210/ 72220/ 72230/

72240

READ ENABLE (

OUTPUT ENABLE (OE)

ALMOST EMPTY (AE)

EMPTY FLAG (EF) #1 EMPTY FLAG (EF) #2

REN

DATA OUT (Q)

)

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IDT72420/72200/72210/72220/72230/72240 CMOS SyncFIFO 64 X 8, 256 X 8, 512 X 8, 1024 X 8, 2048 X 8 and 4096 X 8 MILITARY AND COMMERCIAL TEMPERATURE RANGES

DEPTH EXPANSION - The IDT72420/72200/72210/72220/

72230/72240 can be adapted to applications when the requirements are for greater than 64/256/512/1024/2048/4096 words. Depth expansion is possible by using expansion logic to direct the flow of data. A typical application would have the

ORDERING INFORMATION

IDT XXXXX

Device

Type

Power

SpeedXXPackageXProcess /

Temperature

Range

BLANKBCommercial (0°C to +70°C)

TP TC

12 15 20 25 35 50

expansion logic alternate data accesses from one device to the next in a sequential manner.

Please see the Application Note “DEPTH EXPANSION IDT'S SYNCHRONOUS FIFOs USING RING COUNTER APPROACH” for details of this configuration.

Military (–55°C to +125°C) Compliant to MIL-STD-883, Class B

Plastic THINDIP Sidebraze THINDIP

Commercial Only Commercial Only Commercial and Military Commercial and Military Commercial Only Commercial and Military

Clock Cycle Time (tCLK) Speed in Nanoseconds

72420 72200 72210 72220 72230 72240

Low Power

64 x 8 Synchronous FIFO 256 x 8 Synchronous FIFO 512 x 8 Synchronous FIFO 1024 x 8 Synchronous FIFO 2048 x 8 Synchronous FIFO 4098 x 8 Synchronous FIFO

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