Page 1
查询IDT72413L25D供应商
CMOS PARALLEL
64 x 5-BIT FIFO
WITH FLAGS
Integrated Device Technology, Inc.
FEATURES:
• First-ln/First-Out Dual-Port memory—45MHz
• 64 x 5 organization
• Low-power consumption
— Active: 200mW (typical)
• RAM-based internal structure allows for fast fall-through
time
• Asynchronous and simultaneous read and write
• Expandable by bit width
• Cascadable by word depth
• Half-Full and Almost-Full/Empty status flags
• IDT72413 is pin and functionally compatible with the
MMI67413
• High-speed data communications applications
• Bidirectional and rate buffer applications
• High-performance CMOS technology
• Available in plastic DIP, CERDIP and SOIC
• Military product compliant to MIL-STD-883, Class B
• Industrial temperature range (-40
able, tested to military electrical specifications
o
C to +85oC) is avail-
IDT72413
DESCRIPTION:
The IDT72413 is a 64 x 5, high-speed First-In/First-Out
(FIFO) that loads and empties data on a first-in-first-out basis.
It is expandable in bit width. All speed versions are cascadable in depth.
The FIFO has a Half-Full Flag, which signals when it has 32
or more words in memory. The Almost-Full/Empty Flag is
active when there are 56 or more words in memory or when
there are 8 or less words in memory.
The IDT72413 is pin and functionally compatible to the
MMI67413. It operates at a shift rate of 45MHz. This makes it
ideal for use in high-speed data buffering applications. The
IDT72413 can be used as a rate buffer, between two digital
systems of varying data rates, in high-speed tape drivers, hard
disk controllers, data communications controllers and
graphics controllers.
The IDT72413 is fabricated using IDTs high-performance
CMOS process. This process maintains the speed and high
output drive capability of TTL circuits in low-power CMOS.
Military grade product is manufactured in compliance with
the latest revision of MIL-STD-883, Class B.
FUNCTIONAL BLOCK DIAGRAM
DATA
(D
0-4
MASTER
RESET
INPUT
READY
SHIFT
IN
IN
)
(MR)
(IR)
(SI)
FIFO
INPUT
STAGE
INPUT
CONTROL
LOGIC
64 x 5
MEMORY
ARRAY
REGISTER
CONTROL
LOGIC
FLAG
CONTROL
LOGIC
OUPUT ENABLE
(OE)
FIFO
OUTPUT
STAGE
OUTPUT
CONTROL
LOGIC
HALF-FULL (HF)
ALMOST-FULL/
EMPTY (AF/E)
(SO)
(OR)
DATA
(Q
0-4
SHIFT
OUT
OUPUT
READY
2748 drw 01
OUT
)
The IDT logo is a registered trademark of Integrated Device Technology,Inc.
FAST is a trademark of National Semiconductor, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES DECEMBER 1996
1996 Integrated Device Technology, Inc. DSC-2748/7
For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.
5.02 1
Page 2
IDT72413
CMOS PARALLEL 64 x 5-BIT FIFO WITH FLAGS MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATION
OE
HF
IR
SI
D
D
D
D
D
GND
1
2
3
4
P20-1,
C20-1,
5
0
6
1
2
3
4
7
8
9
10
SO20-2
DIP/SOIC
TOP VIEW
20
Vcc
19
AF/E
18
SO
17
OR
16
Q
&
15
14
13
12
11
0
1
Q
Q
2
Q
3
Q
4
MR
2748 drw 02
CAPACITANCE (TA = +25°C, f = 1.0MHz)
Symbol Parameter
IN Input Capacitance VIN = 0V 5 pF
C
OUT Output Capacitance VOUT = 0V 7 pF
C
NOTE: 2748 tbl 02
1. This parameter is sampled and not 100% tested.
2. Characterized values, not currently listed.
(1)
Conditions Max. Unit
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol Rating Commercial Military Unit
V
TERM Terminal Voltage -0.5 to +7.0 -0.5 to +7.0 V
with Respect
to GND
T
A Operating 0 to +70 -55 to +125 °C
Temperature
T
BIAS Temperature -55 to +125 -65 to +135 °C
Under Bias
T
STG Storage -55 to +125 -65 to +150 °C
Temperature
OUT DC Output 50 50 mA
I
Current
NOTE: 2748 tbl 01
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min. Typ. Max. Unit
CC Military Supply 4.5 5.0 5.5 V
V
Voltage
CC Commercial Supply 4.5 5.0 5.5 V
V
Voltage
GND Supply Voltage 0 0 0 V
IH Input High Voltage 2.0 — — V
V
(1)
IL
V
NOTE: 2748 tbl 03
1. 1.5V undershoots are allowed for 10ns once per cycle.
Input Low Voltage — — 0.8 V
5.02 2
Page 3
IDT72413
CMOS PARALLEL 64 x 5-BIT FIFO WITH FLAGS MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 5.0V ± 10%, TA = 0°C to +70°C; Military: VCC = 5.0V ± 10%, TA = –55°C to +125°C)
Symbol Parameter Test Conditions Min. Max. Unit
IL Low-Level Input Current VCC = Max., GND ≤ VI ≤ VCC -10 — µA
I
IH High-Level Input Current VCC = Max., GND ≤ VI ≤ VCC —10 µA
I
OL Low-Level Output Current VCC = Min. IOL (Q0-4) Mil. 12mA — 0.4 V
V
Com'l. 24mA
OL (IR, OR)
I
OL (HF, AF/E) 8mA
I
OH High-Level Output Current VCC = Min. IOH (Q0-4) –4mA 2.4 — V
V
OH (IR, OR) –4mA
I
OH (HF, AF/E) –4mA
I
(2)
OS
I
HZ Off-State Output Current VCC = Max. VO = 2.4V — 20 µA
I
LZ VCC = Max. VO = 0.4V -20 —
I
(3)
CC
I
Output Short-Circuit Current VCC = Max. VO = 0V -20 -110 mA
Supply Current VCC = Max., OE=HIGH Mil. — 70 mA
Inputs LOW, f=25MHz Com'l. — 60
NOTES: 2748 tbl 04
1. Care should be taken to minimize as much as possible the DC and capactive load on IR and OR when operating at frequencies above 25mHz.
2. Not more than one output should be shorted at a time and duration of the short circuit should not exceed one second. Guaranteed by design, but not
currently tested.
3. For frequencies greater than 25MHz, I
CC = 60mA + (1.5mA x [f - 25MHz]) commercial and ICC = 70mA + (1.5mA x [f - 25MHz]) military.
(1)
8mA
OPERATING CONDITIONS
(Commercial: VCC = 5.0V ± 10%, TA = 0°C to +70°C; Military: VCC = 5.0V ± 10%, TA = –55°C to +125°C)
Commercial Military & Commercial Military & Commercial
IDT72413L45 IDT72413L35 IDT72413L25
Symbol Parameters Figure Min. Max. Min. Max. Min. Max. Unit
(1)
SIH
t
SIL
t
IDS Input Data Set-up 2 0 — 0 — 0 — ns
t
IDH Input Data Hold Time 2 13 — 15 — 25 — ns
t
SOH
t
SOL Shift Out LOW Time 5 11 — 17 — 20 — ns
t
MRW Master Reset Pulse 8 20 — 30 — 35 — ns
t
MRS Master Reset Pulse to SI 8 20 — 35 — 35 — ns
t
NOTE: 2748 tbl 05
1. Since the FIFO is a very high-speed device, care must be excercised in the design of the hardware and timing utilized within the design. Device grounding
and decoupling are crucial to correct operation as the FIFO will respond to very small glitches due to long reflective lines, high capacitances and/or poor
supply decoupling and grounding. A monolithic ceramic capacitor of 0.1µF directly between VCC and GND with very short lead length is recommended.
Shift in HIGH Time 2 9 — 9 — 16 — ns
(1)
Shift in LOW TIme 2 11 — 17 — 20 — ns
(1)
Shift Out HIGH Time 5 9 — 9 — 16 — ns
5.02 3
Page 4
IDT72413
CMOS PARALLEL 64 x 5-BIT FIFO WITH FLAGS MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 5.0V ± 10%, TA = 0°C to +70°C; Military: VCC = 5.0V ± 10%, TA = –55°C to +125°C)
Commercial Mil. & Com'l Mil. & Com'l
IDT72413L45 IDT72413L35 IDT72413L25
Symbol Parameters Figure Min. Max. Min. Max. Min. Max. Unit
IN Shift In Rate 2 — 45 — 35 — 25 MHz
f
(1)
IRL
t
t
IRH
OUT Shift Out Rate 5 — 45 — 35 — 25 MHz
f
ORL
t
t
ORH
ODH
t
ODS Output Data Shift Next Word 5 — 19 — 20 — 20 ns
t
PT Data Throughput or "Fall-Through" 4, 7 — 25 — 28 — 40 ns
t
t
MRORL Master Reset ↓ to Output Ready LOW 8 — 25 — 28 — 30 ns
MRIRH
t
MRIRL
t
t
MRQ Master Reset ↓ to Outputs LOW 8 — 20 — 25 — 35 ns
MRHF Master Reset ↓ to Half-Full Flag 8 — 25 — 28 — 40 ns
t
MRAFE Master Reset ↓ to AF/E Flag 8 — 25 — 28 — 40 ns
t
IPH
t
OPH
t
ORD
t
AEH Shift Out ↑ to AF/E HIGH 9 — 28 — 28 — 40 ns
t
AEL Shift In ↑ to AF/E 9 — 28 — 28 — 40 ns
t
AFL Shift Out ↑ to AF/E LOW 10 — 28 — 28 — 40 ns
t
AFH Shift In ↑ to AF/E HIGH 10 — 28 — 28 — 40 ns
t
HFH Shift In ↑ to HF HIGH 11 — 28 — 28 — 40 ns
t
HFL Shif Out ↑ to HF LOW 11 — 28 — 28 — 40 ns
t
PHZ
t
PLZ
t
PLZ
t
PHZ
t
NOTES: 2748 tbl 06
1. Since the FIFO is a very high-speed device, care must be taken in the design of the hardware and the timing utilized within the design. Device grounding
and decoupling are crucial to correct operation as the FIFO will respond to very small glitches due to long reflective lines, high capacitances and/or poor
supply decoupling and grounding. A monolithic ceramic capacitor of 0.1µF directly between VCC and GND with very short lead length is recommended.
2. If the FIFO is full, (IR = HIGH),
3. Guaranteed by design but not currently tested.
Shift In ↑ to Input Ready LOW 2 — 18 — 18 — 28 ns
(1)
Shift In ↓ to Input Ready HIGH 2 — 18 — 20 — 25 ns
(1)
Shift Out ↓ to Output Ready LOW 5 — 18 — 18 — 28 ns
(1)
Shift Out ↓ to Output Ready HIGH 5 — 19 — 20 — 25 ns
(1)
Output Data Hold Previous Word 5 5 — 5 — 5 — ns
(3)
Master Reset ↑ to Input Ready HIGH 8 — 25 — 28 — 30 ns
(2)
Master Reset ↓ to Input Ready LOW 8 — 25 — 28 — 30 ns
(3)
Input Ready Pulse HIGH 4 5 — 5 — 5 — ns
(3)
Ouput Ready Pulse HIGH 7 5 — 5 — 5 — ns
(3)
Output Ready ↑ HIGH to Valid Data 5 — 5 — 5 — 7 ns
(3)
Output Disable Delay 12 — 12 — 12 — 15 ns
(3)
(3)
Output Enable Delay 12 — 15 — 15 — 20 ns
(3)
MR ↓ forces IR to go LOW, and MR ↑ causes IR to go HIGH.
12 — 12 — 12 — 15
12 — 15 — 15 — 20
5.02 4
Page 5
IDT72413
CMOS PARALLEL 64 x 5-BIT FIFO WITH FLAGS MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC TEST CONDITIONS
Input Pulse Levels GND to 3.0V
Input Rise/Fall Times 3ns
Input Timing Reference Levels 1.5V
Output Reference Levels 1.5V
Output Load See Figure 1
2748 tbl 07
STANDARD TEST LOAD DESIGN TEST LOAD
5V
2KΩ
2748 drw 03
OUTPUT
R2
5V
R1
TEST POINT
30pF*
or equivalent
30pF*
circuit
*Including scope and jig
RESISTOR VALUES FOR
STANDARD TEST LOAD
IOL R1 R2
24mA 200Ω 300Ω
12mA 390Ω 760Ω
8mA 600Ω 1200Ω
2748 tbl 08
Figure 1. Output Load
FUNCTIONAL DESCRIPTION:
The IDT72413, 65 x 5 FIFO is designed using a dual-port
RAM architecture as opposed to the traditional shift register
approach. This FIFO architecture has a write pointer, a read
pointer and control logic, which allow simultaneous read and
write operations. The write pointer is incremented by the
falling edge of the Shift In (Sl) control; the read pointer is
incremented by the falling edge of the Shift Out (SO). The
Input Ready (IR) signals when the FIFO has an available
memory location; Output Ready (OR) signals when there is
valid data on the output. Output Enable (OE) provides the
capability of three-stating the FIFO outputs.
FIFO RESET
The FIFO must be reset upon power up using the Master
Reset (MR) signal. This causes the FIFO to enter an empty
state signified by Output Ready (OR) being LOW and Input
Ready (IR) being HIGH. In this state, the data outputs (Q0-4)
will be LOW.
DATA INPUT
Data is shifted in on the LOW-to-HIGH transition of Shift In
(Sl). This loads input data into the first word location of the
FIFO and causes the lnput Ready to go LOW. On the HlGHto-LOW transition of Shift In, the write pointer is moved to the
next word position and Input Ready (lR) goes HlGH indicating
the readiness to accept new data. If the FIFO is full, Input
Ready will remain LOW until a word of data is shifted out.
DATA OUTPUT
Data is shifted out on the HIGH-to-LOW transition of Shift
Out (SO). This causes the internal read pointer to be advanced to the next word location. If data is present, valid data
will appear on the outputs and Output Ready (OR) will go
HIGH. If data is not present, Output Ready will stay LOW
indicating the FIFO is empty. The last valid word read from the
FIFO will remain at the FlFOs output when it is empty. When
the FIFO is not empty Output Ready (OR) goes LOW on the
LOW-to-HlGH transition of Shift Out.
FALL-THROUGH MODE
The FIFO operates in a Fall-Through Mode when data gets
shifted into an empty FIFO. After the fall-through delay the
data propagates to the output. When the data reaches the
output, the Output Ready (OR) goes HIGH.
A Fall-Through Mode also occurs when the FIFO is
completely full. When data is shifted out of the full FIFO a
location is available for new data. After a fall-through delay,
the lnput Ready goes HlGH. If Shift In is HIGH, the new data
can be written to the FIFO. The fall-through delay of a RAMbased FIFO (one clock cycle) is far less than the delay of a
Shift register-based FIFO.
5.02 5
Page 6
IDT72413
CMOS PARALLEL 64 x 5-BIT FIFO WITH FLAGS MILITARY AND COMMERCIAL TEMPERATURE RANGES
SIGNAL DESCRIPTIONS:
INPUTS:
DATA INPUT (D0-4)
Data input lines. The IDT72413 has a 5-bit data input.
CONTROLS:
SHIFT IN (SI)
Shift In controls the input of the data into the FIFO. When
SI is HIGH, data can be written to the FIFO via the D0-4 lines.
The data has to meet set-up and hold time requirements with
respect to the rising edge of SI.
SHIFT OUT (SO)
Shift Out controls the outputs data from the FIFO.
MASTER RESET (
MR)
Master Reset clears the FIFO of any data stored within.
Upon power up, the FIFO should be cleared with a Master
Reset. Master Reset is active LOW.
HALF-FULL FLAG (HF)
Half-Full Flag signals when the FIFO has 32 or more words
in it.
TIMING DIAGRAMS
1/f
IN
INPUT READY(IR)
When Input Ready is HIGH, the FIFO is ready for new input
data to be written to it. When IR is LOW, the FIFO is
unavailable for new input data, Input Ready is also used to
cascade many FIFOs together, as shown in Figure 13 in the
Applications section.
OUTPUT READY (OR)
When Output Ready is HIGH, the output (Q
0-4) contains valid
data. When OR is LOW, the FIFO is unavailable for new
output data. Output Ready is also used to cascade many
FIFOs together, as shown in Figure 13 in the Applications
section.
OUTPUT ENABLE (OE)
Output Enable is used to enable the FIFO outputs onto a
bus. Output Enable is active LOW.
ALMOST-FULL/EMPTY FLAG (AFE)
Almost-Full/Empty Flag signals when the FIFO is 7/8 full
(56 or more words) or 1/8 from empty (8 or less words).
OUTPUTS:
DATA OUTPUT (Q0-4)
Data output lines, three-state. The IDT72413 has a 5-bit
output.
1/f
IN
t
SHIFT IN
INPUT READY
INPUT DATA
SHIFT IN
INPUT READY
INPUT DATA
NOTES:
1. Input Ready HIGH indicates space is available and a Shift In pulse may be applied.
2. Input Data is loaded into the FIFO.
3. Input Ready goes LOW indicating the FIFO is unavailable for new data.
4. The write pointer is incremented.
5. The FIFO is ready for the next word.
6. If the FIFO is full, then the Input Ready remains LOW.
7. Shift In pulses applied while Input Ready is LOW will be ignored (see Figure 4).
(7)
(1)
SIH
t
IDH
t
IDS
(2)
STABLE DATA
Figure 3. The Machanism of Shifting Data Into the FIFO
t
SIL
Figure 2. Input Timing
(3)
t
IRL
(4)
t
IRH
2748 drw 04
(5)
(6)
2748 drw 05
5.02 6
Page 7
IDT72413
CMOS PARALLEL 64 x 5-BIT FIFO WITH FLAGS MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING DIAGRAMS (Continued)
(2)
SHIFT OUT
(3)
SHIFT IN
(5)
t
INPUT READY
(1)
PT
INPUT DATA
NOTES:
1. FIFO is initially full.
2. Shift Out pulse is applied.
3. Shift In is held HIGH.
4. As soon as Input Ready becomes HIGH the Input Data is loaded into the FIFO.
5. The write pointer is incremented. Shift In should not go LOW until (tPT + tIPH).
Figure 4. Data is Shifted In Whenever Shift In and Input Ready are Both HIGH
1/fOUT
SHIFT OUT
OUTPUT READY
tSOH
tSOL
tORD
tODH
(4)
t
IPH
STABLE DATA
2748 drw 06
1/fOUT
(2)
tRH
tORLtODS
OUTPUT DATA
NOTES:
1. This data is loaded consecutively A, B, C.
2. Output data changes on the falling edge of SO after a valid Shift Out sequence, i.e., OR and SO are both high together.
SHIFT OUT
(7)
(1)
OUTPUT READY
OUTPUT DATA
A-DATA B-DATA
(1)
Figure 5. Output TIming
(2)
(3)
A-DATA
C-DATA
(4)
(5)
B-DATA
A or B
NOTES:
1. Output Ready HIGH indicates that data is available and a Shift Out pulse may be applied.
2. Shift Out goes HIGH causing the next step.
3. Output Ready goes LOW.
4. Read pointer is incremented.
5. Output Ready goes HIGH indicating that new data (B) will be available at the FIFO outputs after t
6. If the FIFO has only one word loaded (A DATA) , Output Ready stays LOW and the A-DATA remains unchanged at the outputs.
7. Shift Out pulses applied when Output Ready is LOW will be ignored.
ORD ns.
2748 drw 07
(6)
2748 drw 08
Figure 6. The Mechanism of Shifting Data Out of the FIFO
5.02 7
Page 8
IDT72413
CMOS PARALLEL 64 x 5-BIT FIFO WITH FLAGS MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING DIAGRAMS (Continued)
SHIFT IN
SHIFT OUT
tPT
OUTPUT READY
NOTE:
1. FIFO initailly empty.
MASTER RESET
INPUT READY
OUTPUT READY
SHIFT IN
DATA OUTPUTS
(1)
(1)
(1)
tMRW
tMRIRL
tMRORL
tMRQ
Figure 7. t
PT and tOPH Specification
tMRIRH
tMRS
tOPH
2748 drw 09
HALF-FULL FLAG
ALMOST FULL/
EMPTY FLAG
NOTE:
1. FIFO is partially full..
tMRHF
tMRAFE
2748 drw 10
Figure 8. Master Reset Timing
5.02 8
Page 9
IDT72413
CMOS PARALLEL 64 x 5-BIT FIFO WITH FLAGS MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING DIAGRAMS (Continued)
SHIFT OUT
tSOH
ALMOST
FULL/EMPTY
SHIFT IN
(1)
tAEH
tSIH
NOTE:
1. FIFO contains 9 words (one more than Almost-Empty).
SHIFT IN
ALMOST
FULL/EMPTY
(1)
SHIFT OUT
NOTE:
1. FIFO contains 55 words (one short of Almost-Full).
Figure 10. t
SHIFT IN
t
HALF-FULL
(1)
Figure 9. t
t
SIH
t
AFH
SIH
t
HFH
AEH and tAEL Specifications
AFH and tAFL Specifications
t
SOH
t
SOH
tAEL
t
AFL
2748 drw 11
2748 drw 12
SHIFT OUT
t
NOTE:
1. FIFO contains 31 words (one short of Half-Full).
Figure 11. t
HFL and tHFH Specifications
HFL
2748 drw 13
3V
V
T
V
OE
t
WAVEFORM 1
WAVEFORM 2
NOTES:
1. Waveform 1 is for an output with internal conditions such that the output is LOW except when disabled by the output control.
2. Waveform 2 is for an output with internal conditions such that the output is HIGH except when disabled by the output control.
(1)
(2)
PZL
t
PZH
Figure 12. Enable and Disable
5.02 9
T
4.5V
V
T
t
PHZ
V
T
0V
t
PLZ
0.5V
0.5V
0V
1.5V
V
OL
V
OH
1.5V
2748 drw 14
Page 10
IDT72413
CMOS PARALLEL 64 x 5-BIT FIFO WITH FLAGS MILITARY AND COMMERCIAL TEMPERATURE RANGES
APPLICATIONS
OUTPUT
ENABLE
OE
COMPOSITE
INPUT
READY
HF
IR
SI
D0
D
D2
D
D
HF
IR
SI
D0
D
D2
D
D
1
3
4
1
3
4
MR
OE
MR
AF/E
SO
OR
Q
Q1
Q2
Q3
Q
AF/E
SO
OR
Q
Q1
Q2
Q3
Q
SHIFT OUT
0
4
COMPOSITE
OUTPUT
0
4
READY
OE
SHIFT IN
HF
IR
SI
D0
D
D2
D
D
1
3
4
MR
AF/E
SO
OR
Q
Q1
Q2
Q3
Q
0
4
MASTER
RESET
NOTE:
1. FIFOs are expandable in width. However, in forming wider words two external gates are required to generate composite Input and Output Ready
flags. This requirement is due to the different fall-through times of the FIFOs.
Figure 13. 64 x 15 FIFO with IDT72413
8-BITS
SYSTEM 1
8-BITS
TWO
2748 drw 15
SYSTEM 2
IDT72413
64 x 8
SO
OR
ALMOST-FULL/
EMPTY
IO RDY
INTERRUPTINTERRUPT
ENBL SI
SI
IR
HALF-FULL FLAG
NOTE:
1. Cascading the FIFOs in word width is done by ANDing the IR and OR as shown in Figure 13.
Figure 14. Application for IDT72413 for Two Asynchronous Systems
5.02 10
2748 drw 16
Page 11
IDT72413
CMOS PARALLEL 64 x 5-BIT FIFO WITH FLAGS MILITARY AND COMMERCIAL TEMPERATURE RANGES
SHIFT IN
INPUT READY
DATA IN
SI
IR
D0
D
1
D2
D
3
D
4 Q4
MR
OR
SO
Q
Q1
Q2
Q3
SI
IR
0
D0
D
1
D2
D
3
D
4 Q4
MR
OR
SO
Q
Q1
Q2
Q3
0
MR
NOTE:
1. FIFOs can be easily cascaded to any desired depth. The handshaking and associated timing between the FIFOs are handled by the inherent timing
of the devices.
Figure 15. 128 x 5 Depth Expansion
OUTPUT READY
SHIFT OUT
DATA OUT
2748 drw 17
ORDERING INFORMATION
IDT XXXXX
Device Type
Power
X
X
Speed
PackageXProcess/
X
Temperature
Range
Blank
Commercial (0°C to+70°C)
B
Military (–55°C to+125°C)Compliant to MIL-STD-883, Class B
P
Plastic DIP (300 mils wide)
D
Cerdip (300 mils wide)
SO
Small Outline IC
45
Com’l. Only
35
Com'l. and Mil
25
Com’l. and Mil
L
Low Power
64 x 5 FIFO
72413
Shift Frequency (fs)Speed in MHz
2748 drw 18
5.02 11
Loading...