Datasheet IDT72132L35P, IDT72142L35P, IDT72142L50P Datasheet (Integrated Device Technology Inc)
Page 1
Integrated Device Technology, Inc.
CMOS SERIAL-TO-PARALLEL FIFO
2048 x 9
4096 x 9
IDT72132
IDT72142
FEATURES:
• 35ns parallel-port access time, 45ns cycle time
• 50MHz serial port shift rate
• Expandable in depth and width with no external
components
• Programmable word lengths including 8, 9, 16-18, and
32-36 bit using Flexshift serial input without using any
additional components
• Multiple status flags: Full, Almost-Full (1/8 from full),
Half-Full, Almost Empty (1/8 from empty), and Empty
• Asynchronous and simultaneous read and write
operations
• Dual-Port zero fall-through architecture
• Retransmit capability in single device mode
• Produced with high-performance, low-power CMOS
technology
• Available in the 28-pin plastic DIP
• Industrial temperature range (-40
able, tested to military electrical specifications
o
C to +85oC) is avail-
DESCRIPTION:
The IDT72132/72142 are high-speed, low-power serial-toparallel FIFOs. These FIFOs are ideally suited to serial
communications applications, tape/disk controllers, and local
area networks (LANs). The IDT72132/72142 can be configured with the IDTs parallel-to-serial FIFOs (IDT72131/72141)
for bidirectional serial data buffering.
The FIFO has a serial input port and a 9-bit parallel output
port. Wider and deeper serial-to-parallel data buffers can be
built using multiple IDT72132/72142 chips. IDTs unique
Flexshift serial expansion logic (SIX, NW) makes width
expansion possible with no additional components. These
FIFOs will expand to a variety of word widths including 8, 9, 16,
and 32 bits. The IDT72132/142 can also be directly connected
for depth expansion.
Five flags are provided to monitor the FIFO. The full and
empty flags prevent any FIFO data overflow or underflow
conditions. The Almost-Full (7/8), Half-Full, and Almost Empty
(1/8) flags signal memory utilization within the FIFO.
The IDT72132/72142 is fabricated using IDTs high-speed
submicron CMOS technology.
FUNCTIONAL BLOCK DIAGRAM
SICP
SIX
SI
NW
RS
FL/RT
XI
D7D
SERIAL INPUT
CIRCUITRY
NEXT WRITE
POINTER
RESET
LOGIC
EXPANSION
LOGIC
8
RAM ARRAY
2048 x 9
4096 x 9
XO/
OE
Q0-Q
PIN CONFIGURATION
NW
EF
FLAG
LOGIC
READ
POINTER
8
AEF
/HF
FF
R
2752 drw 01
GND
AEF
FF
Q
Q
Q
Q
Q
GND
1
2
3
XI
4
5
6
0
7
1
8
2
9
3
10
4
11
12
R
Q
13
5
Q
14
6
P28-1
&
C28-3
DIP
28
27
26
25
24
23
22
21
20
19
18
17
16
15
TOP VIEW
Vcc
D
7
D8
FL/RT
RS
SI
SICP
SIX
OE
EF
XO/HF
GND
Q
8
Q
7
2752 drw 02
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGES DECEMBER 1996
1996 Integrated Device Technology, Inc. DSC-2752/6
For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.
5.36 1
Page 2
IDT72132, IDT72142
CMOS SERIAL-TO-PARALLEL FIFO 2048 x 9 AND 4096 x 9 COMMERCIAL TEMPERATURE RANGES
PIN DESCRIPTIONS
Symbol Name I/O Description
SI Serial Input I Serial data is shifted in least significant bit first. In the serial cascade mode, the Serial Input
(SI) pins are tied together and SIX plus D
RS
Reset I When RS is set LOW, internal READ and WRITE pointers are set to the first location of the
RAM array. HF and FF go HIGH, and
WRITE after power-up. R must be HIGH during an RS cycle.
NW
Next Write I To program the Serial In word width , connect NW with one of the Data Set pins (D
SICP Serial Input Clock I Serial data is read into the serial input register on the rising edge of SICP. In both Depth and
Serial Word Width Expansion modes, all of the SICP pins are tied together.
R
Read I When READ is LOW, data can be read from the RAM array sequentially, independent of SICP.
In order for READ to be active, EF must be HIGH. When the FIFO is empty (EF-LOW), the
internal READ operation is blocked and Q
FL/RT
First Load/ I This is a dual-purpose input. In the single device configuration (XI grounded), activating
Retransmit
retransmit (FL/RT-LOW) will set the internal READ pointer to the first location. There is no
effect on the WRITE pointer. R must be HIGH and SICP must be LOW before setting FL/
LOW. Retransmit is not possible in depth expansion. In the depth expansion configuration,
FL/RT
grounded indicates the first activated device.
XI
Expansion In I In the single device configuration, XI is grounded. In depth expansion or daisy chain
expansion, XI is connected to XO (expansion out) of the previous device.
SIX Serial Input I In the Expansion mode, the SIX pin of the least significant device is tied HIGH. The SIX pin
of all other devices is connected to the D
operation, SIX is tied HIGH.
OE
Expansion
Output Enable I When OE is set LOW, the parallel output buffers receive data from the RAM array. When
is set HIGH, parallel three state buffers inhibit data flow.
Q
0–Q8 Output Data O Data outputs for 9-bit wide data.
FF
Full Flag O When FF goes LOW, the device is full and data must not be clocked by SICP. When FF is
HIGH, the device is not full. See the diagram on page 7 for more details.
EF
AEF
XO/HF
Empty Flag O When EF goes LOW, the device is empty and further READ operations are inhibited. When
EF
is HIGH, the device is not empty.
Almost-Empty/ O When
Almost-Full Flag
AEF
is LOW, the device is empty to 1/8 full or 7/8 to completely full. When
the device is greater than 1/8 full, but less than 7/8 full.
Expansion Out/ O This is a dual-purpose output. In the single device configuration (XI grounded), the device is
Half-Full Flag
more than half full when HF is LOW. In the depth expansion configuration (XO connected to
XI
of the next device), a pulse is sent from XO to XI when the last location in the RAM array
is filled.
D
7, D8 Data Set O The appropriate Data Set pin (D7, D8 ) is connected to
width. For example: D
7 -
NW
programs a 8-bit word width, D8 - NW programs a 9-bit word
width, etc.
V
CC Power Supply Single Power Supply of 5V.
GND Ground Three grounds at 0V.
7, D8 determine which device stores the data.
AEF
, and EF go LOW. A reset is required before an initial
0-Q8 are in a high impedance condition.
7 or D8 pin of the previous device. For single device
AEF
NW
to program the Serial In data word
7, D8).
RT
OE
is HIGH,
2752 tbl 01
STATUS FLAGS
Number of Words in FIFO
IDT72132 IDT72142
00HLHL
1-255 1-511 H L H H
256-1024 512-2048 H H H H
1025-1792 2049-3584 H H L H
1793-2047 3585-4095 H L L H
2048 4096 L L L H
FF AEF HF EF
2752 tbl 02
5.36 2
Page 3
IDT72132, IDT72142
CMOS SERIAL-TO-PARALLEL FIFO 2048 x 9 AND 4096 x 9 COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol Rating Commercial Unit
V
TERM Terminal Voltage –0.5 to +7.0 V
with Respect
to GND
T
A Operating 0 to +70 °C
Temperature
T
BIAS Temperature –55 to +125 °C
Under Bias
T
STG Storage –55 to +125 °C
Temperature
OUT DC Output 50 mA
I
Current
NOTE: 2752 tbl 03
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
CAPACITANCE (TA = +25°C, f = 1.0MHz)
Symbol Parameter
IN Input Capacitance VIN = 0V 10 pF
C
OUT Output Capacitance VOUT = 0V 12 pF
C
NOTE: 2752 tbl 05
1. This parameter is sampled and not 100% tested.
(1)
Conditions Max. Unit
RECOMMENDED DC OPERATING CONDITIONS
Symbol Parameter Min. Typ. Max. Unit
CC Commercial Supply 4.5 5.0 5.5 V
V
Voltage
GND Supply Voltage 0 0 0 V
IH Input High Voltage 2.0 — — V
V
Commercial
(1)
IL
V
NOTE: 2752 tbl 04
1. 1.5V undershoots are allowed for 10ns once per cycle.
Input Low Voltage — — 0.8 V
DC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 5.0V ± 10%, TA = 0°C to +70°C)
IDT72132/IDT72142
Commercial
Symbol Parameter Min. Typ. Max. Unit
(1)
IL
I
(2)
I
OL
OH Output Logic "1" Voltage, 2.4 — — V
V
OL Output Logic "0" Voltage, — — 0.4 V
V
(3)
CC1
I
(3)
CC2
I
CC3(L)
I
NOTES: 2752 tbl 06
1. Measurements with 0.4 ≤ VIN ≤ VCC.
2. R
≤ VIL, 0.4 ≤ VOUT ≤ VCC.
CC measurements are made with outputs open.
3. I
Input Leakage Current –1 — 1 µA
(Any Input)
Output Leakage Current –10 — 10 µA
I
OUT = -2mA
I
OUT = 8mA
Power Supply Current — 90 140 mA
Average Standby Current — 8 12 mA
(R =
RS = FL/RT
(SICP = V
(3,4)
Power Down Current — — 2 mA
IL)
= V
IH)
5.36 3
Page 4
IDT72132, IDT72142
CMOS SERIAL-TO-PARALLEL FIFO 2048 x 9 AND 4096 x 9 COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 5.0V ± 10%, TA = 0°C to +70°C)
Commercial
IDT72132L35 IDT72132L50
IDT72142L35 IDT72142L50
Symbol Parameter Min. Max. Min. Max. Unit
t
S Parallel Shift Frequency — 22.2 — 15 MHz
t
SICP Serial-InShift Frequency — 50 — 40 MHz
PARALLEL OUTPUT TIMINGS
t
A Access Time — 35 — 50 ns
t
RR Read Recovery Time 10 — 15 — ns
t
RPW Read Pulse Width 35 — 50 — ns
t
RC Read Cycle Time 45 — 65 — ns
t
RLZ Read Pulse LOW to Data Bus at Low-Z
t
RHZ Read Pulse HIGH to Data Bus at High-Z
t
DV Data Valid from Read Pulse HIGH 5 — 5 — ns
t
OEHZ Output Enable to High-Z (Disable)
t
OELZ Output Enable to Low-Z (Enable)
t
AOE Output Enable to Data Valid (Q0-8) — 20 — 22 ns
SERIAL INPUT TIMINGS
t
SIS Serial Data in Set-Up Time to SICP Rising Edge 12 — 15 — ns
t
SIH Serial Data in Hold Time to SICP Rising Edge 0 — 0 — ns
t
SIX SIX Set-Up Time to SICP Rising Edge 5 — 5 — ns
t
SICW Serial-In Clock Width HIGH/LOW 8 — 10 — ns
FLAG TIMINGS
t
SICEF SICP Rising Edge (Last Bit - First Word) to
t
SICFF SICP Rising Edge (Bit 1 - Last Word) to
t
SICF SICP Rising Edge to
t
RFFSI Recovery Time SICP After
t
REF Read LOW to
t
RFF Read HIGH to
t
RF Read HIGH to Transitioning
t
RPE Read Pulse Width After
HF, AEF
FF
Goes HIGH 15 — 15 — ns
EF
LOW — 30 — 45 ns
FF
HIGH — 30 — 45 ns
HF
and
EF
HIGH 35 — 50 — ns
RESET TIMINGS
t
RSC Reset Cycle Time 45 — 65 — ns
t
RS Reset Pulse Width 35 — 50 — ns
t
RSS Reset Set-up Time 35 — 50 — ns
t
RSR Reset Recovery Time 10 — 15 — ns
t
RSF1 Reset to
t
RSF2 Reset to
t
RSDL Reset to D LOW 20 — 35 — ns
t
POI SICP Rising Edge to D 5 17 5 20 ns
EF
and
AEF
LOW — 45 — 65 ns
HF
and FF HIGH — 45 — 65 ns
RETRANSMIT TIMINGS
t
RTC Retransmit Cycle Time 45 — 65 — ns
t
RT Retransmit Pulse Width 35 — 50 — ns
t
RTS Retransmit Set-up Time 35 — 50 — ns
t
RTR Retransmit Recovery Time 10 — 15 — ns
DEPTH EXPANSION MODE TIMINGS
t
XOL Read/Write to
t
XOH Read/Write to
t
XI
t
XIR
t
XIS
NOTE: 2752 tbl 07
1. Guaranteed by design minimum times, not tested
XI
Pulse Width 35 — 50 — ns
XI
Recovery Time 10 — 10 — ns
XI
Set-up Time 16 — 15 — ns
XO
LOW — 40 — 50 ns
XO
HIGH — 40 — 50 ns
(1)
(1)
(1)
(1)
5 — 10 — ns
—20—30ns
—15—15ns
5—5—ns
EF
HIGH — 45 — 65 ns
FF
LOW — 30 — 40 ns
—45—65ns
AEF
—45—65ns
5.36 4
Page 5
IDT72132, IDT72142
CMOS SERIAL-TO-PARALLEL FIFO 2048 x 9 AND 4096 x 9 COMMERCIAL TEMPERATURE RANGES
AC TEST CONDITIONS
Input Pulse Levels GND to 3.0V
Input Rise/Fall Times 5ns
Input Timing Reference Levels 1.5V
Output Reference Levels 1.5V
Output Load See Figure A
2752 tbl 08
FUNCTIONAL DESCRIPTION
Serial Data Input
The serial data is input on the SI pin. The data is clocked
in on the rising edge of SICP providing the Full Flag (FF) is not
asserted. If the Full Flag is asserted then the next parallel data
word is inhibited from moving into the RAM array. NOTE:
SICP should not be clocked once the last bit of the last word
has been shifted in, as indicated by NW HIGH and FF LOW.
If it is, then the input data will be lost.
The serial word is shifted in Least Significant Bit first. Thus,
when the FIFO is read, the Least Significant Bit will come out
on Q
0 and the second bit is on Q1 and so on. The serial word
width must be programmed by connecting the appropriate
Data Set line (D7, D8) to the NW input. The data set lines are
taps off a digital delay line. Selecting one of these taps
programs the width of the serial word to be written in.
5V
1.1K
Ω
D.U.T.
Ω
680
or equivalent circuit
Figure A. Output Load
*Includies jig and scope capacitances
30pF*
2752 drw 03
Parallel Data Output
A read cycle is initiated on the falling edge of Read (R)
provided the Empty Flag is not set. The output data is
accessed on a first-in/first-out basis, independent of the
ongoing write operations. The data is available tA after the
falling edge of R and the output bus Q goes into high impedance after R goes HIGH.
Alternately, the user can access the FIFO by keeping
LOW and enabling data on the bus by asserting Output Enable
(OE). When R is LOW, the OE signal enables data on the
output bus. When R is LOW and OE is HIGH, the output bus
is three-stated. When R is HIGH, the output bus is disabled
irrespective of OE.
R
RS
SICP
R
AEF, EF
HF, FF
tRSDL tPDI
78
D ,D
NOTE:
1. Input bits are numbered 0 to n-1. D
tRSC
tRS
tRSS
tRSS
t
RSF1
tRSF2
7 and D8 correspond to n=8 and n=9 respectively
Figure 1. Reset
tRSR
0 n-1
(1)
2752 drw 04
5.36 5
Page 6
IDT72132, IDT72142
CMOS SERIAL-TO-PARALLEL FIFO 2048 x 9 AND 4096 x 9 COMMERCIAL TEMPERATURE RANGES
0 1 n – 1
SICP
SIX
tSIX
SI
tSIS tSIH
NOTE:
1. Input bits are numbered 0 to n-1.
R
Q
0–8
t
RLZ
tSICW
tSICW
2
(1)
1/tSICP
2752 drw 05
t
RPW
Figure 2. Write Operation
t
RC
t
RR
VALID DATA
t
DV
t
A
t
RHZ
R
OE
Q0–8
t
RLZ
2752 drw 06
Figure 3. Read Operation
tRC
t
RR
t
A
tOEHZ
DATA 1
Figure 4. Output Enable Timings
SECOND READ BY CONTROLLING
tAOE
tOELZ
DATA 1
TERMINATE READ CYCLE
OE
tDV
2752 drw 07
5.36 6
Page 7
IDT72132, IDT72142
CMOS SERIAL-TO-PARALLEL FIFO 2048 x 9 AND 4096 x 9 COMMERCIAL TEMPERATURE RANGES
LAST WRITE NO WRITE FIRST READ ADDITIONAL
FIRST WRITE
READS
R
0 1 n – 1
SICP
0 1 n – 1
tSICFF
(1)
tRFF
FF
NOTE:
1. After FF goes LOW and the last bit of the final word has been clocked in, SICP should not be clocked until FF goes HIGH.
Figure 5. Full Flag from Last Write to First Read
LAST READ IGNORED
READ
FIRST WRITE ADDITIONAL
WRITES
0 1 n – 1 0 1 n – 1
SICP
R
tREF
tSICEF
2752 drw 08
FIRST READ
DATAOUT
SICP
EF
DATAOUT
EF
R
tA
VALID
Figure 6. Empty Flag from Last Read to First Write
FIRST SERIAL-IN WORD SECOND SERIAL-IN WORD
0 1 n – 1
tSICEF
Figure 7. Empty Boundry Condition Timing
tRPE
VALID
0 1 n – 1 0
t
A
2752 drw 09
2752 drw 10
5.36 7
Page 8
IDT72132, IDT72142
CMOS SERIAL-TO-PARALLEL FIFO 2048 x 9 AND 4096 x 9 COMMERCIAL TEMPERATURE RANGES
R
t
RFF
FF
tSICFF
0 1 n – 1
SICP
tRFFSI
(1)
tSIS
SI
tA
DATAOUT
NOTE:
1. After FF goes LOW and the last bit of the final word has been clocked in, SICP should not be clocked until FF goes HIGH.
Figure 8. Full Boundry Condition Timing
0 1 n – 2 n – 1
SICP
HF
HALF-FULL
t
SICF
HALF_FULL + 1
tRF
HALF-FULL
R
AEF
AEF
t
SICF
7/8 FULL
ALMOST-EMPTY
(1/8 FULL-1)
ALMOST FULL (7/8 + 1)
1/8 FULL
Figure 9. Half Full, Almost Full and Almost Empty Timings
tRF
7/8 FULL
ALMOST-EMPTY
(1/8 FULL-1)
2752 drw 11
2752 drw 12
RT
SICP
EF, AEF, HF, FF
NOTE:
1.EF,
AEF, HF
tRTC
tRT
tRTS tRTR
R
tRTS
and FF may change status during Retransmit, but flags will be valid at t
Figure 10. Retransmit
5.36 8
01
FLAG VALID
2752 drw 13
RTC.
Page 9
IDT72132, IDT72142
CMOS SERIAL-TO-PARALLEL FIFO 2048 x 9 AND 4096 x 9 COMMERCIAL TEMPERATURE RANGES
SICP
XO
XI
SICP
WRITE TO LAST PHYSICAL LOCATION
0
1 n – 1
READ FROM LAST
PHYSICAL LOCATION
R
tXOL
t
XOH
Figure 11. Expansion-Out
tXOL t XOH
2752 drw 14
tXI tXIR
t
XIS
R
0
Write to first
physical location
1 n – 1
tXIS
Figure 12. Expansion-In
Read from
physical location
2752 drw 15
5.36 9
Page 10
IDT72132, IDT72142
CMOS SERIAL-TO-PARALLEL FIFO 2048 x 9 AND 4096 x 9 COMMERCIAL TEMPERATURE RANGES
OPERATING CONFIGURATIONS
Single Device Configuration
In the standalone case, the SIX line is tied HIGH and not
used. On the first LOW-to-HIGH of the SICP clock, both of the
SERIAL DATA IN
SERIAL INPUT CLOCK
VCC
01234567 01234567
SICP
D7
D8
SICP
SIX
NW D7 D8
8
Data Set lines (D
7, D8) go LOW and a new serial word is
started. The Data Set lines then go HIGH on the equivalent
SICP clock pulse. This continues until the D line connected to
NW
goes HIGH completing the serial word. The cycle is then
repeated with the next LOW-to-HIGH transition of SICP.
SI
Q0-8
XI
PARALLEL DATA OUTPUT
GND
8
0
NW
2752 drw 16
Figure 13. Nine-Bit Word Single Device Configuration
TRUTH TABLES
TABLE 1: RESET AND RETRANSMIT
SINGLE DEVICE CONFIGURATION/WIDTH EXPANSION MODE
Inputs Internal Status Outputs
Mode
Reset 0 X 0 Location Zero Location Zero 0 1 1
Retransmit 1 0 0 Location Zero Unchanged X X X
Read/Write 1 1 0 Increment
NOTE: 2752 tbl 09
1. Pointer will increment if appropriate flag is HIGH.
RS FL/RT XI
Read Pointer Write Pointer
(1)
Increment
(1)
AEF, EF FF HF
XXX
5.36 10
Page 11
IDT72132, IDT72142
CMOS SERIAL-TO-PARALLEL FIFO 2048 x 9 AND 4096 x 9 COMMERCIAL TEMPERATURE RANGES
Width Expansion Configuration
In the cascaded case, word widths of more than 9 bits can
be achieved by using more than one device. By tying the SIX
line of the least significant device HIGH and the SIX of the
subsequent devices to the appropriate Data Set lines of the
SERIAL DATA IN
SI
Q0-7
FIFO #1
NW D7
1 7 8 9 10 14 15 0
SERIAL-IN CLOCK
VCC
SOCP
D OF FIFO #1
7
AND SIX OF
FIFO #2
D OF FIFO #2
7
AND NW TO
FIFO #1 AND
FIFO #2
XI
SICP
SIX
0
previous devices, a cascaded serial word is achieved.
On the first LOW-to-HIGH clock edge of SICP, both the
Data Set lines go LOW. Just as in the standalone case, on
each corresponding clock cycle, the equivalent Data Set line
goes HIGH in order of least to most significant.
8
8
XI
SICP
SI
FIFO #2
SIX
NW D7
Q
0-7
PARALLEL
DATA OUT
8
2752 drw 17
Figure 14. Serial-In to Parallel-Out Data of 16 Bits
5.36 11
Page 12
IDT72132, IDT72142
CMOS SERIAL-TO-PARALLEL FIFO 2048 x 9 AND 4096 x 9 COMMERCIAL TEMPERATURE RANGES
Depth Expansion (Daisy Chain) Mode
The IDT72132/42 can be easily adapted to applications
where the requirements are for greater than 2048/4096 words.
Figure 15 demonstrates Depth Expansion using three
IDT72132/42. Any depth can be attained by adding additional
IDT72132/42 operates in the Depth Expansion configuration
when the following conditions are met:
1. The first device must be designated by grounding the
First Load (FL) control input.
VCC
SIX
FL/RT
SIX
FL/RT
FIFO #1
IDT72142
SI
FIFO #2
IDT72142
SI
SICP
SICP
XO
SICP
V
CC
2. All other devices must have FL in the high state.
3. The Expansion Out (XO) pin and Expansion In (XI) pin
of each device must be tied together.
4. External logic is needed to generate a composite Full
Flag (FF) and Empty Flag (EF). This requires the
OR-ing of all EFs and OR-ing of all FFs (i.e., all must be
set to generate the correct composite
(FF
) or
5. The Retransmit (RT) function and Half-Full Flag (HF)
are not available in the Depth Expansion mode.
Q 0-7
Q
0-7
XI
XI
XO
R
NW
7
D
Q
0-7
R
NW
7
D
R
(EF
).
SI
Figure 15. An 8K x 8 Serial-In Parallel-Out FIFO
2752 drw 18
TABLE 2: RESET AND FIRST LOAD TRUTH TABLE —
DEPTH EXPANSION/COMPOUND EXPANSION MODE
Inputs Internal Status Outputs
Mode
Reset-First 0 0 (1) Location Zero Location Zero 0 1
Device
Reset all 0 1 (1) Location Zero Location Zero 0 1
Other Devices
Read/Write 1 X (1) X X X X
NOTES: 2752 tbl 10
1.XI is connected to
2. RS = Reset Input, FL/RT = First Load/Retransmit, EF = Empty Flag Ouput, FF = Full Flag Output, XI = Expansion Input.
RS FL/RT XI
XO
of the previous device.
Read Pointer Write Pointer
EF FF
5.36 12
Page 13
IDT72132, IDT72142
CMOS SERIAL-TO-PARALLEL FIFO 2048 x 9 AND 4096 x 9 COMMERCIAL TEMPERATURE RANGES
SERIAL INPUT WITH WIDTH AND DEPTH EXPANSION
SERIAL
DATA IN
V
CC
SERIAL
INPUT
CLOCK
CC
SIX
SICP
V
SIX
SICP
SI
D
7
SIX
NW
SICP
R
Q
SI
0-7
D
7
XI XO
XO
XI
SIX
NW
SICP
R
Q
0-7
P
0-7
PARALLEL DATA OUT
Q
P
Q
SI
0-7
0-7
8-15
SI
D
7
D
7
XI XO
XO
XI
NW
R
NW
R
SIX
SICP
SIX
SICP
Q
Q
P
0-7
SI
0-7
16-23
SI
D
7
D
7
XI XO
XO
XI
NW
R
NW
R
READ
2752 drw 19
Figure 16. An 8K x 24 Serial-In, Parallel-Out FIFO Using Six IDT72142s
ORDERING INFORMATION
IDT
XXXXX
Device
Type
X
Power
XXX
Speed
X
Package
X
Process/
Temperature
Range
Blank Commercial (0°C to +70°C)
P Plastic DIP
35
50
(50MHz serial shift rate)
(40MHz serial shift rate)
L Low Power
72132
72142
2048 x 9-Bit Serial-Parallel FIFO
4096 x 9-Bit Serial-Parallel FIFO
Parallel Access Time (tA)
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5.36 13
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