Datasheet IDT72105L25SO, IDT72105L25TP, IDT72105L50SO, IDT72115L25SO, IDT72115L25TP Datasheet (Integrated Device Technology Inc)

Integrated Device Technology, Inc.

CMOS PARALLEL-TO-SERIAL FIFO
256 x 16, 512 x 16, 1024 x 16

IDT72105
IDT72115
IDT72125

FEATURES:

• 25ns parallel port access time, 35ns cycle time

• 45MHz serial output shift rate

• Wide x16 organization offering easy expansion

• Low power consumption (50mA typical)

• Least/Most Significant Bit first read selected by asserting
the FL/DIR pin

• Four memory status flags: Empty, Full, Half-Full, and
Almost-Empty/Almost-Full

• Dual-Port zero fall-through architecture

• Available in 28-pin 300 mil plastic DIP and 28-pin SOIC

• Industrial temperature range (-40oC to +85oC) is avail­able, tested to military electrical specifications

DESCRIPTION:

The IDT72105/72115/72125s are very high-speed, low­power,dedicated, parallel-to-serial FIFOs. These FIFOs
possess a 16-bit parallel input port and a serial output port with
256, 512 and 1K word depths, respectively.

The ability to buffer wide word widths (x16) make these
FIFOs ideal for laser printers, FAX machines, local area
networks (LANs), video storage and disk/tape controller
applications.

Expansion in width and depth can be achieved using
multiple chips. IDT’s unique serial expansion logic makes this
possible using a minimum of pins.

The unique serial output port is driven by one data pin (SO)
and one clock pin (SOCP). The Least Significant or Most
Significant Bit can be read first by programming the DIR pin
after a reset.

Monitoring the FIFO is eased by the availability of four
status flags: Empty, Full, Half-Full and Almost-Empty/Almost­Full. The Full and Empty flags prevent any FIFO data overflow
or underflow conditions. The Half-Full Flag is available in both
single and expansion mode configurations. The Almost-Empty/
Almost-Full Flag is available only in a single device mode.

The IDT72105/15/25 are fabricated using IDT’s leading
edge, submicron CMOS technology. Military grade product is
manufactured in compliance with the latest revision of Mil­STD-883, Class B.

FUNCTIONAL BLOCK DIAGRAM

D

RS

RESET

LOGIC

RSIX

RSOX

FL/DIR

The IDT logo is a registered trademark of Integrated Device Technology, Inc.
FAST is a trademark of National Semiconductor Co.

W

WRITE

POINTER

EXPANSION

LOGIC

SERIAL OUTPUT

SOCP SO

COMMERCIAL TEMPERATURE RANGE DECEMBER 1996

1996 Integrated Device Technology, Inc. DSC-2665/6

For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.

0–15

16

RAM

ARRAY
256 x 16
512 x 16

1024 x 16

LOGIC

5.35 1

READ

POINTER

FLAG

LOGIC

FF
EF
HF
AEF

2665 drw 01

IDT72105, IDT72115, IDT72125,
256 x 16, 512 x 16, 1024 x 16 PARALLEL-TO-SERIAL CMOS FIFO

PIN CONFIGURATION

COMMERCIAL TEMPERATURE RANGES

W

D
D
D

D
D
D
D
D

EF

FF
HF

RSIX

GND

1
2

0

3

1

4

2

5

3

6

4
5
6
7

7
8
9
10
11
12
13
14

P28-2

SO28-3

28
27
26
25
24
23
22
21
20
19
18
17
16
15

Vcc

D

15

D

14

D

13

D

12

D

11

D

10

D

9

D

8

RS

SO
SOCP
RSOX/

FL

/DIR

2665 drw 02a

AEF

DIP/SOIC

TOP VIEW

PIN DESCRIPTIONS

Symbol Name I/O Description

D0–D

15

RS

W

SOCP Serial Output

FL

/DIR First Load/

RSIX Read Serial In

SO Serial Output O Serial data is output on the Serial Output (SO) pin. Data is clocked out LSB or MSB depending

FF

EF

HF

RSOX/

V

CC

GND Ground Single ground of 0V.

Inputs I Data inputs for 16-bit wide data.

Reset I When RS is set low, internal READ and WRITE pointers are set to the first location of the RAM

array. FF and HF go HIGH. EF and

AEF

go LOW. A reset is required before an initial WRITE
after power-up. W must be high during the RS cycle. Also the First Load pin (FL) is programmed
only during Reset.

Write I A write cycle is initiated on the falling edge of WRITE if the Full Flag (FF) is not set. Data set-up

and hold times must be adhered to with respect to the rising edge of WRITE. Data is stored in the
RAM array sequentially and independently of any ongoing read operation.

I A serial bit read cycle is initiated on the rising edge of SOCP if the Empty Flag (EF) is not set. In

Clock

both Depth and Serial Word Width Expansion modes, all of the SOCP pins are tied together.

I This is a dual purpose input used in the width and depth expansion configurations. The First

Direction

Load (FL) function is programmed only during Reset (RS) and a LOW on FL indicates the first
device to be loaded with a byte of data. All other devices should be programmed HIGH. The
Direction (DIR) pin controls shift direction after Reset and tells the device whether to read out the
Least Significant or Most Significant bit first.

I In the single device configuration, RSIX is set HIGH. In depth expansion or daisy chain

Expansion

expansion, RSIX is connected to RSOX (expansion out) of the previous device.

on the Direction pin programming. During Expansion the SO pins are tied together.

Full Flag O When FF goes LOW, the device is full and further WRITE operations are inhibited. When FF is

HIGH, the device is not full.

Empty Flag O When EF goes LOW, the device is empty and further READ operations are inhibited. When EF is

HIGH, the device is not empty.

Half-Full Flag O When HF is LOW, the device is more than half-full. When HF is HIGH, the device is empty to

half-full.

AEF

Read Serial
Out Expansion
Almost-Empty,
Almost-Full
Flag

O This is a dual purpose output. In the single device configuration (RSIX HIGH), this is an

output pin. When

AEF

is HIGH, the device is 1/8-full up to 7/8-full. In the Expansion configuration (RSOX

AEF

is LOW, the device is empty-to-(1/8 full -1) or (7/8 full +1)-to-full. When

connected to RSIX of the next device) a pulse is sent from RSOX to RSIX to coordinate the
width, depth or daisy chain expansion.

Power Supply Single power supply of 5V.

AEF

2665 tbl 01

5.35 2

IDT72105, IDT72115, IDT72125,
256 x 16, 512 x 16, 1024 x 16 PARALLEL-TO-SERIAL CMOS FIFO

COMMERCIAL TEMPERATURE RANGE

STATUS FLAGS

Number of Words in FIFO

IDT72105 IDT72115 IDT72125

FF

FF

AEF

AEF

HF

HF

0 0 0 HLHL

1–31 1–63 1–127 H L H H

32–128 64–256 128–512 H H H H
129–224 257–448 513–896 H H L H
225–255 449–511 897–1023 H L L H

256 512 1024 L L L H

RECOMMENDED DC OPERATING

ABSOLUTE MAXIMUM RATINGS

Symbol Rating Commercial Unit

V

TERM

T

A

T

BIAS

T

STG

I

OUT

NOTE: 2665 tbl 03

1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.

Terminal Voltage
with Respect to
GND

Operating
Temperature

Temperature

Under Bias
Storage

Temperature

DC Output
Current

–0.5 to + 7.0 V

–55 to + 125

(1)

0 to +70

–55 to +125

50 mA

CONDITIONS

Symbol Parameter Min. Typ. Max. Unit

VCC Supply Voltage 4.5 5.0 5.5 V

°

C

°

C

°

C

GND Supply Voltage 0 0 0 V
VIH Input High Voltage 2.0 — — V

(1)

VIL

NOTE: 2665 tbl 04

1. 1.5V undershoots are allowed for 10ns once per cycle.

Input Low Voltage — — 0.8 V

EF

EF

2665 tbl 02

DC ELECTRICAL CHARACTERISTICS

(Commercial VCC = 5.0V ± 10%, TA = 0°C to +70°C)

Symbol Parameter

(1)

I

IL

(2)

I

OL

V

OH

V

OL

(3)

I

CC1

(3)

I

CC2

(3,4,7)

I

CC3

NOTES:

1. Measurements with 0.4V ≤ VIN ≤ VCC.

2. SOCP = VIL, 0.4 ≤ VOUT ≤ VCC.

3. I

CC measurements are made with outputs open.

4.RS = FL/DIR = W = V

5. For SO, I

6. For SO, I

7. Measurements are made after reset.

Input Leakage Current (Any Input) –1 — 1

Output Leakage Current –10 — 10

Output Logic "1" Voltage I

Output Logic "0" Voltage I

OUT
OUT

= –2mA
= 8mA

(5)

(6)

Power Supply Current — 50 100 mA
Average Standby Current

IH

(W = RS = FL/DIR = V

)(SOCP = VIL)

Power Down Current — 1 6 mA

OUT = -4mA.
OUT = 16mA.

CC - 0.2V; SOCP = 0.2V; all other inputs ≥ VCC - 0.2 or ≤ 0.2V.

IDT72105/IDT72115/ IDT72125

Commercial

Min. Typ. Max. Unit

µ

A

µ

A

2.4 — — V
— — 0.4 V

—4 8mA

2665 tbl 05

5.35 3

IDT72105, IDT72115, IDT72125,
256 x 16, 512 x 16, 1024 x 16 PARALLEL-TO-SERIAL CMOS FIFO

COMMERCIAL TEMPERATURE RANGES

AC ELECTRICAL CHARACTERISTICS

(Commercial: VCC = 5V±10%, TA = 0°C to +70°C)

COM'L

72105L25 72105L50
72115L25 72115L50

Symbol Parameter Figure Min. Max. Min. Max. Unit

tS Parallel Shift Frequency — — 28.5 — 15 MHz
tSOCP Serial Shift Frequency — — 50 — 40 MHz

PARALLEL INPUT TIMINGS

tWC Write Cycle Time 2 35 — 65 — ns
tWPW Write Pulse Width 2 25 — 50 — ns
tWR Write Recovery Time 2 10 — 15 — ns
tDS Data Set-up Time 2 12 — 15 — ns
tDH Data Hold Time 2 0 — 2 — ns
tWEF Write High to EF HIGH 5, 6 — 35 — 45 ns
tWFF Write Low to FF LOW 4, 7 — 35 — 45 ns
tWF Write Low to Transitioning HF,

AEF

8 — 35 — 45 ns

tWPF Write Pulse Width After FF HIGH 7 25 — 50 — ns

SERIAL OUTPUT TIMINGS

tSOCP Serial Clock Cycle Time 3 20 — 25 — ns
tSOCW Serial Clock Width HIGH/LOW 3 8 — 10 — ns
tSOPD SOCP Rising Edge to SO Valid Data 3 — 14 — 15 ns

(1)

(1)

3 3 14 3 15 ns
3 3 14 3 15 ns

tSOHZ SOCP Rising Edge to SO at High-Z
tSOLZ SOCP Rising Edge to SO at Low-Z
tSOCEF SOCP Rising Edge to EF LOW 5, 6 — 35 — 45 ns
tSOCFF SOCP Rising Edge to FF HIGH 4, 7 — 35 — 45 ns
tSOCF SOCP Rising Edge to Transitioning

8 — 35 — 45 ns

HF, AEF

tREFSO SOCP Delay After EF HIGH 6 35 — 65 — ns

RESET TIMINGS

tRSC Reset Cycle Time 1 35 — 65 — ns
tRS Reset Pulse Width 1 25 — 50 — ns
tRSS Reset Set-up Time 1 25 — 50 — ns
tRSR Reset Recovery Time 1 10 — 15 — ns

EXPANSION MODE TIMINGS

tFLS
tFLH
tDIRS DIR Set-up Time to SOCP Rising

FL

Set-up Time to RS Rising Edge 9 7 — 8 — ns

FL

Hold Time to RS Rising Edge 9 0 — 2 — ns

9 10 — 12 — ns

Edge

tDIRH DIR Hold Time from SOCP Rising

95—5 —ns

Edge

tSOXD1 SOCP Rising Edge to RSOX Rising

9 — 15 — 17 ns

Edge

tSOXD2 SOCP Rising Edge to RSOX Falling

9 — 15 — 17 ns

Edge

tSIXS RSIX Set-up Time to SOCP Rising

95— 8 —ns

Edge

tSIXPW RSIX Pulse Width 9 10 — 15 — ns

NOTE: 2665 tbl 06

1. Values guaranteed by design.

72125L25 72125L50

5.35 4

IDT72105, IDT72115, IDT72125,
256 x 16, 512 x 16, 1024 x 16 PARALLEL-TO-SERIAL CMOS FIFO

COMMERCIAL TEMPERATURE RANGE

AC TEST CONDITIONS

Input Pulse Levels GND to 3.0V
Input Rise/Fall Times 5ns
Input Timing Reference Levels 1.5V
Output Reference Levels 1.5V
Output Load See Figure A

2665 tbl 07

CAPACITANCE (TA = +25°C, f = 1.0MHz)

Symbol Parameter

CIN Input Capacitance VIN = 0V 10 pF
COUT Output

Capacitance

NOTE: 2665 tbl 08

1. This parameter is sampled and not 100% tested.

(1)

Conditions Max. Unit

VOUT = 0V 12 pF

FUNCTIONAL DESCRIPTION

Parallel Data Input

The device must be reset before beginning operation so
that all flags are set to their initial state. In width or depth
expansion the First Load pin (FL) must be programmed to
indicate the first device.

The data is written into the FIFO in parallel through the D

15 input data lines. A write cycle is initiated on the falling edge

of the Write (W) signal provided the Full Flag (FF) is not
asserted. If the W signal changes from HIGH-to-LOW and the
Full Flag (FF) is already set, the write line is internally inhibited
internally from incrementing the write pointer and no write
operation occurs.

Data set-up and hold times must be met with respect to the

0–

5V

1.1K

Ω

TO

OUTPUT

PIN

680

Ω

30pF

*

2665 drw 03

or equivalent circuit

Figure A. Output Load

*Includes jig and scope capacitances.

rising edge of Write. On the rising edge of W, the write pointer
is incremented. Write operations can occur simultaneously or
asynchronously with read operations.

Serial Data Output

The serial data is output on the SO pin. The data is clocked
out on the rising edge of SOCP providing the Empty Flag (EF)
is not asserted. If the Empty Flag is asserted then the next data
word is inhibited from moving to the output register and being
clocked out by SOCP.

The serial word is shifted out Least Significant Bit or Most
Significant Bit first, depending on the FL/DIR level during
operation. A LOW on DIR will cause the Least Significant Bit
to be read out first. A HIGH on DIR will cause the Most
Significant Bit to be read out first.

t

RSC

t

RS

RS

t

RSS

t

RSR

W

t

RSC

AEF, EF

t

RSC

HF, FF

t

SOCP

RSS

NOTE 2

t

FLS

t

t

FLH

RSR

FL/DIR

NOTES:

1. EF, FF, HF and

2. SOCP should be in the steady LOW or HIGH during tRSS. The first LOW-HIGH (or HIGH-LOW) transition can begin after tRSR.

AEF

may change status during Reset, but flags will be valid at t

Figure 1. Reset

RSC.

FLAG
STABLE

FLAG
STABLE

2665 drw 04

5.35 5

IDT72105, IDT72115, IDT72125,
256 x 16, 512 x 16, 1024 x 16 PARALLEL-TO-SERIAL CMOS FIFO

t

WPW

W

D

0–15

COMMERCIAL TEMPERATURE RANGES

t

WC

t

WR

Figure 2. Write Operation

1/t

SOCP

0 1 n–1

SOCP

t

SOCW

SO

(First Device in Width Expansion Mode)

t

SOHZ

SO

(Single Device Mode or Second
Device in Width Expansion Mode)

NOTE:

1. In Single Device Mode, SO will not tri-state except after reset.

LAST WRITE

IGNORED

WRITE

t

SOLZ

Figure 3. Read Operation

SOCP

t

DH

t

SOPD

t

SOCW

t

DS

FIRST READ ADDITIONAL READS FIRST WRITE

0

1 n–1

0

1 n–1

2665 drw 05

2665 drw 06

W

t

WFF

FF

Figure 4. Full Flag from Last Write to First Read

LAST READ NO READ FIRST WRITE

W

1 n–1 0 1 n–1

0

NOTE 1

SOCP

t

SOCEF

EF

t

SOPD

VALID

SO

NOTE:

1. SOCP should not be clocked until EF goes HIGH.

Figure 5. Empty Flag from Last Read to First Write

t

SOCFF

t

SOCFF

VALID

2665 drw 07

ADDITIONAL

WRITES FIRST READ

VALID

2665 drw 08

5.35 6

IDT72105, IDT72115, IDT72125,
256 x 16, 512 x 16, 1024 x 16 PARALLEL-TO-SERIAL CMOS FIFO

DATA

IN

W

t

EF

SOCP

NOTE 1

WEF

t

REFSO

COMMERCIAL TEMPERATURE RANGE

t

SOCEF

0 1 n–1

NOTE 2

t

SOLZ

SO

t

NOTE:

1. Once EF has gone LOW and the last bit of the final word has been shifted out, SOCP should not be clocked until EF goes HIGH.

2. In Single Device Mode, SO will not tri-state except after Reset. It will retain the last valid data.

Figure 6. Empty Boundary Condition Timing

0

1 n–1

SOPD

SOCP

t

SOCFF

t

WFF

FF

t

WPF

W

t

DS

DATA

IN

t

NOTE 1

SOPD

SO

NOTE:

1. Single Device Mode will not tri-state but will retain the last valid data.

DATAINVALID

DATA

OUT

t

DH

VALID

NOTE 1

2665 drw 09

2665 drw 10

HF

SOCP

AEF

AEF

Figure 7. Full Boundary Condition Timing

W

HALF-FULL (1/2) HALF-FULL

HALF-FULL + 1

t

WF

t

WF

7/8 FULL 7/8 FULL

ALMOST-EMPTY

(1/8 FULL – 1)

Figure 8. Half-Full, Almost-Full and Almost-Empty Timings

ALMOST-FULL (7/8 FULL + 1)

1/8 FULL

5.35 7

t

SOCF

t

SOCF

ALMOST-EMPTY

(1/8 FULL – 1)

2665 drw 11

IDT72105, IDT72115, IDT72125,
256 x 16, 512 x 16, 1024 x 16 PARALLEL-TO-SERIAL CMOS FIFO

RS

SOCP

t

FLS

FL/DIR

t

FLH

COMMERCIAL TEMPERATURE RANGES

15 0

t

DIRS

t

DIRH

RSOX

RSIX

Figure 9. Serial Read Expansion

OPERATING CONFIGURATIONS

Single Device Mode

The device must be reset before beginning operation so
that all flags are set to location zero. In the standalone case,
the RSIX line is tied HIGH and indicates single device opera­tion to the device. The RSOX/
outputs the Almost-Empty and Almost-Full Flag.

AEF

pin defaults to

AEF

and

PARALLEL DATA

t

SOXD1

t

SIXS

t

RSIXPW

t

SOXD2

2665 drw 12

Width Expansion Mode

In the cascaded case, word widths of more than 16 bits can
be achieved by using more than one device. By tying the
RSOX and RSIX pins together, as shown in Figure 11, and
programming which is the Least Significant Device, a cas­caded serial word is achieved. The Least Significant Device
is programmed by a LOW on the FL/DIR pin during reset. All
other devices should be programmed HIGH on the FL/DIR pin
at reset.

IN

Vcc

SERIAL OUTPUT CLOCK

D

0–15

RSIX
SOCP

Figure 10. Single Device Configuration

RSOX/AEF

SO

ALMOST-EMPTY/FULL FLAG

SERIAL DATA

OUT

2665 drw 13

5.35 8

IDT72105, IDT72115, IDT72125,
256 x 16, 512 x 16, 1024 x 16 PARALLEL-TO-SERIAL CMOS FIFO

Inputs Internal Status Outputs

RS

Mode

Reset 0 X X Location Zero Location Zero 0 1 1
Read/Write 1 X 0,1 Increment

NOTE: 2665 tbl 09

1. Pointer will increment if appropriate flag is HIGH.

RS

FL

FL

Table 1. Reset and First Load Truth Table–Single Device Configuration

DIR Read Pointer Write Pointer

(1)

Increment

(1)

COMMERCIAL TEMPERATURE RANGE

FF

AEF

,

EF

AEF

EF

XXX

FF

HF

HF

The Serial Data Output (SO) of each device in the serial
word must be tied together. Since the SO pin is three stated,
only the device which is currently shifting out is enabled and
driving the 1-bit bus. NOTE: After reset, the level on the

FL

/DIR pin decides if the Least Significant or Most Significant

PARALLEL DATA

D

0–15

W

RSIX

IN

SOCP

FIFO #1

RSOX

LOW AT RESET

FL/DIR

SO

EF
HF
FF

Figure 11. Width Expansion for 32-bit Parallel Data In

D

16–31

W

RSIX

Bit is read first out of each device.

The three flag outputs, Empty (EF), Half-Full (HF) and
Full (FF), should be taken from the Most Significant Device (in
the example, FIFO #2). The Almost-Empty/Almost-Full flag is
not available. The RSOX pin is used for expansion.

SERIAL OUTPUT CLOCK

HIGH AT RESET

SOCP

FIFO #2

RSOX

FL/DIR

SO

EF
HF
FF

EMPTY FLAG

HALF-FULL FLAG
FULL FLAG

SERIAL DATA

2665 drw 14

OUT

Depth Expansion (Daisy Chain) Mode

The IDT72105/15/25 can easily be adapted to applications
requiring greater than 1024 words. Figure 12 demonstrates
Depth Expansion using three IDT72105/15/25s and an
IDT74FCT138 Address Decoder. Any depth can be attained
by adding additional devices. The Address Decoder is neces­sary to determine which FIFO is being written. A word of data
must be written sequentially into each FIFO so that the data
will be read in the correct sequence. The IDT72105/15/25
operates in the Depth Expansion Mode when the following
conditions are met:

1. The first device must be programmed by holding FL LOW

at Reset. All other devices must be programmed by holding

FL

HIGH at reset.

2. The Read Serial Out Expansion pin (RSOX) of each device

must be tied to the Read Serial In Expansion pin (RSIX) of

the next device (see Figure 12).

3. External logic is needed to generate composite Empty,
Half-Full and Full Flags. This requires the OR-ing of all EF,

HF

and FF Flags.

4. The Almost-Empty and Almost-Full Flag is not available
due to using the RSOX pin for expansion.

Compound Expansion (Daisy Chain) Mode

The IDT72105/15/25 can be expanded in both depth and
width as Figure 13 indicates:

1. The RSOX-to-RSIX expansion signals are wrapped
around sequentially.

2. The write (W) signal is expanded in width.

3. Flag signals are only taken from the Most Significant
Devices.

4. The Least Significant Device in the array must be
programmed with a LOW on FL/DIR during reset.

5.35 9

IDT72105, IDT72115, IDT72125,
256 x 16, 512 x 16, 1024 x 16 PARALLEL-TO-SERIAL CMOS FIFO

COMMERCIAL TEMPERATURE RANGES

LOW AT RESET

PARALLEL DATA

ADDRESS
DECODER
74FCT138

00
01
10

SERIAL OUTPUT CLOCK

IN

D

0–15

W

SOCP

RSIX

FIFO #1

RSOX

FL/DIR

SO

EF
HF
FF

EMPTY
FLAG

HIGH AT RESET

D

0–15

W

SOCP

RSIX

FIFO #2

RSOX

FL/DIR

SO

EF
HF
FF

HALF-FULL
FLAG

HIGH AT RESET

D

0–15

W

SOCP

RSIX

FIFO #3

RSOX

FL/DIR

SO

EF
HF
FF

FULL
FLAG

SERIAL DATA

OUT

2665 drw 15

Figure 12. A 3K x 16 Parallel-to-Serial FIFO using the IDT72125

Inputs Internal Status Outputs

Mode

RS

RS

FL

FL

DIR Read Pointer Write Pointer

EF

EF

HFHF,

FF

FF

Reset-First Device 0 0 X Location Zero Location Zero 0 1
Reset All Other Devices 0 1 X Location Zero Location Zero 0 1
Read/Write 1 X 0,1 X X X X

NOTE: 2665 tbl 10

1. RS = Reset Input, FL/FIR = First Load/Direction, EF = Empty Flag Output, HF = Half- Full Flag Output, FF = Full Flag Output.

Table 2. Reset and First Load Truth Table–Width/Depth Compound Expansion Mode

5.35 10

IDT72105, IDT72115, IDT72125,
256 x 16, 512 x 16, 1024 x 16 PARALLEL-TO-SERIAL CMOS FIFO

ADDRESS
DECODER
74FCT138

PARALLEL DATA

IN

00 01 10

COMMERCIAL TEMPERATURE RANGE

SERIAL OUTPUT CLOCK
LOW ON RESET
HIGH ON RESET

SOCP

D

0–15

W

RSIX RSOX

SOCP

D

0–15

W

RSIX RSOX

SOCP

D

0–15

W

RSIX RSOX

FIFO #1

FIFO #3

FIFO #5

FL

FL

FL

/DIR

/DIR

/DIR

SO

SO

SO

EF

HF

FF

EF

HF

FF

EF

HF

FF

D

W

D

W

D

W

16–31

RSIX

16–31

RSIX

16–31

RSIX

SOCP

SOCP

SOCP

FIFO #2

RSOX

FIFO #4

RSOX

FIFO #6

RSOX

FL

FL

FL

/DIR

/DIR

/DIR

SO

SO

SO

EF

HF

FF

EF

HF

FF

EF

HF

FF

EMPTY
FLAG

HALF-FULL
FLAG

FULL
FLAG

SERIAL DATA

2665 drw 16

OUT

Figure 13. A 3K x 32 Parallel-to-Serial FIFO using the IDT72125

5.35 11

IDT72105, IDT72115, IDT72125,
256 x 16, 512 x 16, 1024 x 16 PARALLEL-TO-SERIAL CMOS FIFO

ORDERING INFORMATION

IDT

XXXXX

Device

Type

X

Power

X

Speed

X

Package

X

Process/

Temperature

Range

COMMERCIAL TEMPERATURE RANGES

BLANK

TP

SO

25
50

Commercial (0°C to +70°C)

Plastic THINDIP (300mil)

Small Outline (Gull Wing)

(50 MHz serial shift rate)
(40MHz serial shift rate)

L Low Power

72105
72115
72125

256 x 16-Bit Parallel-to-Serial FIFO
512 x 16-Bit Parallel-to-Serial FIFO
1024 x 16-Bit Parallel-to-Serial FIFO

Commercial only
Parallel Access
Time (tA) in ns

2665 drw 17

5.35 12