Datasheet IDT7207L15D, IDT7207L15J, IDT7207L15P, IDT7207L20D, IDT7207L20DB Datasheet (Integrated Device Technology Inc)
...Page 1
Integrated Device Technology, Inc.
CMOS ASYNCHRONOUS FIFO
32,768 x 9
IDT7207
FEATURES:
• 32768 x 9 storage capacity
• High-speed: 15ns access time
• Low power consumption
— Active: 660mW (max.)
— Power-down: 44mW (max.)
• Asynchronous and simultaneous read and write
• Fully expandable in both word depth and width
• Pin and functionally compatible with IDT720x family
• Status Flags: Empty, Half-Full, Full
• Retransmit capability
• High-performance CMOS technology
• Military product compliant to MIL-STD-883, Class B
• Industrial temperature range (-40oC to +85oC) is available, tested to military electrical specifications
FUNCTIONAL BLOCK DIAGRAM
W
WRITE
CONTROL
DESCRIPTION:
The IDT7207 is a monolithic dual-port memory buffer with
internal pointers that load and empty data on a first-in/first-out
basis. The device uses Full and Empty flags to prevent data
overflow and underflow and expansion logic to allow for
unlimited expansion capability in both word size and depth.
Data is toggled in and out of the device through the use of
the Write (W) and Read (R) pins.
The devices 9-bit width provides a bit for a control or parity
at the user’s option. It also features a Retransmit (RT) capability that allows the read pointer to be reset to its initial position
when RT is pulsed LOW. A Half-Full Flag is available in the
single device and width expansion modes.
The IDT7207 is fabricated using IDT’s high-speed CMOS
technology. It is designed for applications requiring asynchronous and simultaneous read/writes in multiprocessing, rate
buffering, and other applications.
Military grade product is manufactured in compliance with
the latest revision of MIL-STD-883, Class B.
DATA INPUTS
(D –D
0
)
8
RAM ARRAY
32,768 x 9
DATA OUTPUTS
(Q –Q
0
8
)
EF
FF
READ
POINTER
RS
RESET
LOGIC
FL/RT
XO/HF
3140 drw 01
R
XI
The IDT logo is a registered trademark of Integrated Device Techology, Inc.
READ
CONTROL
EXPANSION
WRITE
POINTER
THREESTATE
BUFFERS
FLAG
LOGIC
LOGIC
MILITARY AND COMMERCIAL TEMPERATURE RANGES DECEMBER 1996
1996 Integrated Device Technology, Inc. DSC-3140/2
For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.
5.05 1
Page 2
IDT7207 CMOS ASYNCHRONOUS FIFO
32,768 x 9 MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
1
W
2
D
8
3
D
3
4
2
D
5
D
1
6
D0
7
XI
8
FF
9
0
Q
10
Q1
11
Q
2
12
Q3
13
Q
8
GND
14
TOP VIEW
ABSOLUTE MAXIMUM RATINGS
Symbol Rating Commercial Military Unit
V
TERM Terminal –0.5 to + 7.0 –0.5 to +7.0 V
Voltage with
Respect to
GND
T
A Operating 0 to +70 –55 to +125 ° C
Temperature
T
BIAS Temperature –55 to +125 –65 to +135 ° C
Under Bias
T
STG Storage –55 to + 125 –65 to +155 ° C
Temperature
I
OUT DC Output 50 50 mA
Current
NOTE: 3140 tbl 01
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
P28-1
D28-1
DIP
28
Vcc
27
D
4
26
D
5
25
6
D
24
D
7
23
FL/RT
22
RS
21
EF
20
XO/HF
19
Q
7
18
Q6
17
5
Q
16
Q
4
15
R
3140 drw 02
(1)
INDEX
2
D
D1
D0
XI
FF
Q
0
Q1
NC
Q
2
5
6
7
8
9
10
11
12
13
D3D8
432
J32-1
L32-1
141516
3
8
Q
Q
NC
W
1
&
171819
NC
GND
Vcc
32
R
D4
D
30
31
29
D
6
28
D7
27
NC
26
FL/RT
25
RS
24
EF
23
XO/HF
22
Q
7
21
Q6
20
5
4
Q
Q
3140 drw 03
5
PLCC/LCC
TOP VIEW
RECOMMENDED DC OPERATING
CONDITIONS
Symbol Parameter Min. Typ. Max. Unit
V
CCM Military Supply 4.5 5.0 5.5 V
Voltage
CCC Commercial Supply 4.5 5.0 5.5 V
V
Voltage
GND Supply Voltage 0 0 0 V
(1)
V
IH
V
IH
V
IL
NOTE: 3140 tbl 02
1. 1.5V undershoots are allowed for 10ns once per cycle.
Input High Voltage 2.0 — — V
Commercial
(1)
Input High Voltage 2.2 — — V
Military
(1)
Input Low Voltage — — 0.8 V
Commercial and
Military
DC ELECTRICAL CHARACTERISTICS FOR THE 7207
(Commercial: VCC = 5.0V±10%, TA = 0°C to +70°C; Military: VCC = 5.0V±10%, TA = –55°C to +125°C)
IDT7207 IDT7207
Commercial Military
t
A = 15, 20, 25, 35, 50 ns tA = 20, 30, 50 ns
Symbol Parameter Min. Typ. Max. Min. Typ. Max. Unit
(1)
LI
I
(2)
LO
I
OH Output Logic “1” Voltage IOH = –2mA 2.4 — — 2.4 — — V
V
OL Output Logic “0” Voltage IOL = 8mA — — 0.4 — — 0.4 V
V
(3)
CC1
I
(3)
CC2
I
CC3(L)
I
NOTES: 3140 tbl 04
1. Measurements with 0.4 ≤ VIN ≤ VCC.
2. R ≥ V
CC measurements are made with outputs open (only capacitive loading).
3. I
4. Tested at f = 20MHz.
Input Leakage Current (Any Input) –1 — 1 –1 — 1 µA
Output Leakage Current –10 — 10 –10 — 10 µA
Active Power Supply Current — — 120
(4)
— — 150
(4)
Standby Current (R=W=RS=FL/RT=VIH)——12— —25mA
(3)
Power Down Current (All Input = VCC - 0.2V) — — 8 — — 12 mA
IH, 0.4 ≤ VOUT ≤ VCC.
5.05 2
mA
Page 3
IDT7207 CMOS ASYNCHRONOUS FIFO
32,768 x 9 MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS
(1)
(Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C; Military: VCC = 5V ± 10%, TA = –55°C to +125°C)
Com'l Com'l & Mil. Com'l Military Com'l Com'l & Mil.
7207L15 7207L20 7207L25 7207L30 7207L35 7207L50
Symbol Parameters Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
fS Shift Frequency — 40 — 33.3 — 28.5 — 25 — 22.2 — 15 MHz
tRC Read Cycle Time 25 — 30 — 35 — 40 — 45 — 65 — ns
tA Access Time — 15 — 20 — 25 — 30 — 35 — 50 ns
tRR Read Recovery Time 10 — 10 — 10 — 10 — 10 — 15 — ns
tRPW Read Pulse Width
tRLZ Read LOW to Data Bus LOW
tWLZ Write HIGH to Data Bus Low-Z
tDV Data Valid from Read HIGH 5 — 5 — 5 — 5 — 5 — 5 — ns
tRHZ Read HIGH to Data Bus High-Z
tWC Write Cycle Time 25 — 30 — 35 — 40 — 45 — 65 — ns
tWPW Write Pulse Width
tWR Write Recovery Time 10 — 10 — 10 — 10 — 10 — 15 — ns
tDS Data Set-up Time 11 — 12 — 15 — 18 — 18 — 30 — ns
tDH Data Hold Time 0 — 0 — 0 — 0 — 0 — 5 — ns
tRSC Reset Cycle Time 25 — 30 — 35 — 40 — 45 — 65 — ns
tRS Reset Pulse Width
tRSS Reset Set-up Time
tRTR Reset Recovery Time 10 — 10 — 10 — 10 — 10 — 15 — ns
tRTC Retransmit Cycle Time 25 — 30 — 35 — 40 — 45 — 65 — ns
tRT Retransmit Pulse Width
tRTS Retransmit Set-up Time
tRSR Retransmit Recovery Time 10 — 10 — 10 — 10 — 10 — 15 — ns
tEFL Reset to EF LOW — 25 — 30 — 35 — 40 — 45 — 65 ns
tHFH, tFFH Reset to HF and FF HIGH — 25 — 30 — 35 — 40 — 45 — 65 ns
tRTF Retransmit LOW to Flags Valid — 25 — 30 — 35 — 40 — 45 — 65 ns
tREF Read LOW to EF LOW — 15 — 20 — 25 — 30 — 30 — 45 ns
tRFF Read HIGH to FF HIGH — 15 — 20 — 25 — 30 — 30 — 45 ns
tRPE Read Pulse Width after EF HIGH 15 — 20 — 25 — 30 — 35 — 50 — ns
tWEF Write HIGH to EF HIGH — 15 — 20 — 25 — 30 — 30 — 45 ns
tWFF Write LOW to FF LOW — 15 — 20 — 25 — 30 — 30 — 45 ns
tWHF Write LOW to HF Flag LOW — 25 — 30 — 35 — 40 — 45 — 65 ns
tRHF Read HIGH to HF Flag HIGH — 25 — 30 — 35 — 40 — 45 — 65 ns
tWPF Write Pulse Width after FF HIGH 15 — 20 — 25 — 30 — 35 — 50 — ns
tXOL Read/Write LOW to XO LOW — 15 — 20 — 25 — 30 — 35 — 50 ns
tXOH Read/Write HIGH to XO HIGH — 15 — 20 — 25 — 30 — 35 — 50 ns
tXI XI Pulse Width
tXIR XI Recovery Time 10 — 10 — 10 — 10 — 10 — 10 — ns
tXIS XI Set-up Time 10 — 10 — 10 — 10 — 15 — 15 — ns
(2)
(2)
(2)
(3)
(2)
(3)
(2)
15 — 20 — 25 — 30 — 35 — 50 — ns
(3)
5 — 5 — 5—5—5 — 10—ns
(3, 4)
5 — 5 — 5—5—10—15—ns
(3)
— 15 — 15 — 18 — 20 — 20 — 30 ns
15 — 20 — 25 — 30 — 35 — 50 — ns
15 — 20 — 25 — 30 — 35 — 50 — ns
15 — 20 — 25 — 30 — 35 — 50 — ns
15 — 20 — 25 — 30 — 35 — 50 — ns
15 — 20 — 25 — 30 — 35 — 50 — ns
15 — 20 — 25 — 30 — 35 — 50 — ns
NOTES: 3140 tbl 05
1. Timings referenced as in AC Test Conditions.
2. Pulse widths less than minimum are not allowed.
3. Values guaranteed by design, not currently tested.
4. Only applies to read data flow-through mode.
5.05 3
Page 4
IDT7207 CMOS ASYNCHRONOUS FIFO
32,768 x 9 MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
CAPACITANCE
Symbol Parameter Condition Max. Unit
(1)
C
IN
C
OUT
NOTES: 3140 tbl 08
1. This parameter is sampled and not 100% tested.
2. With output deselected.
Input Capacitance V IN = 0V 10 pF
(1,2)
Output Capacitance VOUT = 0V 10 pF
(1)
(TA = +25°C, f = 1.0 MHz)
GND to 3.0V
5ns
1.5V
1.5V
See Figure 1
3140 tbl 07
SIGNAL DESCRIPTIONS
Inputs:
DATA IN (D0–D8) — Data inputs for 9-bit wide data.
Controls:
RESET (
(RS) input is taken to a LOW state. During reset, both internal
read and write pointers are set to the first location. A reset is
required after power-up before a write operation can take place.
Both the Read Enable (
be in the HIGH state during the window shown in Figure 2
(i.e. tRSS before the rising edge of
change until tRSR after the rising edge of
WRITE ENABLE (
edge of this input if the Full Flag (FF) is not set. Data set-up and
hold times must be adhered-to, with respect to the rising edge
of the Write Enable (W). Data is stored in the RAM array
sequentially and independently of any on-going read operation.
After half of the memory is filled, and at the falling edge of the
next write operation, the Half-Full Flag (HF) will be set to LOW,
and will remain set until the difference between the write pointer
and read pointer is less-than or equal to one-half of the total
memory of the device. The Half-Full Flag (HF) is reset by the
rising edge of the read operation.
To prevent data overflow, the Full Flag (FF) will go LOW on
the falling edge of the last write signal, which inhibits further write
operations. Upon the completion of a valid read operation, the
Full Flag (FF) will go HIGH after t
to begin. When the FIFO is full, the internal write pointer is
blocked from W, so external changes in W will not affect the FIFO
when it is full.
RSRS) — Reset is accomplished whenever the Reset
RR) and Write Enable (
WW) inputs must
RSRS) and should not
RSRS.
WW) — A write cycle is initiated on the falling
RFF, allowing a new valid write
5V
1.1KΩ
D.U.T.
680Ω
*Includes jig and scope capacitances.
READ ENABLE (
OR EQUIVALENT CIRCUIT
Figure 1. Output Load
RR) — A read cycle is initiated on the falling
30pF*
3140 drw 04
edge of the Read Enable (R), provided the Empty Flag (EF) is not
set. The data is accessed on a First-In/First-Out basis, independent of any ongoing write operations. After Read Enable (R)
goes HIGH, the Data Outputs (Q0 through Q8) will return to a
high-impedance condition until the next Read operation. When
all the data has been read from the FIFO, the Empty Flag (EF)
will go LOW, allowing the “final” read cycle but inhibiting further
read operations, with the data outputs remaining in a highimpedance state. Once a valid write operation has been accomplished, the Empty Flag (EF) will go HIGH after t
WEF and a valid
Read can then begin. When the FIFO is empty, the internal read
pointer is blocked from R so external changes will not affect the
FIFO when it is empty.
FIRST LOAD/RETRANSMIT (
FLFL/
RTRT) — This is a dual-
purpose input. In the Depth Expansion Mode, this pin is
grounded to indicate that it is the first device loaded (see
Operating Modes). The Single Device Mode is initiated by
grounding the Expansion In (XI).
The IDT7207 can be made to retransmit data when the
Retransmit Enable Control (RT) input is pulsed LOW. A retransmit operation will set the internal read pointer to the first location
and will not affect the write pointer. The status of the Flags will
change depending on the relative locations of the read and write
pointers. Read Enable (R) and Write Enable (W) must be in the
HIGH state during retransmit. This feature is useful when less
than 32,768 writes are performed between resets. The retransmit feature is not compatible with the Depth Expansion Mode.
EXPANSION IN (
XIXI) — This input is a dual-purpose pin.
Expansion In (XI) is grounded to indicate an operation in the
single device mode. Expansion In (XI) is connected to Expansion Out (XO) of the previous device in the Depth Expansion or
Daisy-Chain Mode.
5.05 4
Page 5
IDT7207 CMOS ASYNCHRONOUS FIFO
32,768 x 9 MILITARY AND COMMERCIAL TEMPERATURE RANGES
Outputs:
FULL FLAG (
further write operations, when the device is full. If the read
pointer is not moved after Reset (RS), the Full Flag (FF) will go
LOW after 32,768 writes.
EMPTY FLAG (
inhibiting further read operations, when the read pointer is equal
to the write pointer, indicating that the device is empty.
EXPANSION OUT/HALF-FULL FLAG (
dual-purpose output. In the single device mode, when Expansion In (XI) is grounded, this output acts as an indication of a halffull memory.
After half of the memory is filled, and at the falling edge of the
next write operation, the Half-Full Flag (HF) will be set to LOW
RS
W
FFFF) — The Full Flag (FF) will go LOW, inhibiting
EFEF) — The Empty Flag (EF) will go LOW,
XOXO/
HFHF) — This is a
tRS
and will remain set until the difference between the write pointer
and read pointer is less than or equal to one half of the total
memory of the device. The Half-Full Flag (HF) is then reset by
the rising edge of the read operation.
In the Depth Expansion Mode, Expansion In (XI) is connected to Expansion Out (XO) of the previous device. This
output acts as a signal to the next device in the Daisy Chain by
providing a pulse to the next device when the previous device
reaches the last location of memory. There will be an XO pulse
when the Write pointer reaches the last location of memory, and
an additional XO pulse when the Read pointer reaches the last
location of memory.
DATA OUTPUTS (Q0-Q8) — Q0-Q8 are data outputs for 9-
bit wide data. These outputs are in a high-impedance condition
whenever Read (R) is in a HIGH state.
tRSC
t
RSS
t
RSR
R
EF
HF, FF
NOTE:
1. W and R = V
R
Q0–Q
8
IH around the rising edge of
t
t
RLZ
t
RSS
t
EFL
t
HFH
, t
FFH
3140 drw 05
RS
.
Figure 2. Reset
tRC
OUT
t RR
t
DV
VALID
t WR
A
DATA
t
WC
tWPW
tA
tRPW
OUT
t
RHZ
VALIDDATA
D
0 –D8
W
t
DS
DATA
Figure 3. Asynchronous Write and Read Operation
IN
t
DH
VALID
5.05 5
DATA IN
VALID
3140 drw 06
Page 6
IDT7207 CMOS ASYNCHRONOUS FIFO
32,768 x 9 MILITARY AND COMMERCIAL TEMPERATURE RANGES
LAST WRITE
IGNORED
WRITE
FIRST READ
R
W
t
WFF
t
RFF
FF
3140 drw 07
Figure 4. Full FlagTiming From Last Write to First Read
LAST READ
IGNORED
READ
FIRST WRITE
W
R
DATA
HF, EF, FF
EF
OUT
RT
W,R
t
REF
t
A
VALID
Figure 5. Empty Flag Timing From Last Read to First Write
t
RTC
t
RT
t
RTS
RTF
t
WEF
t
3171 drw 08
RTR
FLAG VALID
3140 drw 09
NOTE:
1. EF, FF and HF
may change status during Retransmit, but flags will be valid at tRTC.
Figure 6. Retransmit
5.05 6
Page 7
IDT7207 CMOS ASYNCHRONOUS FIFO
32,768 x 9 MILITARY AND COMMERCIAL TEMPERATURE RANGES
W
t
WEF
EF
t
RPE
R
3140 drw 10
Figure 7. Minimum Timing for an Empty Flag Coincident Read Pulse.
R
t
RFF
FF
t
WPF
W
HF
3140 drw 11
Figure 8. Minimum Timing for an Full Flag Coincident Write Pulse.
W
t
RHF
R
tWHF
HALF-FULL OR LESS MORE THAN HALF-FULL
Figure 9. Half-Full Flag Timing
HALF-FULL OR LESS
3140 drw 12
WRITE TO
LAST PHYSICAL
W
LOCATION
XO
READ FROM
R
t
XOL
t
XOH
Figure 10. Expansion Out
5.05 7
LAST PHYSICAL
LOCATION
t
XOL
t
XOH
3140 drw 13
Page 8
IDT7207 CMOS ASYNCHRONOUS FIFO
32,768 x 9 MILITARY AND COMMERCIAL TEMPERATURE RANGES
t
XI
XI
t
XIS
W
R
WRITE TO
FIRST PHYSICAL
LOCATION
t
Figure 11. Expansion In
OPERATING MODES:
Care must be taken to assure that the appropriate flag is
monitored by each system (i.e. FF is monitored on the device
where W is used; EF is monitored on the device where R is
used). For additional information, refer to Tech Note 8:
ating FIFOs on Full and Empty Boundary Conditions
Tech Note 6:
Designing with FIFOs.
Single Device Mode
A single IDT7207 may be used when the application
requirements are for 32,768 words or less. The IDT7207 is
in a Single Device Configuration when the Expansion In (XI)
control input is grounded (see Figure 12).
Depth Expansion
The IDT7207 can easily be adapted to applications when
the requirements are for greater than 32,768 words. Figure 14
demonstrates Depth Expansion using three IDT7207s. Any
depth can be attained by adding additional IDT7207s. The
IDT7207 operates in the Depth Expansion mode when the
following conditions are met:
1. The first device must be designated by grounding the First
Load (FL) control input.
2. All other devices must have FL in the HIGH state.
3. The Expansion Out (XO) pin of each device must be tied to
the Expansion In (XI) pin of the next device. See Figure 14.
4. External logic is needed to generate a composite Full Flag
(FF) and Empty Flag (EF). This requires the ORing of all
EF
s and ORing of all FFs (i.e. all must be set to generate the
correct composite FF or EF). See Figure 14.
5. The Retransmit (RT) function and Half-Full Flag (HF) are
not available in the Depth Expansion Mode.
Oper-
and
XIR
t XIS
READ FROM
FIRST PHYSICAL
LOCATION
corresponding input control signals of multiple devices. Status flags (EF, FF and HF) can be detected from any one device.
Figure 13 demonstrates an 18-bit word width by using two
IDT7207s. Any word width can be attained by adding additional IDT7207s (Figure 13).
Bidirectional Operation
Applications which require data buffering between two
systems (each system capable of Read and Write operations)
can be achieved by pairing IDT7207s as shown in Figure 16.
Both Depth Expansion and Width Expansion may be used in
this mode.
Data Flow-Through
Two types of flow-through modes are permitted, a read
flow-through and write flow-through mode. For the read flowthrough mode (Figure 17), the FIFO permits a reading of a
single word after writing one word of data into an empty FIFO.
The data is enabled on the bus in (tWEF + tA) ns after the rising
edge of W, called the first write edge, and it remains on the bus
until the R line is raised from LOW-to-HIGH, after which the
bus would go into a three-state mode after tRHZ ns. The EF line
would have a pulse showing temporary deassertion and then
would be asserted.
In the write flow-through mode (Figure 18), the FIFO
permits the writing of a single word of data immediately after
reading one word of data from a full FIFO. The R line causes
the FF to be deasserted but the W line being LOW causes it to
be asserted again in anticipation of a new data word. On the
rising edge of W, the new word is loaded in the FIFO. The
line must be toggled when FF is not asserted to write new data
in the FIFO and to increment the write pointer.
3140 drw 14
W
For additional information, refer to Tech Note 9:
Cascading
FIFOs or FIFO Modules.
USAGE MODES:
Width Expansion
Word width may be increased simply by connecting the
Compound Expansion
The two expansion techniques described above can be
applied together in a straightforward manner to achieve large
FIFO arrays (see Figure 15).
5.05 8
Page 9
IDT7207 CMOS ASYNCHRONOUS FIFO
32,768 x 9 MILITARY AND COMMERCIAL TEMPERATURE RANGES
DATA (D)
IN
WRITE (W)
FULL FLAG (FF)
(HALF–FULL FLAG)
WRITE (W)
9
DATA IN (D)
FULL FLAG (FF)
RESET (RS)
(HF)
IDT
7207
READ (R)
9
DATA OUT (Q)
EMPTY FLAG (EF)
RETRANSMIT (RT)
EXPANSION IN (XI)
Figure 12. Block Diagram of 32,768 x 9 FIFO Used in Single Device Mode
HFHF
9918
IDT
7207
IDT
7207
3140 drw 15
READ (R)
EMPTY FLAG (EF)
RESET (RS)
9
9
RETRANSMIT (RT)
XI XI
18
OUT
DATA
NOTE:
1. Flag detection is accomplished by monitoring the FF, EF and HF signals on either (any) device used in the width expansion configuration.
Do not connect any output signals together.
Figure 13. Block Diagram of 32,768 x 18 FIFO Memory Used in Width Expansion Mode
(Q)
3140 drw 16
5.05 9
Page 10
IDT7207 CMOS ASYNCHRONOUS FIFO
32,768 x 9 MILITARY AND COMMERCIAL TEMPERATURE RANGES
TRUTH TABLES
TABLE I – RESET AND RETRANSMIT
SINGLE DEVICE CONFIGURATION/WIDTH EXPANSION MODE
Inputs Internal Status Outputs
Mode
RS
RS
RT
RT
XIXIRead Pointer Write Pointer
EF
EF
FF
FF
HF
HF
Reset 0 X 0 Location Zero Location Zero 0 1 1
Retransmit 1 0 0 Location Zero Unchanged X X X
Read/Write 1 1 0 Increment
NOTE:
1. Pointer will Increment if flag is HIGH.
(1)
Increment
(1)
XXX
3140 tbl 09
TABLE II – RESET AND FIRST LOAD
DEPTH EXPANSION/COMPOUND EXPANSION MODE
Inputs Internal Status Outputs
Mode
Reset First Device 0 0 (1) Location Zero Location Zero 0 1
Reset all Other Devices 0 1 (1) Location Zero Location Zero 0 1
Read/Write 1 X (1) X X X X
NOTES:
1. XI is connected to XO of previous device. See Figure 14.
2. RS = Reset Input,
FL/RT
RS
RS
= First Load/Retransmit, EF = Empty Flag Output, FF = Full Flag Output, XI = Expansion Input, HF = Half-Full Flag Output
FL
FL
XI
XI
Read Pointer Write Pointer
EF
EF
FF
FF
3140 tbl 10
FULL
RS
XO
W
D
9
FF EF
99
IDT
7207
FL
R
Q
V
CC
XI
XO
FF EF
9
IDT
7207
EMPTY
FL
XI
XO
FF
9
IDT
7207
EF
FL
XI
3140 drw 17
Figure 14. Block Diagram of 98,304 x 9 FIFO Memory (Depth Expansion)
5.05 10
Page 11
IDT7207 CMOS ASYNCHRONOUS FIFO
32,768 x 9 MILITARY AND COMMERCIAL TEMPERATURE RANGES
Q0–Q
8
Q0–Q
8
IDT7207
DEPTH
EXPANSION
BLOCK
IDT7207
DEPTH
EXPANSION
BLOCK
R, W, RS
D0-D
8
D9-D
FF
N
W
A
A
IDT
7207
IDT
7201A
NOTES:
1. For depth expansion block see section on Depth Expansion and Figure 14.
2. For Flag detection see section on Width Expansion and Figure 13.
Figure 15. Compound FIFO Expansion
Q9–Q
Q9–Q
D9-D
D18-D
R
EF
HF
17
Q
(N-8)
-Q
N
•••
17
Q
(N-8)
-Q
N
IDT7207
DEPTH
EXPANSION
BLOCK
•••
17
D
(N-8)-DN
•••D0 –D N
N
B
B
B
D
(N-8)-DN
3140 drw 18
DATA
IDT
7207
Q
B 0-8
DB 0-8Q
W
FF
B
B
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D
A 0-8
SYSTEM A SYSTEM B
A 0-8
R
A
HF
A
EF
A
Figure 16. Bidirectional FIFO Operation
IN
W
t
RPE
R
DATA
OUT
EF
t
t
WLZ
Figure 17. Read Data Flow-Through Mode
WEF
5.05 11
t
t
A
REF
DATA VALID OUT
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Page 12
IDT7207 CMOS ASYNCHRONOUS FIFO
32,768 x 9 MILITARY AND COMMERCIAL TEMPERATURE RANGES
R
t
WPF
W
t
RFF
FF
t
DATA
DATA
OUT
WFF
IN
t
A
DATA
Figure 18. Write Data Flow-Through Mode
OUT VALID
DATA IN
t
VALID
DS
t
3140 drw 21
DH
ORDERING INFORMATION
IDT
XXXX
Device
Type
X
PowerXXSpeedXPackage
X
Process/
Temperature
Range
Blank
B
Commercial (0
Military (–55
°C to +125°C)
Compliant to MIL-STD-883, Class B
P
D
J
L
15
Plastic DIP
Ceramic DIP
Plastic Leaded Chip Carrier
Leadless Chip Carrier (Military only)
Commercial Only
20
25
30
35
Commercial Only
Military Only
Commercial Only
50
L Low Power
7207 32,768 x 9 FIFO
°C to +70°C)
Access Time (t
Speed in ns
A)
3140 drw 22
5.05 12
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