Datasheet IDT72021, IDT72031, IDT72041 Datasheet (Integrated Device Technology)

查询IDT72255LA供应商

Integrated Device Technology, Inc.

CMOS SUPERSYNC FIFO™
8,192 x 18
16,384 x 18

IDT72255LA
IDT72265LA

FEATURES:

• Choose among the following memory organizations:
IDT72255LA 8,192 x 18
IDT72265LA 16,384 x 18

• Pin-compatible with the IDT72275/72285 SuperSync FIFOs

• 10ns read/write cycle time (8ns access time)

• Fixed, low first word data latency time

• Auto power down minimizes standby power consumption

• Master Reset clears entire FIFO

• Partial Reset clears data, but retains programmable

settings

• Retransmit operation with fixed, low first word data

latency time

• Empty, Full and Half-Full flags signal FIFO status

• Programmable Almost-Empty and Almost-Full flags, each

flag can default to one of two preselected offsets

• Program partial flags by either serial or parallel means

• Select IDT Standard timing (using EF and FF flags) or First

Word Fall Through timing (using OR and IR flags)

•

Output enable puts data outputs into high impedance state

• Easily expandable in depth and width

FUNCTIONAL BLOCK DIAGRAM

WCLK

D0 -D

• Independent Read and Write clocks (permit reading and
writing simultaneously)

• Available in the 64-pin Thin Quad Flat Pack (TQFP) and the
64-pin Slim Thin Quad Flat Pack (STQFP)

• High-performance submicron CMOS technology

• Industrial temperature range (–40°C to +85°C) is available

DESCRIPTION:

The IDT72255LA/72265LA are exceptionally deep, high
speed, CMOS First-In-First-Out (FIFO) memories with clocked
read and write controls. These FIFOs offer numerous improve­ments over previous SuperSync FIFOs, including the following:

• The limitation of the frequency of one clock input with

respect to the other has been removed. The Frequency
Select pin (FS) has been removed, thus it is no longer
necessary to select which of the two clock inputs, RCLK or
WCLK, is running at the higher frequency.

• The period required by the retransmit operation is now fixed

and short.

17

INPUT REGISTER

WRITE CONTROL

LOGIC

RAM ARRAY

8,192 x 18

WRITE POINTER

RESET

LOGIC

SuperSyncFIFO is a trademark and the IDT logo is a registered trademark of Integrated Device Technology, Inc.

16,384 x 18

OUTPUT REGISTER

Q0 -Q

17

OFFSET REGISTER

FLAG

LOGIC

READ POINTER

READ

CONTROL

LOGIC

/
/

FWFT/SI

RCLK

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DESCRIPTION (Continued)

• The first word data latency period, from the time the first
word is written to an empty FIFO to the time it can be read,
is now fixed and short. (The variable clock cycle counting
delay associated with the latency period found on previous
SuperSync devices has been eliminated on this SuperSync
family.)

SuperSync FIFOs are particularly appropriate for network,
video, telecommunications, data communications and other
applications that need to buffer large amounts of data.

The input port is controlled by a Write Clock (WCLK) input
and a Write Enable (
on every rising edge of WCLK when

WEN

) input. Data is written into the FIFO

WEN

is asserted. The
output port is controlled by a Read Clock (RCLK) input and
Read Enable (
rising edge of RCLK when

REN

) input. Data is read from the FIFO on every

REN

is asserted. An Output Enable

(OE) input is provided for three-state control of the outputs.

PIN CONFIGURATIONS

WCLK

FWFT/SI

GND

The frequencies of both the RCLK and the WCLK signals
may vary from 0 to fMAX with complete independence. There
are no restrictions on the frequency of one clock input with
respect to the other.

There are two possible timing modes of operation with
these devices: IDT Standard mode and First Word Fall Through
(FWFT) mode.

In

IDT Standard mode,

the first word written to an empty
FIFO will not appear on the data output lines unless a specific
read operation is performed. A read operation, which consists
of activating

REN

and enabling a rising RCLK edge, will shift

the word from internal memory to the data output lines.

In

FWFT mode,

the first word written to an empty FIFO is
clocked directly to the data output lines after three transitions
of the RCLK signal. A

REN

does not have to be asserted for
accessing the first word. However, subsequent words written
to the FIFO do require a LOW on

/

VCC

/

RCLK

REN

for access. The state

PIN 1

DC

V

CC

GND

D17
D16
D15
D14
D13
D12
D11
D10

D9
D8
D7

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33

Q17
Q16
GND
Q15
Q14
V

CC

Q13
Q12
Q11
GND
Q10
Q9
Q8
Q7
Q6
GND

D6

D5

D4

D3

D2

D1

D0

GND

Q0

Q1

TQFP (PN64-1, order code: PF)
STQFP (PP64-1, order code: TF)

TOP VIEW

GND

Q2

Q3

CC

V

Q4

Q5

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DESCRIPTION (Continued)

of the FWFT/SI input during Master Reset determines the
timing mode in use.

For applications requiring more data storage capacity than
a single FIFO can provide, the FWFT timing mode permits
depth expansion by chaining FIFOs in series (i.e. the data
outputs of one FIFO are connected to the corresponding data
inputs of the next). No external logic is required.

These FIFOs have five flag pins, EF/OR (Empty Flag or
Output Ready), FF/IR (Full Flag or Input Ready), HF (Half-full
Flag),

PAE

(Programmable Almost-Empty flag) and
grammable Almost-Full flag). The EF and FF functions are
selected in IDT Standard mode. The IR and OR functions are
selected in FWFT mode. HF,
available for use, irrespective of timing mode.

PAE

and

PAF

can be programmed independently to switch
at any point in memory. (See Table I and Table II.) Program­mable offsets determine the flag switching threshold and can
be loaded by two methods: parallel or serial. Two default
offset settings are also provided, so that
switch at 127 or 1,023 locations from the empty boundary and
the

PAF

threshold can be set at 127 or 1,023 locations from the
full boundary. These choices are made with the LD pin during
Master Reset.

For serial programming,
rising edge of WCLK, are used to load the offset registers via
the Serial Input (SI). For parallel programming,
with LD on each rising edge of WCLK, are used to load the
offset registers via Dn.
edge of RCLK can be used to read the offsets in parallel from

REN

PAE

and

PAF

PAE

SEN

together with LD on each

together with LD on each rising

PAF

(Pro-

are always

can be set to

WEN

together

Qn regardless of whether serial or parallel offset loading has
been selected.

During Master Reset (
The read and write pointers are set to the first location of the
FIFO. The FWFT pin selects IDT Standard mode or FWFT
mode. The LD pin selects either a partial flag default setting
of 127 with parallel programming or a partial flag default
setting of 1,023 with serial programming. The flags are
updated according to the timing mode and default offsets
selected.

The Partial Reset (
pointers to the first location of the memory. However, the
timing mode, partial flag programming method, and default or
programmed offset settings existing before Partial Reset
remain unchanged. The flags are updated according to the
timing mode and offsets in effect.
a device in mid-operation, when reprogramming partial flags
would be undesirable.

The Retransmit function allows data to be reread from the
FIFO more than once. A LOW on the RT input during a rising
RCLK edge initiates a retransmit operation by setting the read
pointer to the first location of the memory array.

If, at any time, the FIFO is not actively performing an
operation, the chip will automatically power down. Once in the
power down state, the standby supply current consumption is
minimized. Initiating any operation (by activating control
inputs) will immediately take the device out of the power down
state.

The IDT72255LA/72265LA are fabricated using IDT’s high
speed submicron CMOS technology.

MRS

) the following events occur:

PRS

) also sets the read and write

PRS

is useful for resetting

PARTIAL RESET ( )

WRITE CLOCK (WCLK)

WRITE ENABLE (

LOAD (

DATA IN (D

0

- Dn)

SERIAL ENABLE( )

FIRST WORD FALL THROUGH/SERIAL INPUT

(FWFT/SI)

FULL FLAG/INPUT READY (

/ )

PROGRAMMABLE ALMOST-FULL (

Figure 1. Block Diagram of Single 8,192 x 18 and 16,384 x 18 Synchronous FIFO

)

)

)

MASTER RESET ( )

READ CLOCK (RCLK)
READ ENABLE (

OUTPUT ENABLE (

DATA OUT (Q0 - Qn)

IDT
72255LA
72265LA

RETRANSMIT ( )
EMPTY FLAG/OUTPUT READY (
PROGRAMMABLE ALMOST-EMPTY (

HALF FULL FLAG ( )

)

)

/ )

)

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COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE

PIN DESCRIPTION

Symbol Name I/O Description

D0–D17 Data Inputs I Data inputs for a 18-bit bus.

MRS

PRS

RT

FWFT/SI First Word Fall I During Master Reset, selects First Word Fall Through or IDT Standard mode.

WCLK Write Clock I When enabled by

WEN

RCLK Read Clock I When enabled by

REN
OE
SEN
LD

DC Don't Care I This pin must be tied to either VCC or GND and must not toggle after Master

FF/IR

EF/OR

PAF

PAE

HF

Q0–Q17 Data Outputs O Data outputs for an 18-bit bus.
VCC Power +5 Volt power supply pins.
GND Ground Ground pins.

Master Reset I

MRS

initializes the read and write pointers to zero and sets the output register to
all zeroes. During Master Reset, the FIFO is configured for either FWFT or IDT
Standard mode, one of two programmable flag default settings, and serial or
parallel programming of the offset settings.

Partial Reset I

PRS

initializes the read and write pointers to zero and sets the output register to
all zeroes. During Partial Reset, the existing mode (IDT or FWFT), programming
method (serial or parallel), and programmable flag settings are all retained.

Retransmit I

RT

asserted on the rising edge of RCLK initializes the READ pointer to zero, sets
the EF flag to LOW (OR to HIGH in FWFT mode) temporarily and does not disturb
the write pointer, programming method, existing timing mode or programmable flag
settings. RT is useful to reread data from the first physical location of the FIFO.

Through/Serial In After Master Reset, this pin functions as a serial input for loading offset registers

WEN

, the rising edge of WCLK writes data into the FIFO and
offsets into the programmable registers for parallel programming, and when
enabled by

SEN

, the rising edge of WCLK writes one bit of data into the

programmable register for serial programming.

Write Enable I

WEN

enables WCLK for writing data into the FIFO memory and offset registers.

REN

, the rising edge of RCLK reads data from the FIFO

memory and offsets from the programmable registers.

Read Enable I

REN

enables RCLK for reading data from the FIFO memory and offset registers.
Output Enable I OE controls the output impedance of Qn.
Serial Enable I

SEN

enables serial loading of programmable flag offsets.

Load I During Master Reset, LD selects one of two partial flag default offsets (127 or

1,023) and determines the flag offset programming method, serial or parallel. After
Master Reset, this pin enables writing to and reading from the offset registers.

Reset.

Full Flag/ O In the IDT Standard mode, the FF function is selected. FF indicates whether or
Input Ready not the FIFO memory is full. In the FWFT mode, the IR function is selected.

indicates whether or not there is space available for writing to the FIFO memory.

Empty Flag/ O In the IDT Standard mode, the EF function is selected. EF indicates whether or
Output Ready not the FIFO memory is empty. In FWFT mode, the OR function is selected.

OR

indicates whether or not there is valid data available at the outputs.

Programmable O

PAF

goes LOW if the number of words in the FIFO memory is more than

Almost-Full Flag total word capacity of the FIFO minus the full offset value m, which is stored in the

Full Offset register. There are two possible default values for m: 127 or 1,023.

Programmable O

PAE

goes LOW if the number of words in the FIFO memory is less than offset n,

Almost-Empty Flag which is stored in the Empty Offset register. There are two possible default values

for n: 127 or 1,023. Other values for n can be programmed into the device.

Half-Full Flag O

HF

indicates whether the FIFO memory is more or less than half-full.

IR

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IDT72255LA/72265LA SUPERSYNC FIFO™
8,192 x 18, 16,384 x 18

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE

ABSOLUTE MAXIMUM RATINGS

Symbol Rating Com’l & Ind’l Unit

V

TERM Terminal Voltage –0.5 to +7.0 V

with respect to GND

STG Storage –55 to +125 °C

T

Temperature

OUT DC Output Current –50 to +50 mA

I

NOTE:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT­INGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for ex­tended periods may affect reliability.

RECOMMENDED DC OPERATING CONDITIONS

Symbol Parameter Min. Typ. Max. Unit

V

CC Supply Voltage 4.5 5.0 5.5 V

Commercial/Industrial
GND Supply Voltage 0 0 0 V
VIH Input High Voltage 2.0 — — V

Commercial/Industrial

(1)

V

IL

Input Low Voltage — — 0.8 V

Commercial/Industrial

A Operating Temperature 0 — 70 °C

T

Commercial
T

A Operating Temperature –40 — 85 °C

Industrial

NOTE:

1. 1.5V undershoots are allowed for 10ns once per cycle.

DC ELECTRICAL CHARACTERISTICS

(Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C; Industrial: VCC = 5V ± 10%, TA = –40°C to +85°C )

IDT72255LA
IDT72265LA

Commercial & Industrial

tCLK = 10, 15, 20 ns

(1)

Symbol Parameter Min. Max. Unit

(2)

ILI
I

LO

(3)

Input Leakage Current –1 1 µA

Output Leakage Current –10 10 µA
VOH Output Logic “1” Voltage, IOH = –2 mA 2.4 — V
V

OL Output Logic “0” Voltage, IOL = 8 mA — 0.4 V

(4,5,6)

I

CC1

(4,7)

CC2

I

NOTES:

1. Industrial temperature range product for 15ns and 20ns speed grades are available as a standard device.

2. Measurements with 0.4 ≤ VIN ≤ VCC.

3.OE

≥ VIH, 0.4 ≤ VOUT ≤ VCC.

4. Tested with outputs disabled (IOUT = 0).

5. RCLK and WCLK toggle at 20 MHz and data inputs switch at 10 MHz.

6. Typical I
data switching at f

7. All Inputs = V

Active Power Supply Current — 80 mA
Standby Current — 20 mA

CC1 = 15 + 2.1*fS + 0.02*CL*fS (in mA) with VCC = 5V, tA = 25°C, fS = WCLK frequency = RCLK frequency (in MHz, using TTL levels),

S/2, CL = capacitive load (in pF).

CC - 0.2V or GND + 0.2V, except RCLK and WCLK, which toggle at 20 MHz.

CAPACITANCE (TA = +25°C, f = 1.0MHz)

Symbol Parameter

(2)

C

IN

Input VIN = 0V 10 pF
Capacitance

(1,2)

C

OUT

Output VOUT = 0V 10 pF
Capacitance

NOTES:

1. With output deselected, (OE ≥ V

2. Characterized values, not currently tested.

(1)

Conditions Max. Unit

IH).

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IDT72255LA/72265LA SUPERSYNC FIFO™
8,192 x 18, 16,384 x 18

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE

AC ELECTRICAL CHARACTERISTICS

(1)

(Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C; Industrial: VCC = 5V ± 10%, TA = –40°C to +85°C )

Commercial Com’l & Ind’l

IDT72255LA10 IDT72255LA15 IDT72255LA20
IDT72265LA10 IDT72265LA15 IDT72265LA20

Symbol Parameter Min. Max. Min. Max. Min. Max. Unit

S Clock Cycle Frequency — 100 — 66.7 — 50 MHz

f

A Data Access Time 2 8 2 10 2 12 ns

t

CLK Clock Cycle Time 10 — 15 — 20 — ns

t

CLKH Clock High Time 4.5 — 6 — 8 — ns

t

CLKL Clock Low Time 4.5 — 6 — 8 — ns

t

DS Data Setup Time 3 — 4 — 5 — ns

t

DH Data Hold Time 0 — 1 — 1 — ns

t

ENS Enable Setup Time 3 — 4 — 5 — ns

t

ENH Enable Hold Time 0 — 1 — 1 — ns

t

LDS Load Setup Time 3 — 4 — 5 — ns

t

LDH Load Hold Time 0 — 1 — 1 — ns

t

PAF

FF

EF

PAF

PAE

or

or

(3)

(4)

(4)

IR

OR

10 — 15 — 20 — ns

0—0—0—ns

26 3 8 310ns
— 8 — 10 — 12 ns
— 8 — 10 — 12 ns
— 8 — 10 — 12 ns
— 8 — 10 — 12 ns
—16 — 20 — 22ns

RS Reset Pulse Width

t

RSS Reset Setup Time 10 — 15 — 20 — ns

t

RSR Reset Recovery Time 10 — 15 — 20 — ns

t

RSF Reset to Flag and Output Time — 10 — 15 — 20 ns

t

FWFT Mode Select Time 0 — 0 — 0 — ns

t

RTS Retransmit Setup Time 3 — 4 — 5 — ns

t

OLZ Output Enable to Output in Low Z

t

OE Output Enable to Output Valid 2 6 3 8 3 10 ns

t

OHZ Output Enable to Output in High Z

t

WFF Write Clock to

t

REF Read Clock to

t

PAF Write Clock to

t

PAE Read Clock to

t

HF Clock to

t

SKEW1 Skew time between RCLK and WCLK 5 — 6 — 10 — ns

t

for FF/

SKEW2 Skew time between RCLK and WCLK 12 — 15 — 20 — ns

t

for

t

SKEW3 Skew time between RCLK and WCLK 60 — 60 — 60 — ns

for EF/

NOTES:

1. All AC timings apply to both Standard IDT mode and First Word Fall Through mode.

2.

Industrial temperature range product for 15ns and 20ns speed grade are available as a
standard device.

3. Pulse widths less than minimum values are not allowed.

4. Values guaranteed by design, not currently tested.

PAE

HF

IR

and

OR

(1)

5V

1.1K

AC TEST CONDITIONS

Input Pulse Levels GND to 3.0V
Input Rise/Fall Times 3ns
Input Timing Reference Levels 1.5V
Output Reference Levels 1.5V
Output Load See Figure 1

D.U.T.

680Ω

Figure 2. Output Load

* Includes jig and scope capacitances.

30pF*

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COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE

FUNCTIONAL DESCRIPTION

TIMING MODES: IDT STANDARD vs FIRST WORD FALL
THROUGH (FWFT) MODE

The IDT72255LA/72265LA support two different timing
modes of operation: IDT Standard mode or First Word Fall
Through (FWFT) mode. The selection of which mode will
operate is determined during Master Reset, by the state of the

FWFT/SI input.

If, at the time of Master Reset, FWFT/SI is LOW, then IDT
Standard mode will be selected. This mode uses the Empty
Flag (EF) to indicate whether or not there are any words
present in the FIFO. It also uses the Full Flag function (FF) to
indicate whether or not the FIFO has any free space for
writing. In IDT Standard mode, every word read from the
FIFO, including the first, must be requested using the Read
Enable (

FWFT mode will be selected. This mode uses Output Ready
(OR) to indicate whether or not there is valid data at the data
outputs (Qn). It also uses Input Ready (IR) to indicate whether
or not the FIFO has any free space for writing. In the FWFT
mode, the first word written to an empty FIFO goes directly to
Qn after three RCLK rising edges,
sary. Subsequent words must be accessed using the Read
Enable (

differently depending on which timing mode is in effect.

IDT STANDARD MODE

operate in the manner outlined in Table 1. To write data into to
the FIFO, Write Enable (
the DATA IN lines will be clocked into the FIFO on subsequent
transitions of the Write Clock (WCLK). After the first write is
performed, the Empty Flag (EF) will go HIGH. Subsequent
writes will continue to fill up the FIFO. The Programmable
Almost-Empty flag (
been loaded into the FIFO, where n is the empty offset value.
The default setting for this value is stated in the footnote of Table

1. This parameter is also user programmable. See section on
Programmable Flag Offset Loading.

assumed no read operations were taking place, the Half-Full
flag (HF) would toggle to LOW once the 4,097th word for
IDT72255LA and 8,193th word for IDT72265LA respectively
was written into the FIFO. Continuing to write data into the
FIFO will cause the Programmable Almost-Full flag (
go LOW. Again, if no reads are performed, the
LOW after (8,192-m) writes for the IDT72255LA and (16,384-m)
writes for the IDT72265LA. The offset “m” is the full offset
value. The default setting for this value is stated in the footnote
of Table 1. This parameter is also user programmable. See
section on Programmable Flag Offset Loading.

inhibiting further write operations. If no reads are performed

REN

) and RCLK.

If, at the time of Master Reset, FWFT/SI is HIGH, then

REN

= LOW is not neces-

REN

) and RCLK.

Various signals, both input and output signals operate

In this mode, the status flags, FF,

WEN

) must be LOW. Data presented to

PAE

) will go HIGH after n + 1 words have

PAF, HF, PAE

, and

EF

If one continued to write data into the FIFO, and we

PAF

) to

PAF

will go

When the FIFO is full, the Full Flag (FF) will go LOW,

after a reset, FF will go LOW after D writes to the FIFO.
D = 8,192 writes for the IDT72255LA and 16,384 for the
IDT72265LA, respectively.

If the FIFO is full, the first read operation will cause FF to go

HIGH. Subsequent read operations will cause

PAF

and HF to
go HIGH at the conditions described in Table 1. If further read
operations occur, without write operations,

PAE

will go LOW
when there are n words in the FIFO, where n is the empty
offset value. Continuing read operations will cause the FIFO
to become empty. When the last word has been read from the
FIFO, the EF will go LOW inhibiting further read operations.

REN

is ignored when the FIFO is empty.

When configured in IDT Standard mode, the EF and

FF

outputs are double register-buffered outputs.

Relevant timing diagrams for IDT Standard mode can be

found in Figure 7, 8 and 11.

FIRST WORD FALL THROUGH MODE (FWFT)

In this mode, the status flags, IR,

PAF, HF, PAE

, and

OR

operate in the manner outlined in Table 2. To write data into
to the FIFO,

WEN

must be LOW. Data presented to the DATA
IN lines will be clocked into the FIFO on subsequent transi­tions of WCLK. After the first write is performed, the Output
Ready (OR) flag will go LOW. Subsequent writes will continue
to fill up the FIFO.

PAE

will go HIGH after n + 2 words have
been loaded into the FIFO, where n is the empty offset value.
The default setting for this value is stated in the footnote of
Table 2. This parameter is also user programmable. See
section on Programmable Flag Offset Loading.

If one continued to write data into the FIFO, and we
assumed no read operations were taking place, the HF would
toggle to LOW once the 4,098th word for the IDT72255LA and
8,194th word for the IDT72265LA, respectively was written
into the FIFO. Continuing to write data into the FIFO will cause
the

PAF

to go LOW. Again, if no reads are performed, the

PAF

will go LOW after (8,193-m) writes for the IDT72255LA and
(16,385-m) writes for the IDT72265LA, where m is the full
offset value. The default setting for this value is stated in the
footnote of Table 2.

When the FIFO is full, the Input Ready (IR) flag will go HIGH,
inhibiting further write operations. If no reads are performed after
a reset, IR will go HIGH after D writes to the FIFO. D = 8,193
writes for the IDT72255LA and 16,385 writes for the IDT72265LA,
respectively. Note that the additional word in FWFT mode is due
to the capacity of the memory plus output register.

If the FIFO is full, the first read operation will cause the

IR

flag to go LOW. Subsequent read operations will cause the

PAF

and HF to go HIGH at the conditions described in Table

2. If further read operations occur, without write operations,
the

PAE

will go LOW when there are n + 1 words in the FIFO,
where n is the empty offset value. Continuing read operations
will cause the FIFO to become empty. When the last word has
been read from the FIFO, OR will go HIGH inhibiting further
read operations.

REN

is ignored when the FIFO is empty.

When configured in FWFT mode, the OR flag output is triple
register-buffered, and the IR flag output is double register­buffered.

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IDT72255LA/72265LA SUPERSYNC FIFO™
8,192 x 18, 16,384 x 18

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE

Relevant timing diagrams for FWFT mode can be found in

Figure 9, 10 and 12.

PROGRAMMING FLAG OFFSETS

Full and Empty Flag offset values are user programmable.
The IDT72255LA/72265LA has internal registers for these
offsets. Default settings are stated in the footnotes of Table 1
and Table 2. Offset values can be programmed into the FIFO
in one of two ways; serial or parallel loading method. The
selection of the loading method is done using the LD (Load)
pin. During Master Reset, the state of the LD input determines
whether serial or parallel flag offset programming is enabled.
A HIGH on LD during Master Reset selects serial loading of
offset values and in addition, sets a default

PAE

offset value
of 3FFH (a threshold 1,023 words from the empty boundary),
and a default

PAF

offset value of 3FFH (a threshold 1,023

words from the full boundary). A LOW on LD during Master
Reset selects parallel loading of offset values, and in addition,
sets a default
from the empty boundary), and a default

PAE

offset value of 07FH (a threshold 127 words

PAF

offset value of
07FH (a threshold 127 words from the full boundary). See
Figure 3,

Offset Register Location and Default Values

.

In addition to loading offset values into the FIFO, it also

possible to read the current offset values. It is only possible to
read offset values via parallel read.

Figure 4,

quence

Programmable Flag Offset Programming Se-

, summarizes the control pins and sequence for both
serial and parallel programming modes. For a more detailed
description, see discussion that follows.

The offset registers may be programmed (and repro­grammed) any time after Master Reset, regardless of whether
serial or parallel programming has been selected.

TABLE I –– STATUS FLAGS FOR IDT STANDARD MODE

72255LA 72265LA

0

(1)

Number of
Words in
FIFO

NOTES:

1. n = Empty Offset, Default Values: n = 127 when parallel offset loading is selected or n = 1,023 when serial offset loading is selected.

2. m = Full Offset, Default Values: m = 127 when parallel offset loading is selected or m = 1,023 when serial offset loading is selected.

4,097 to (8,192-(m+1))

(8,192-m)

1 to n

(n+1) to 4,096

(2)

to 8,191

8,192

8,193 to (16,384-(m+1))
(16,384-m)

0

(1)

1 to n

(n+1) to 8,192

(2)

to 16,383

16,384

HHHL L
HHHLH
HHHH H
HHLHH

HLLHH

LLLHH

TABLE II –– STATUS FLAGS FOR FWFT MODE

72255LA 72265LA

0

Number of
Words in

(

1)

FIFO

NOTES:

1. n = Empty Offset, Default Values: n = 127 when parallel offset loading is selected or n = 1,023 when serial offset loading is selected.

2. m = Full Offset, Default Values: m = 127 when parallel offset loading is selected or m = 1,023 when serial offset loading is selected.

4,098 to (8,193-(m+1))

(8,193-m)

1 to n+1

(n+2) to 4,097

8,193

(1)

to 8,192

(2)

8,194 to (16,385-(m+1))

(16,385-m)

0

1 to n+1

(n+2) to 8,193

to 16,384

16,385

LHHLH

(1)

(2)

LHHLL
LHHHL

LHLHL
LLLHL
HLL HL

4670 drw 05

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COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE

72255LA – 8,192 x 18–BIT

17 0

17 0

12

EMPTY OFFSET REGISTER

07FH if is LOW at Master Reset,

3FFH if

12

07FH if

3FFH if

DEFAULT VALUE

is HIGH at Master Reset

FULL OFFSET REGISTER

DEFAULT VALUE

is LOW at Master Reset,

is HIGH at Master Reset

Figure 3. Offset Register Location and Default Values

72265LA – 16,384 x 18–BIT

17 0

17 0

13

EMPTY OFFSET REGISTER

07FH if is LOW at Master Reset,

13

07FH if

DEFAULT VALUE

3FFH if

FULL OFFSET REGISTER

3FFH if

is HIGH at Master Reset

DEFAULT VALUE

is LOW at Master Reset,
is HIGH at Master Reset

4670 drw 06

WCLK

0

0

1

1

RCLK

X

Parallel write to registers:

Selection

Empty Offset
Full Offset

0

1

0

1

X

Parallel read from registers:

Empty Offset
Full Offset

0

1

1

0

X

Serial shift into registers:
26 bits for the 72255LA
28 bits for the 72265LA

1 bit for each rising WCLK edge
Starting with Empty Offset (LSB)

Ending with Full Offset (MSB)

X

1

1

1

1

0

X

1

1

X

0

1

1

X

X

X

X

X

X

X

X

X

No Operation

Write Memory

Read Memory

No Operation

NOTES:

1. The programming method can only be selected at Master Reset.

2. Parallel reading of the offset registers is always permitted regardless of which programming method has been selected.

3. The programming sequence applies to both IDT Standard and FWFT modes.

Figure 4. Programmable Flag Offset Programming Sequence

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SERIAL PROGRAMMING MODE

If Serial Programming mode has been selected, as de-

s

cribed above, then programming of
be achieved by using a combination of the LD,
and SI input pins. Programming
follows: when LD and

SEN

are set LOW, data on the SI input

PAE

PAE

and

and

PAF

PAF

values can

SEN

, WCLK

proceeds as

are written, one bit for each WCLK rising edge, starting with
the Empty Offset LSB and ending with the Full Offset MSB. A
total of 26 bits for the IDT72255LA and 28 bits for the
IDT72265LA. See Figure 13,

mable Flag Registers

, for the timing diagram for this mode.

Serial Loading of Program-

Using the serial method, individual registers cannot be

programmed selectively.

PAE

and

PAF

can show a valid
status only after the complete set of bits (for all offset regis­ters) has been entered. The registers can be reprogrammed
as long as the complete set of new offset bits is entered.
When LD is LOW and

SEN

is HIGH, no serial write to the

registers can occur.

Write operations to the FIFO are allowed before and during
the serial programming sequence. In this case, the program­ming of all offset bits does not have to occur at once. A select
number of bits can be written to the SI input and then, by
bringing LD and
memory via Dn by toggling
with LD and

SEN

HIGH, data can be written to FIFO

WEN

. When

SEN

restored to a LOW, the next offset bit in

WEN

is brought HIGH

sequence is written to the registers via SI. If an interruption
of serial programming is desired, it is sufficient either to set
LOW and deactivate

LD

. Once LD and

SEN

or to set

SEN

are both restored to a LOW level, serial

SEN

LOW and deactivate

LD

offset programming continues.

From the time serial programming has begun, neither
partial flag will be valid until the full set of bits required to fill all
the offset registers has been written. Measuring from the
rising WCLK edge that achieves the above criteria;
valid after two more rising WCLK edges plus tPAF,

PAF

PAE

will be

will be
valid after the next two rising RCLK edges plus tPAE plus
tSKEW2.

It is not possible to read the flag offset values in a serial

mode.

PARALLEL MODE

If Parallel Programming mode has been selected, as

de

scribed above, then programming of
be achieved by using a combination of the LD, WCLK ,
Dn input pins. Programming
when LD and

WEN

are set LOW, data on the inputs Dn are

PAE

and

PAE

and

PAF

values can

PAF

proceeds as follows:

WEN

and

written into the Empty Offset Register on the first LOW-to-HIGH
transition of WCLK. Upon the second LOW-to-HIGH transition of
WCLK, data are written into the Full Offset Register. The third
transition of WCLK writes, once again, to the Empty Offset
Register. See Figure 14,

Flag Registers

, for the timing diagram for this mode.

Parallel Loading of Programmable

The act of writing offsets in parallel employs a dedicated
write offset register pointer. The act of reading offsets em­ploys a dedicated read offset register pointer. The two point­ers operate independently; however, a read and a write
should not be performed simultaneously to the offset regis­ters. A Master Reset initializes both pointers to the Empty

Offset (LSB) register. A Partial Reset has no effect on the
position of these pointers.

Write operations to the FIFO are allowed before and during
the parallel programming sequence. In this case, the pro­gramming of all offset registers does not have to occur at one
time. One, two or more offset registers can be written and then
by bringing LD HIGH, write operations can be redirected to the
FIFO memory. When LD is set LOW again, and

WEN

is LOW,
the next offset register in sequence is written to. As an
alternative to holding

WEN

LOW and toggling LD, parallel
programming can also be interrupted by setting LD LOW and
toggling

WEN

.

Note that the status of a partial flag (

PAE

or

PAF

) output is
invalid during the programming process. From the time
parallel programming has begun, a partial flag output will not
be valid until the appropriate offset word has been written to
the register(s) pertaining to that flag. Measuring from the rising
WCLK edge that achieves the above criteria;
after two more rising WCLK edges plus tPAF,

PAF

will be valid

PAE

will be valid

after the next two rising RCLK edges plus tPAE plus tSKEW2.

The act of reading the offset registers employs a dedicated
read offset register pointer. The contents of the offset regis­ters can be read on the Q0-Qn pins when LD is set LOW and

REN

is set LOW. Data are read via Qn from the Empty Offset
Register on the first LOW-to-HIGH transition of RCLK. Upon
the second LOW-to-HIGH transition of RCLK, data are read
from the Full Offset Register. The third transition of RCLK
reads, once again, from the Empty Offset Register. See
Figure 15,

Parallel Read of Programmable Flag Registers

, for

the timing diagram for this mode.

It is permissible to interrupt the offset register read se­quence with reads or writes to the FIFO. The interruption is
accomplished by deasserting
When

REN

and LD are restored to a LOW level, reading of the

REN, LD

, or both together.

offset registers continues where it left off. It should be noted,
and care should be taken from the fact that when a parallel
read of the flag offsets is performed, the data word that was
present on the output lines Qn will be overwritten.

Parallel reading of the offset registers is always permitted
regardless of which timing mode (IDT Standard or FWFT
modes) has been selected.

RETRANSMIT OPERATION

The Retransmit operation allows data that has already
been read to be accessed again. There are two stages: first,
a setup procedure that resets the read pointer to the first
location of memory, then the actual retransmit, which consists
of reading out the memory contents, starting at the beginning
of memory.

Retransmit setup is initiated by holding RT LOW during a
rising RCLK edge.

REN

and

WEN

must be HIGH before
bringing RT LOW. At least one word, but no more than D - 2
words should have been written into the FIFO between Reset
(Master or Partial) and the time of Retransmit setup. D = 8,192
for the IDT72255LA and D = 16,384 for the IDT72265LA. In
FWFT mode, D = 8,193 for the IDT72255LA and D= 16,385 for
the IDT72265LA.

If IDT Standard mode is selected, the FIFO will mark the

beginning of the Retransmit setup by setting EF LOW. The

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change in level will only be noticeable if EF was HIGH before
setup. During this period, the internal read pointer is initialized
to the first location of the RAM array.

When EF goes HIGH, Retransmit setup is complete and
read operations may begin starting with the first location in
memory. Since IDT Standard mode is selected, every word
read including the first word following Retransmit setup re­quires a LOW on
Figure 11,

REN

to enable the rising edge of RCLK. See

Retransmit Timing (IDT Standard Mode)

, for the

relevant timing diagram.

If FWFT mode is selected, the FIFO will mark the beginning
of the Retransmit setup by setting OR HIGH. During this
period, the internal read pointer is set to the first location of the
RAM array.

When OR goes LOW, Retransmit setup is complete; at the
same time, the contents of the first location appear on the

outputs. Since FWFT mode is selected, the first word
appears on the outputs, no LOW on
Reading all subsequent words requires a LOW on
enable the rising edge of RCLK. See Figure 12,

Timing (FWFT Mode)

, for the relevant timing diagram.

REN

is necessary.

Retransmit

REN

to

For either IDT Standard mode or FWFT mode, updating

of the

PAE, HF

RCLK that RT is setup.
on the second rising edge of RCLK after RT is setup, the

and

PAF

flags begin with the rising edge of

PAE

is synchronized to RCLK, thus

PAE

flag will be updated. HF is asynchronous, thus the rising
edge of RCLK that RT is setup will update HF.

PAF

is
synchronized to WCLK, thus the second rising edge of
WCLK that occurs tSKEW after the rising edge of RCLK that

RT

is setup will update

PAF. RT

is synchronized to RCLK.

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SIGNAL DESCRIPTION
INPUTS:

DATA IN (D0 - D17)

Data inputs for 18-bit wide data.

RETRANSMIT (
read to be accessed again. There are two stages: first, a setup

procedure that resets the read pointer to the first location of
memory, then the actual retransmit, which consists of reading out
the memory contents, starting at the beginning of the memory.

CONTROLS:

MASTER RESET (

A Master Reset is accomplished whenever the

MRSMRS

MRS

MRSMRS

)

MRS

input
is taken to a LOW state. This operation sets the internal read
and write pointers to the first location of the RAM array.
will go LOW,

PAF

will go HIGH, and HF will go HIGH.

PAE

If FWFT is LOW during Master Reset then the IDT
Standard mode, along with EF and FF are selected. EF will go
LOW and FF will go HIGH. If FWFT is HIGH, then the First
Word Fall Through mode (FWFT), along with IR and OR, are
selected. OR will go HIGH and IR will go LOW.

If LD is LOW during Master Reset, then
threshold 127 words from the empty boundary and

PAE

is assigned a

PAF

assigned a threshold 127 words from the full boundary; 127
words corresponds to an offset value of 07FH. Following
Master Reset, parallel loading of the offsets is permitted, but
not serial loading.

If LD is HIGH during Master Reset, then
a threshold 1,023 words from the empty boundary and

PAE

is assigned

PAF

assigned a threshold 1,023 words from the full boundary;
1,023 words corresponds to an offset value of 3FFH. Follow­ing Master Reset, serial loading of the offsets is permitted, but
not parallel loading.

Parallel reading of the registers is always permitted. (See
section describing the LD pin for further details.)

During a Master Reset, the output register is initialized to
all zeroes. A Master Reset is required after power up, before
a write operation can take place.

See Figure 5,

Master Reset Timing

MRS

is asynchronous.

, for the relevant timing

diagram.
PARTIAL RESET (

A Partial Reset is accomplished whenever the

PRSPRS

PRS

PRSPRS

)

PRS

input is
taken to a LOW state. As in the case of the Master Reset, the
internal read and write pointers are set to the first location of the
RAM array,

PAE

goes LOW,

PAF

goes HIGH, and HF goes HIGH.

Whichever mode is active at the time of Partial Reset, IDT
Standard mode or First Word Fall Through, that mode will
remain selected. If the IDT Standard mode is active, then FF will
go HIGH and EF will go LOW. If the First Word Fall Through
mode is active, then OR will go HIGH, and IR will go LOW.

Following Partial Reset, all values held in the offset regis­ters remain unchanged. The programming method (parallel
or serial) currently active at the time of Partial Reset is also
retained. The output register is initialized to all zeroes.

PRS

is asynchronous.

A Partial Reset is useful for resetting the device during the
course of operation, when reprogramming partial flag offset
settings may not be convenient.

See Figure 6,

Partial Reset Timing

, for the relevant timing

diagram.

rising RCLK edge.
bringing RT LOW.

beginning of the Retransmit setup by setting EF LOW. The
change in level will only be noticeable if EF was HIGH before
setup. During this period, the internal read pointer is initialized
to the first location of the RAM array.

read operations may begin starting with the first location in
memory. Since IDT Standard mode is selected, every word
read including the first word following Retransmit setup re­quires a LOW on

is

Figure 11,
relevant timing diagram.

the Retransmit setup by setting OR HIGH. During this period, the
internal read pointer is set to the first location of the RAM array.

same time, the contents of the first location appear on the

is

outputs. Since FWFT mode is selected, the first word appears
on the outputs, no LOW on
subsequent words requires a LOW on
edge of RCLK. See Figure 12,

Mode)

FIRST WORD FALL THROUGH/SERIAL IN (FWFT/SI)
FWFT/SI input determines whether the device will operate in IDT

Standard mode or First Word Fall Through (FWFT) mode.
Standard mode will be selected. This mode uses the Empty

Flag (EF) to indicate whether or not there are any words
present in the FIFO memory. It also uses the Full Flag function
(FF) to indicate whether or not the FIFO memory has any free
space for writing. In IDT Standard mode, every word read
from the FIFO, including the first, must be requested using the
Read Enable (

FWFT mode will be selected. This mode uses Output Ready
(OR) to indicate whether or not there is valid data at the data
outputs (Qn). It also uses Input Ready (IR) to indicate whether
or not the FIFO memory has any free space for writing. In the
FWFT mode, the first word written to an empty FIFO goes
directly to Qn after three RCLK rising edges,
necessary. Subsequent words must be accessed using the
Read Enable (

loading
The serial input function can only be used when the serial
loading method has been selected during Master Reset.
Serial programming using the FWFT/SI pin functions the
same way in both IDT Standard and FWFT modes.

RTRT

RT

)

RTRT

The Retransmit operation allows data that has already been

Retransmit setup is initiated by holding RT LOW during a

REN

and

WEN

must be HIGH before

If IDT Standard mode is selected, the FIFO will mark the

When EF goes HIGH, Retransmit setup is complete and

REN

to enable the rising edge of RCLK. See

Retransmit Timing (IDT Standard Mode)

, for the

If FWFT mode is selected, the FIFO will mark the beginning of

When OR goes LOW, Retransmit setup is complete; at the

REN

is necessary. Reading all

REN

to enable the rising

Retransmit Timing (FWFT

, for the relevant timing diagram.

This is a dual purpose pin. During Master Reset, the state of the

If, at the time of Master Reset, FWFT/SI is LOW, then IDT

REN

) and RCLK.

If, at the time of Master Reset, FWFT/SI is HIGH, then

REN

= LOW is not

REN

) and RCLK.

After Master Reset, FWFT/SI acts as a serial input for

PAE

and

PAF

offsets into the programmable registers.

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COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE

WRITE CLOCK (WCLK)

A write cycle is initiated on the rising edge of the WCLK
input. Data setup and hold times must be met with respect to
the LOW-to-HIGH transition of the WCLK. It is permissible to
stop the WCLK. Note that while WCLK is idle, the FF/IR,

PAF

and HF flags will not be updated. (Note that WCLK is only
capable of updating HF flag to LOW.) The Write and Read
Clocks can either be independent or coincident.

WRITE ENABLE (

When the

WENWEN

WEN

)

WENWEN

WEN

input is LOW, data may be loaded into the
FIFO RAM array on the rising edge of every WCLK cycle if the
device is not full. Data is stored in the RAM array sequentially
and independently of any ongoing read operation.

When

WEN

is HIGH, no new data is written in the RAM

array on each WCLK cycle.

To prevent data overflow in the IDT Standard mode, FF will
go LOW, inhibiting further write operations. Upon the comple­tion of a valid read cycle, FF will go HIGH allowing a write to
occur. The FF is updated by two WCLK cycles + tSKEW after
the RCLK cycle.

To prevent data overflow in the FWFT mode, IR will go
HIGH, inhibiting further write operations. Upon the completion
of a valid read cycle, IR will go LOW allowing a write to occur.
The IR flag is updated by two WCLK cycles + tSKEW after the
valid RCLK cycle.

WEN

is ignored when the FIFO is full in either FWFT or IDT

Standard mode.

READ CLOCK (RCLK)

A read cycle is initiated on the rising edge of the RCLK
input. Data can be read on the outputs, on the rising edge of
the RCLK input. It is permissible to stop the RCLK. Note that
while RCLK is idle, the EF/OR,
updated. (Note that RCLK is only capable of updating the

PAE

and HF flags will not be

HF

flag to HIGH.) The Write and Read Clocks can be indepen­dent or coincident.

READ ENABLE (

RENREN

REN

RENREN

)

When Read Enable is LOW, data is loaded from the RAM
array into the output register on the rising edge of every RCLK
cycle if the device is not empty.

When the

REN

input is HIGH, the output register holds the
previous data and no new data is loaded into the output register.
The data outputs Q0-Qn maintain the previous data value.

In the IDT Standard mode, every word accessed at Qn,
including the first word written to an empty FIFO, must be
requested using

REN

. When the last word has been read from
the FIFO, the Empty Flag (EF) will go LOW, inhibiting further
read operations.

REN

is ignored when the FIFO is empty.
Once a write is performed, EF will go HIGH allowing a read to
occur. The EF flag is updated by two RCLK cycles + tSKEW
after the valid WCLK cycle.

In the FWFT mode, the first word written to an empty FIFO
automatically goes to the outputs Qn, on the third valid LOW
to HIGH transition of RCLK + tSKEW after the first write.

REN

does not need to be asserted LOW. In order to access all other
words, a read must be executed using

REN

. The RCLK LOW

to HIGH transition after the last word has been read from the
FIFO, Output Ready (OR) will go HIGH with a true read (RCLK
with

REN

= LOW), inhibiting further read operations.

REN

is

ignored when the FIFO is empty.

SERIAL ENABLE (

The

SEN

input is an enable used only for serial program-

SENSEN

SEN

SENSEN

)

ming of the offset registers. The serial programming method
must be selected during Master Reset.

SEN

is always used
in conjunction with LD. When these lines are both LOW, data
at the SI input can be loaded into the program register one bit
for each LOW-to-HIGH transition of WCLK. (See Figure 4.)

When

SEN

is HIGH, the programmable registers retains

the previous settings and no offsets are loaded.

SEN

functions

the same way in both IDT Standard and FWFT modes.

OUTPUT ENABLE (

OEOE

OE

OEOE

)

When Output Enable is enabled (LOW), the parallel output
buffers receive data from the output register. When OE is HIGH,
the output data bus (Qn) goes into a high impedance state.

LOAD (

LDLD

LD

LDLD

)

This is a dual purpose pin. During Master Reset, the state of
the LD input determines one of two default offset values (127 or
1,023) for the

PAE

and

PAF

flags, along with the method by which
these offset registers can be programmed, parallel or serial.
After Master Reset, LD enables write operations to and read
operations from the offset registers. Only the offset loading
method currently selected can be used to write to the registers.
Offset registers can be read only in parallel. A LOW on LD during
Master Reset selects a default
threshold 127 words from the empty boundary), a default

PAE

offset value of 07FH (a

PAF

offset value of 07FH (a threshold 127 words from the full
boundary), and parallel loading of other offset values. A HIGH
on LD during Master Reset selects a default

PAE

offset value of
3FFH (a threshold 1,023 words from the empty boundary), a
default

PAF

offset value of 3FFH (a threshold 1,023 words from

the full boundary), and serial loading of other offset values.

After Master Reset, the LD pin is used to activate the

programming process of the flag offset values

PAE

and

PAF

.
Pulling LD LOW will begin a serial loading or parallel load or
read of these offset values. See Figure 4,

Offset Programming Sequence

.

Programmable Flag

OUTPUTS:

FFFF

FULL FLAG (

This is a dual purpose pin. In IDT Standard mode, the Full
Flag (FF) function is selected. When the FIFO is full, FF will go
LOW, inhibiting further write operations. When FF is HIGH, the
FIFO is not full. If no reads are performed after a reset (either

MRS

or

PRS

(D = 8,192 for the IDT72255LA and 16,384 for the IDT72265LA
See Figure 7,

Mode)

, for the relevant timing information.

In FWFT mode, the Input Ready (IR) function is selected.

IR

goes LOW when memory space is available for writing in

data. When there is no longer any free space left, IR goes

IRIR

FF

/

IR

)

FFFF

IRIR

), FF will go LOW after D writes to the FIFO

).

Write Cycle and Full Flag Timing (IDT Standard

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COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE

HIGH, inhibiting further write operations. If no reads are
performed after a reset (either

MRS

or

PRS

), IR will go HIGH
after D writes to the FIFO (D = 8,193 for the IDT72255LA and
16,385 for the IDT72265LA) See Figure 9,

(FWFT Mode)

, for the relevant timing information.

Write Timing

The IR status not only measures the contents of the FIFO
memory, but also counts the presence of a word in the output
register. Thus, in FWFT mode, the total number of writes
necessary to deassert IR is one greater than needed to assert

FF

in IDT Standard mode.

FF/IR

is synchronous and updated on the rising edge of WCLK.

FF/IR

are double register-buffered outputs.

EFEF

EMPTY FLAG (

EF

EFEF

OROR

/

OR

OROR

)

This is a dual purpose pin. In the IDT Standard mode, the
Empty Flag (EF) function is selected. When the FIFO is empty,

EF

will go LOW, inhibiting further read operations. When

is HIGH, the FIFO is not empty. See Figure 8,

Read Cycle,

EF

Empty Flag and First Word Latency Timing (IDT Standard
Mode)

, for the relevant timing information.

In FWFT mode, the Output Ready (OR) function is selected.

OR

goes LOW at the same time that the first word written to an
empty FIFO appears valid on the outputs. OR stays LOW after
the RCLK LOW to HIGH transition that shifts the last word from
the FIFO memory to the outputs. OR goes HIGH only with a true
read (RCLK with

REN

= LOW). The previous data stays at the
outputs, indicating the last word was read. Further data reads
are inhibited until OR goes LOW again.

Timing (FWFT Mode)

, for the relevant timing information.

See Figure 10,

Read

EF/OR is synchronous and updated on the rising edge of

RCLK.

In IDT Standard mode, EF is a double register-buffered

output. In FWFT mode, OR is a triple register-buffered output.

PROGRAMMABLE ALMOST-FULL FLAG (

The Programmable Almost-Full flag (

th

e FIFO reaches the almost-full condition. In IDT Standard

PAF

mode, if no reads are performed after reset (
LOW after (D - m) words are written to the FIFO. The

PAFPAF

PAF

)

PAFPAF

) will go LOW when

MRS

),

PAF

will go

PAF

will
go LOW after (8,192-m) writes for the IDT72255LA and
(16,384-m) writes for the IDT72265LA. The offset “m” is the full
offset value. The default setting for this value is stated in the
footnote of Table 1.

In FWFT mode, the

PAF

will go LOW after (8,193-m) writes

for the IDT72255LA and (16,385-m) writes for the IDT72265LA,

where m is the full offset value. The default setting for this
value is stated in the footnote of Table 2.

See Figure 16,

(IDT Standard and FWFT Mode)

Programmable Almost-Full Flag Timing

, for the relevant timing

information.

PAF

is synchronous and updated on the rising edge of WCLK.

PROGRAMMABLE ALMOST-EMPTY FLAG (

The Programmable Almost-Empty flag (

PAEPAE

PAE

PAEPAE

PAE

) will go LOW

)

when the FIFO reaches the almost-empty condition. In IDT
Standard mode, PAE will go LOW when there are n words or
less in the FIFO.

The offset “n” is the empty offset value. The

default setting for this value is stated in the footnote of Table 1.

In FWFT mode, the

words or less in the FIFO.

PAE

will go LOW when there are n+1

The default setting for this value is

stated in the footnote of Table 2.

See Figure 17,

(IDT Standard and FWFT Mode)

Programmable Almost-Empty Flag Timing

, for the relevant timing

information.

PAE

is synchronous and updated on the rising edge of RCLK.

HALF-FULL FLAG (

HFHF

HF

HFHF

)

This output indicates a half-full FIFO. The rising WCLK
edge that fills the FIFO beyond half-full sets HF LOW. The flag
remains LOW until the difference between the write and read
pointers becomes less than or equal to half of the total depth
of the device; the rising RCLK edge that accomplishes this
condition sets HF HIGH.

In IDT Standard mode, if no reads are performed after reset
(

MRS

or

PRS

), HF will go LOW after (D/2 + 1) writes to the

FIFO, where D = 8,192 for the

IDT72255LA and

16,384 for the

IDT72265LA.

In FWFT mode, if no reads are performed after reset (
or

PRS

), HF will go LOW after (D-1/2 + 2) writes to the FIFO,

where D = 8,193 for the

IDT72255LA and

16,385 for the

MRS

IDT72265LA.

See Figure 18,

FWFT Modes)

HF

is updated by both RCLK and WCLK, it is considered

Half-Full Flag Timing (IDT Standard and

, for the relevant timing information. Because

asynchronous.

DATA OUTPUTS (Q0-Q17)

(Q0 - Q17) are data outputs for 18-bit wide data.

14

IDT72255LA/72265LA SUPERSYNC FIFO™
8,192 x 18, 16,384 x 18

t

FWFT

FWFT/SI

t

RS

t

t

t

RSS

t

RSS

t

RSS

RSS

RSS

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE

t

RSR

t

RSR

t

RSR

t

RSR

/

/

,

Q0 - Q

t

RSF

If FWFT = HIGH, = HIGH
If FWFT = LOW, = LOW

t

RSF

If FWFT = LOW, = HIGH
If FWFT = HIGH, = LOW

t

RSF

t

RSF

t

RSF

n

Figure 5. Master Reset Timing

= HIGH

= LOW

4670 drw 08

15

IDT72255LA/72265LA SUPERSYNC FIFO™
8,192 x 18, 16,384 x 18

t

RS

t

RSS

t

t

RSS

t

RSS

RSS

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE

t

RSR

t

RSR

/

/

,

Q0 - Q

t

RSF

t

RSF

t

RSF

t

RSF

t

RSF

n

Figure 6. Partial Reset Timing

If FWFT = HIGH, = HIGH

If FWFT = LOW, = LOW

If FWFT = LOW, = HIGH

If FWFT = HIGH, = LOW

= HIGH

= LOW

4670 drw 09

16

IDT72255LA/72265LA SUPERSYNC FIFO™
8,192 x 18, 16,384 x 18

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE

tCLK

tCLKL

tDH

D

X

tSKEW1

tWFF

WCLK

D0 - D

tCLKH

tDS

tSKEW1

NO WRITE

(1)

1

2

n

tWFF

RCLK

tENS

DATA READ NEXT DATA READDATA IN OUTPUT REGISTER

Q0 - Q

tENS

tENH

tA

n

NOTES:

1. t

SKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that

If the time between the rising edge of the RCLK and the rising edge of the WCLK is less than t
extra WCLK cycle.

2.LD = HIGH, OE = LOW, EF = HIGH

Figure 7. Write Cycle and Full Flag Timing (IDT Standard Mode)

(1)

1

tENH

tA

FF

will go high (after one WCLK cycle pus tWFF).

SKEW1, then the

NO WRITE

2

tDS

tWFF

FF

deassertion may be delayed one

tDH

DX+1

tWFF

4670 drw 10

t

t

REF

CLK

t

OLZ

RCLK

Q0 - Q

t

1

t

ENS

n

t

t

OLZ

ENH

t

REF

t

NO OPERATION

A

NO OPERATION

LAST WORD

t

t

OE

(1)

t

SKEW3

OHZ

CLKH

2

WCLK

t

D0 - D

t

ENS

t

n

ENH

t

DHS

DS

D

0

t

ENS

t

DS

t

ENH

t

DH

D

1

NOTES:

1. t

SKEW3 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that

If the time between the rising edge of WCLK and the rising edge of RCLK is less than t

SKEW3, then

2.LD = HIGH

3. First word latency: 60ns + t

REF + 1*TRCLK.

Figure 8. Read Cycle, Empty Flag and First Data Word Latency Timing (IDT Standard Mode)

t

CLKL

t

t

t

t

ENS

ENH

t

A

LAST WORD

EF

will go HIGH (after one RCLK cycle plus tREF).

EF

deassertion may be delayed one extra RCLK cycle.

ENS

D

ENH

t

REF

t

A

0

D

4670 drw 11

1

17

IDT72255LA/72265LA SUPERSYNC FIFO™
8,192 x 18, 16,384 x 18

ENH

t

D

W

[D-1]

W

[D-m+2]

W

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE

4670 drw 12

WFF

t

PAF

[D-m+1]

1

W

[D-m]

W

[D-m-1]

W

DS

t

[D-m-2]

W

t

. If the time between the rising edge of WCLK

. If the time between the rising edge of WCLK

PAE

REF

][

D-1

W

][

D-1

W

DS

t

][

D-1

HF

t

W

[n+4]

2

W

(2)

PAE

[n+3]

SKEW2

1

W

t

1

[n +2]

W

DS

t

4

W

3

W

A

REF

t

t

t

will go HIGH after one RCLK cycle plus t

will go LOW after two RCLK cycles plus t

OR

PAE

deassertion may be delayed one extra RCLK cycle.

PAE

assertion may be delayed one extra RCLK cycle.

Figure 9. Write Timing (First Word Fall Through Mode)

OR

SKEW3, then

SKEW2, then the

WCLK

ENS

t

3

W

2

(1)

2

W

1

SKEW3

t

DH

t

1

W

DS

t

17

- D

RCLK

0

D

DATA IN OUTPUT REGISTER

17

- Q

0

Q

SKEW3 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that

SKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that

and the rising edge of RCLK is less than t

and the rising edge of RCLK is less than t

NOTES:

1. t

2. t

+ 2*TRCLK.

REF

offset and D = maximum FIFO depth.

PAF

= LOW

OE

offset, m =

PAE

= HIGH,

LD

3.

4. n =

5. D = 8,193 for IDT72255LA and 16,385 for IDT72265LA.

6. First word latency: 60ns + t

18

IDT72255LA/72265LA SUPERSYNC FIFO™
8,192 x 18, 16,384 x 18

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE

tREF

WD

tENS

1

tA

W[D-1]

W[D-n+1]W[m+4] W[D-n+2]

W[D-n]W[D-n-1]

tPAE

][

D-1

W

tA tA

][

D-1

W

tHF

4670 drw 13

PAF. If the time between the rising edge of RCLK

WFF. If the time between the rising edge of RCLK

will go HIGH after one WCLK cycle plus t

will go LOW after one WCLK cycle plus t

IR

PAF

(2)

tSKEW2

(1)

tSKEW1

12

tENH

tDH

WD

tDS

tENS

WCLK

D0 - D17

RCLK

tENS

tA

tA

tOE tA

tOHZ

W1 W1 W2 W3 Wm+2 W[m+3]

Q0 - Q17

tPAF

tWFF

tWFF

deassertion may be delayed one extra WCLK cycle.

assertion may be delayed one extra WCLK cycle.

IR

PAF

, then the

, then the

SKEW1

SKEW2

Figure 10. Read Timing (First Word Fall Through Mode)

offset and D = maximum FIFO depth.

PAF

Offset, m =

PAE

= HIGH

SKEW2 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that

SKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that

and the rising edge of WCLK is less than t

and the rising edge of WCLK is less than t

LD

2. t

NOTES:

1. t

3.

4. n =

5. D = 8,193 for IDT72255LA and 16,385 for IDT72265LA.

19

IDT72255LA/72265LA SUPERSYNC FIFO™
8,192 x 18, 16,384 x 18

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE

RCLK

Q0 - Q

WCLK

1

t

ENS

n

W

x

t

ENH

t

RTS

t

A

W

x+1

t

SKEW2

t

ENS

2

t

ENH

t

A

(3)

W

1

t

A

(3)

W

2

12

t

RTS

t

t

ENS

ENH

t

REF

t

REF

t

PAE

(5)

t

HF

t

PAF

4670 drw 14

NOTES:

1. Retransmit setup is complete after EF returns HIGH, only then can a read operation begin.

2.

OE

= LOW.

3. W

1 = first word written to the FIFO after Master Reset, W2 = second word written to the FIFO after Master Reset.

4. No more than D - 2 may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, FF will be HIGH throughout the
Retransmit setup procedure. D = 8,192 for IDT72255LA and 16,384 for IDT72265LA.

5.EF goes HIGH at 60 ns + 1 RCLK cycle + t

REF.

Figure 11. Retransmit Timing (IDT Standard Mode)

20

IDT72255LA/72265LA SUPERSYNC FIFO™
8,192 x 18, 16,384 x 18

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE

RCLK

Q0 - Q

WCLK

t

ENS

n

W

x

ENH

t

RTS

W

x+1

t

SKEW2

t

1

2

12

t

RTS

t

t

ENH

REF

t

t

PAE

HF

t

PAF

t

ENS

3

t

ENH

t

A

t

REF

(4)

W

1

(5)

4

t

W

2

t

ENH

A

4670 drw 15

W

3

NOTES:

1. Retransmit setup is complete after OR returns LOW.

2. No more than D - 2 words may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, IR will be LOW throughout the
Retransmit setup procedure. D = 8,193 for the IDT72255LA and 16,385 for the IDT72265LA.

3.

OE

= LOW

4. W1, W2, W3 = first, second and third words written to the FIFO after Master Reset.

5.OR goes LOW at 60 ns + 2 RCLK cycles + tREF.

Figure 12. Retransmit Timing (FWFT Mode)

WCLK

t

t

ENS

t

LDS

t

DS

SI

BIT 0

NOTE:

1. X = 12 for the IDT72255LA and X = 13 for the IDT72265LA.

ENH

t

LDH

EMPTY OFFSET

BIT X

t

ENH

t

LDH

t

(1)

BIT 0

FULL OFFSET

BIT X

DH

(1)

4670 drw 16

Figure 13. Serial Loading of Programmable Flag Registers (IDT Standard and FWFT Modes)

21

IDT72255LA/72265LA SUPERSYNC FIFO™
8,192 x 18, 16,384 x 18

WCLK

tCLKH

tCLK

tCLKL

tLDS

tLDH

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE

tLDH

D0 - D

RCLK

Q0 - Q

NOTE:

1.

OE

15

15

= LOW

tENS

t

DS

PAE

OFFSET

tENH

tDH

PAF

OFFSET

tENH

tDH

Figure 14. Parallel Loading of Programmable Flag Registers (IDT Standard and FWFT Modes)

t

CLK

t

CLKH

DATA IN OUTPUT

REGISTER

t

t

ENS

t

CLKL

LDS

t

LDH

t

ENH

t

A

t

LDH

t

ENH

PAE

OFFSET

t

A

PAF

OFFSET

4670 drw 17

4670 drw 18

Figure 15. Parallel Read of Programmable Flag Registers (IDT Standard and FWFT Modes)

t

WCLK

CLKH

t

ENS

t

CLKL

t

ENH

D - (m+1) words in FIFO

1

(2)

2

t

PAF

RCLK

NOTES:

1. m =

PAF

2. D = maximum FIFO depth.

3.

4.

offset .

In IDT Standard mode: D = 8,192 for the IDT72255LA and 16,384 for the IDT72265LA.
In FWFT mode: D = 8,193 for the IDT72255LA and 16,385 for the IDT72265LA.
t

SKEW2

is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that

time between the rising edge of RCLK and the rising edge of WCLK is less than t

PAF

is asserted and updated on the rising edge of WCLK only.

SKEW2

Figure 16. Programmable Almost-Full Flag Timing (IDT Standard and FWFT Modes)

t

SKEW2

t

ENS

, then the

12

t

PAF

(3)

D - m words in FIFO

t

ENH

PAF

will go HIGH (after one WCLK cycle plus t

PAF

deassertion time may be delayed one extra WCLK cycle.

(2)

D-(m+1) words
in FIFO

4670 drw 19

PAF

2)

(

). If the

22

IDT72255LA/72265LA SUPERSYNC FIFO™
8,192 x 18, 16,384 x 18

t

CLKH

t

CLKL

WCLK

t

t

ENS

ENH

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE

(2)

,

(3)

(4)

t

t

SKEW2

12 12

PAE

t

ENS

n+1 words in FIFO
n+2 words in FIFO

RCLK

n words in FIFO
n+1 words in FIFO

NOTES:

1. n =

PAE

offset.

2. For IDT Standard mode

3. For FWFT mode.

4.

tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that
time between the rising edge of WCLK and the rising edge of RCLK is less than t

5.

PAE

is asserted and updated on the rising edge of WCLK only.

SKEW2, then the

Figure 17. Programmable Almost-Empty Flag Timing (IDT Standard and FWFT Modes)

(2)

,

(3)

t

ENH

PAE

will go HIGH (after one RCLK cycle plus tPAE). If the

PAE

deassertion may be delayed one extra RCLK cycle.

t

PAE

n words in FIFO
n+1 words in FIFO

(2)

4670 drw 20

,

(3)

t

CLKH

t

CLKL

WCLK

t

ENH

t

HF

D/2 + 1 words in FIFO

[

+ 2] words in FIFO

t

HF

(1)

,

(2)

D/2 words in FIFO

[

+ 1] words in FIFO

t

ENS

(1)

,

(2)

RCLK

t

ENS

NOTES:

1. For IDT Standard mode: D = maximum FIFO depth. D = 8,192 for the IDT72255LA and 16,384 for the IDT72265LA.

2. For FWFT mode: D = maximum FIFO depth. D = 8,193 for the IDT72255LA and 16,385 for the IDT72265LA.

Figure 18. Half-Full Flag Timing (IDT Standard and FWFT Modes)

D/2 words in FIFO

[

+ 1] words in FIFO

4670 drw 21

(1)

,

(2)

23

IDT72255LA/72265LA SUPERSYNC FIFO™
8,192 x 18, 16,384 x 18

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE

OPTIONAL CONFIGURATIONS

WIDTH EXPANSION CONFIGURATION

Word width may be increased simply by connecting to­gether the control signals of multiple devices. Status flags can
be detected from any one device. The exceptions are the
and FF functions in IDT Standard mode and the IR and
functions in FWFT mode. Because of variations in skew
between RCLK and WCLK, it is possible for EF/FF deassertion
and IR/OR assertion to vary by one cycle between FIFOs. In

PARTIAL RESET ( )

MASTER RESET (

FIRST WORD FALL THROUGH/

SERIAL INPUT (FWFT/SI)

RETRANSMIT (

m + n m n

FULL FLAG/INPUT READY (
FULL FLAG/INPUT READY ( / ) #2

GATE

DATA IN

(1)

PROGRAMMABLE (

)

)

D0 - Dm

WRITE CLOCK (WCLK)

WRITE ENABLE (

LOAD (

/ )

#1

HALF-FULL FLAG (

)
)

)
)

IDT
72255LA
72265LA

FIFO

#1

Dm

EF

OR

+1

m

IDT Standard mode, such problems can be avoided by
creating composite flags, that is, ANDing EF of every FIFO,
and separately ANDing FF of every FIFO. In FWFT mode,
composite flags can be created by ORing OR of every FIFO,
and separately ORing IR of every FIFO.

Figure 23 demonstrates a width expansion using two
IDT72255LA/72265LA devices. D0 - D17 from each device
form a 36-bit wide input bus and Q0-Q17 from each device form
a 36-bit wide output bus. Any word width can be attained by
adding additional IDT72255LA/72265LA devices.

- Dn

READ CLOCK (RCLK)

IDT
72255LA
72265LA

FIFO

#2

READ ENABLE (
OUTPUT ENABLE (

PROGRAMMABLE ( )

EMPTY FLAG/OUTPUT READY ( / ) #1
EMPTY FLAG/OUTPUT READY (

n

Qm

+1

- Qn

)

)

m + n

/ ) #2

DATA OUT

GATE

(1)

Q

0

- Qm

NOTES:

1. Use an AND gate in IDT Standard mode, an OR gate in FWFT mode.

2. Do not connect any output control signals directly together.

3. FIFO #1 and FIFO #2 must be the same depth, but may be different word widths.

Figure 19. Block Diagram of 8,192 x 36 and 16,384 x 36 Width Expansion

DEPTH EXPANSION CONFIGURATION (FWFT MODE
ONLY)

The IDT72255LA can easily be adapted to applications
requiring depths greater than 8,192 and 16,384 for the
IDT72265LA with an 18-bit bus width. In FWFT mode, the
FIFOs can be connected in series (the data outputs of one
FIFO connected to the data inputs of the next) with no external
logic necessary. The resulting configuration provides a total
depth equivalent to the sum of the depths associated with
each single FIFO. Figure 24 shows a depth expansion using

outputs of the last FIFO in the chain–no read operation is
necessary but the RCLK of each FIFO must be free-running.
Each time the data word appears at the outputs of one FIFO,
that device's OR line goes LOW, enabling a write to the next
FIFO in line.

For an empty expansion configuration, the amount of time
it takes for OR of the last FIFO in the chain to go LOW (i.e. valid
data to appear on the last FIFO's outputs) after a word has
been written to the first FIFO is the sum of the delays for each
individual FIFO:

two IDT72255LA/72265LA devices.

Care should be taken to select FWFT mode during Master
Reset for all FIFOs in the depth expansion configuration. The
first word written to an empty configuration will pass from one
FIFO to the next ("ripple down") until it finally appears at the

where N is the number of FIFOs in the expansion and TRCLK
is the RCLK period. Note that extra cycles should be added
for the possibility that the tSKEW3 specification is not met

4670 drw 22

(N – 1)*(4*transfer clock) + 3*TRCLK

24

IDT72255LA/72265LA SUPERSYNC FIFO™
8,192 x 18, 16,384 x 18

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE

FWFT/SI

WRITE CLOCK

WRITE ENABLE

INPUT READY

DATA IN

n n

WCLK

Dn

•

TRANSFER CLOCK

FWFT/SI FWFT/SI

IDT
72255LA
72265LA

Figure 20. Block Diagram of 16,384 x 18 and 32,768 x 18 Depth Expansion

RCLK

Qn

•

between WCLK and transfer clock, or RCLK and transfer
clock, for the OR flag.

The "ripple down" delay is only noticeable for the first word
written to an empty depth expansion configuration. There will
be no delay evident for subsequent words written to the
configuration.

The first free location created by reading from a full depth
expansion configuration will "bubble up" from the last FIFO to
the previous one until it finally moves into the first FIFO of the
chain. Each time a free location is created in one FIFO of the
chain, that FIFO's IR line goes LOW, enabling the preceding
FIFO to write a word to fill it.

For a full expansion configuration, the amount of time it
takes for IR of the first FIFO in the chain to go LOW after a word

READ CLOCK

READ ENABLE

OUTPUT READY

OUTPUT ENABLE

DATA OUT

4670 drw 23

GND

n

WCLK

Dn

IDT
72255LA
72265LA

RCLK

Qn

has been read from the last FIFO is the sum of the delays for
each individual FIFO:

(N – 1)*(3*transfer clock) + 2 TWCLK

where N is the number of FIFOs in the expansion and TWCLK
is the WCLK period. Note that extra cycles should be added
for the possibility that the tSKEW1 specification is not met
between RCLK and transfer clock, or WCLK and transfer
clock, for the IR flag.

The Transfer Clock line should be tied to either WCLK or
RCLK, whichever is faster. Both these actions result in data
moving, as quickly as possible, to the end of the chain and free
locations to the beginning of the chain.

25

IDT72255LA/72265LA SUPERSYNC FIFO™
8,192 x 18, 16,384 x 18

ORDERING INFORMATION

IDT XXXXX

Device Type

X

Power

XX

Speed

X

Package

X

Process /

Temperature

Range

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE

BLANK

(1)

I
PF

TF

Commercial (0°C to +70°C)
Industrial (–40°C to +85°C)

Thin Plastic Quad Flatpack (TQFP, PN64-1)
Slim Thin Quad Flatpack (STQFP, PP64-1)

10
15
20

LA

72255
72265

NOTE:

1.

Industrial temperature range product for 15ns and 20ns speed grade are available as a standard device.

Commercial
Com'l & Ind'l
Com'l & Ind'l

Clock Cycle Time (tCLK)
Speed in Nanoseconds

Low Power
8,192 x 18 SuperSync FIFO

16,384 x 18 SuperSync FIFO

4670 drw 24

DATASHEET DOCUMENT HISTORY

04/19/2001 pgs. 1, 5, 6 and 26.

26

CMOS SUPERSYNC FIFO™
8,192 x 18
16,384 x 18

PRELIMINARY

IDT72255LA
IDT72265LA

Integrated Device Technology, Inc.

ADDENDUM

DIFFERENCES BETWEEN THE IDT72255LA/72265LA AND IDT72255L/72265L

IDT has improved the performance of the IDT72255/72265 SuperSync™ FIFOs. The new versions are designated by the
“LA” mark. The LA part is pin-for-pin compatible with the original “L” version. Some differences exist between the two versions.
The following table details these differences.

Item NE W PART

72255LA
72265LA

Pi n #3 DC ( D on’ t C a r e) - T her e

is no r es tr i ct ion on
W C LK a nd R C LK. See
note 1.

Fi r s t W or d La t ency

60ns

2

+ t

REF

+ 1 T

RCLK

( I D T Sta ndard M ode)

Fi r s t W or d La t ency

60ns

2

+ t

REF

+ 2 T

RCLK

( FW F T M ode)

Ret r a ns m it La tenc y

60ns

2

+ t

REF

+ 1 T

RCLK

( I D T Sta ndard M ode)

Ret r a ns m it La tenc y

60ns

2

+ t

REF

+ 2 T

RCLK

( FW F T M ode)

FS ( F r equenc y Sel ec t) I n t he LA pa r t t his pi n m ust

4

t

4

t

4

t

4

t

FWL1

=10*T f3 + 2T

FWL2

=10*T f3 + 3T

RTF1

=14*T f3 + 3T

RTF2

=14*T f3 + 4T

OLD PART

72255L
72265L

RCLK

RCLK

RCLK

RCLK

4

(ns)

4

(ns)

4

(ns)

4

(ns)

Comments

be ti ed to ei ther V

CC

or GND
a nd m ust not toggl e a f ter
reset.

Fi r s t w or d l a tenc y i n t he LA
pa r t i s a fi x ed va l ue,
independent of the
fr equency of R C LK or
WCLK.

Fi r s t w or d l a tenc y i n t he LA
pa r t i s a fi x ed va l ue,
independent of the
fr equency of R C LK or W C LK

Retransmit latency in the LA
pa r t i s a fi x ed va l ue,
independent of the
fr equency of R C LK or W C LK

Retransmit latency in the LA
pa r t i s a fi x ed va l ue,
independent of the
fr equency of R C LK or W C LK

I

CC1

I

CC2

Typical I

NOTES:

1. WCLK and RCLK can vary independently and can be stopped. There is no restriction on operating WCLK and RCLK.

2. This is t

3. Tf is the period of the ‘selected clock’.

4. T

5. Typical I

SKEW3

RCLK is the cycle period of the read clock.

CC1 is based on VCC = 5V, tA =25°C, fS= WCLK frequency = RCLK frequency (in MHz using TTL levels), data switching at fS/2,

CL = Capacitive Load (in pF).

CC1

.

5

80m A 180mA Act iv e s upply c ur r ent
20m A 15mA Sta ndby cur r ent
15 + 2.1* fS + 0.02* CL*f

(mA)

S

Not Given Typical I

CC1

ca l c ul a ti on.

Cur r ent

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE APRIL 2001

© 2001 Integrated Device Technology, Inc

1