Integrated Device Technology, Inc.
W
CMOS ASYNCHRONOUS FIFO
256 x 9, 512 x 9, 1K x 9
IDT7200L
IDT7201LA
IDT7202LA
FEATURES:
• First-In/First-Out dual-port memory
• 256 x 9 organization (IDT7200)
• 512 x 9 organization (IDT7201)
• 1K x 9 organization (IDT7202)
• Low power consumption
— Active: 770mW (max.)
—Power-down: 2.75mW (max.)
• Ultra high speed—12ns access time
• Asynchronous and simultaneous read and write
• Fully expandable by both word depth and/or bit width
• Pin and functionally compatible with 720X family
• Status Flags: Empty, Half-Full, Full
• Auto-retransmit capability
• High-performance CEMOS technology
• Military product compliant to MIL-STD-883, Class B
• Standard Military Drawing #5962-87531, 5962-89666,
5962-89863 and 5962-89536 are listed on this function
• Industrial temperature range (-40oC to +85oC) is
available, tested to military electrical specifications
DESCRIPTION:
The IDT7200/7201/7202 are dual-port memories that load
and empty data on a first-in/first-out basis. The devices use
Full and Empty flags to prevent data overflow and underflow
and expansion logic to allow for unlimited expansion capability
in both word size and depth.
The reads and writes are internally sequential through the
use of ring pointers, with no address information required to
load and unload data. Data is toggled in and out of the devices
through the use of the Write (W) and Read (R) pins.
The devices utilizes a 9-bit wide data array to allow for
control and parity bits at the user’s option. This feature is
especially useful in data communications applications where
it is necessary to use a parity bit for transmission/reception
error checking. It also features a Retransmit (RT) capability
that allows for reset of the read pointer to its initial position
when RT is pulsed low to allow for retransmission from the
beginning of data. A Half-Full Flag is available in the single
device mode and width expansion modes.
The IDT7200/7201/7202 are fabricated using IDT’s highspeed CMOS technology. They are designed for those
applications requiring asynchronous and simultaneous read/
writes in multiprocessing and rate buffer applications. Military
grade product is manufactured in compliance with the latest
revision of MIL-STD-883, Class B.
FUNCTIONAL BLOCK DIAGRAM
DATA INPUTS
0(D –D8)
WRITE
CONTROL
WRITE
POINTER
R
XI
The IDT logo is a trademark of Integrated Device Technology, Inc.
READ
CONTROL
EXPANSION
THREESTATE
BUFFERS
FLAG
LOGIC
LOGIC
MILITARY AND COMMERCIAL TEMPERATURE RANGES DECEMBER 1996
1996 Integrated Device Technology, Inc. DSC-2679/7
For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.
5.03 1
RAM
ARRAY
256 x 9
512 x 9
1024 x 9
DATA OUTPUTS
0(Q –Q8)
EF
FF
XO/HF
READ
POINTER
RS
RESET
LOGIC
FL/RT
2679 drw 01
IDT7200/7201A/7202A CMOS ASYNCHRONOUS FIFO
256 x 9, 512 x 9 and 1K x 9 MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
W
D8
1
2
28
27
D3 D5326
D2 D6425
D1 D7524
D0
XI RS
FF EF
Q0
P28-1,
P28-2,
623
D28-1,
D28-3,
722
E28-2,
821
SO28-3
920
Q1 Q710 19
Q2 Q611 18
Q3 Q512 17
Q8 Q413 16
GND
14 15
DIP/SOIC/CERPACK
TOP VIEW
NOTE:
1. CERPACK (E28-2) and 600-mil-wide DIP (P28-1 and D28-1) not available
for 7200.
VCC
D4
FL/RT
XO/HF
R
2679 drw 02a
INDEX
D
2
D
1
D
0
XI
FF
Q
0
Q
1
5
6
7
8
9
10
11
D8
D3
W
4
3 2132 31 30
J32-1
L32-1
NC 12
Q
2
13
14 15 16 17 18 19 20
Q3
Q8
GND
LCC/PLCC
TOP VIEW
NOTE:
1. LCC (L32-1) not available for 7200.
CC
D4
NC
&
NC
D5
V
D
29
28
27
26
25
24
23
22
21
4
R
Q5
Q
6
D
7
NC
FL/RT
RS
EF
XO/HF
Q
7
Q
6
2679 drw 02b
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol Rating Com’l. Mil. Unit
V
TERM Terminal Voltage –0.5 to +7.0 –0.5 to +7.0 V
with Respect
to GND
T
A Operating 0 to +70 –55 to +125 °C
Temperature
T
BIAS Temperature –55 to +125 –65 to +135 °C
Under Bias
T
STG Storage –55 to +125 –65 to +155 °C
Temperature
I
OUT DC Output 50 50 mA
Current
NOTE: 2679 tbl 01
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliabilty.
CAPACITANCE (TA = +25°C, f = 1.0 MHz)
Symbol Parameter
IN Input Capacitance VIN = 0V 8 pF
C
OUT Output Capacitance VOUT = 0V 8 pF
C
NOTE: 2679 tbl 02
1. This parameter is sampled and not 100% tested.
(1)
Condition Max. Unit
RECOMMENDED DC OPERATING
CONDITIONS
Symbol Parameter Min. Typ. Max. Unit
V
CCM
V
CCC
GND Supply Voltage 0 0 0 V
(1)
V
IH
(1)
V
IH
(2)
V
IL
NOTE: 2679 tbl 03
1. VIH = 2.6V for XI input (commercial).
IH = 2.8V for
V
2. 1.5V undershoots are allowed for 10ns once per cycle.
Military Supply
Voltage
Commercial Supply
Voltage
Input High Voltage
Commercial
Input High Voltage
Mlitary
Input Low Voltage
Commercial and
Military
XI
input (military).
4.5 5.0 5.5 V
4.5 5.0 5.5 V
2.0 — — V
2.2 — — V
— — 0.8 V
5.03 2
IDT7200/7201A/7202A CMOS ASYNCHRONOUS FIFO
256 x 9, 512 x 9 and 1K x 9 MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 5.0V±10%, TA = 0°C to +70°C; Military: VCC = 5.0V±10%, TA = –55°C to +125°C)
IDT7200L IDT7200L IDT7200L
IDT7201LA IDT7201LA IDT7201LA
IDT7202LA IDT7202LA IDT7202LA
Commercial Military Commercial
t
A = 12, 15, 20 ns tA = 20 ns tA = 25, 35 ns
Symbol Parameter Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit
(1)
LI
I
(2)
LO
I
OH Output Logic “1” Voltage IOH = –2mA 2.4 — — 2.4 — — 2.4 — — V
V
OL Output Logic “0” Voltage IOL = 8mA — — 0.4 — — 0.4 — — 0.4 V
V
(3)
CC1
I
(3)
CC2
I
CC3(L)
I
Input Leakage Current (Any Input) –1 — 1 –10 — 10 –1 — 1 µA
Output Leakage Current –10 — 10 –10 — 10 –10 — 10 µA
Active Power Supply Current — — 125
(4)
— — 140
(4)
— — 125
(4)
mA
Standby Current (R=W=RS=FL/RT=VIH)——15——20——15mA
(3)
Power Down Current (All Input = VCC - 0.2V) — — 0.5 — — 0.9 — — 0.5 mA
NOTES: 2679 tbl 05
1. Measurements with 0.4 ≤ VIN ≤ VCC.
2.R ≥ V
3. I
4. Tested at f = 20MHz.
IH, 0.4 ≤ VOUT ≤ VCC.
CC measurements are made with outputs open (only capacitive loading).
2679 tbl 04
DC ELECTRICAL CHARACTERISTICS (Continued)
(Commercial: VCC = 5.0V±10%, TA = 0°C to +70°C; Military: VCC = 5.0V±10%, TA = –55°C to +125°C)
IDT7200L IDT7200L IDT7200L
IDT7201LA IDT7201LA IDT7201LA
IDT7202LA IDT7202LA IDT7202LA
Military Commercial Military
t
A = 30, 40 ns tA = 50 ns tA = 50, 65, 80, 120 ns
Symbol Parameter Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit
(1)
LI
I
(2)
LO
I
OH Output Logic “1” Voltage IOH = –2mA 2.4 — — 2.4 — — 2.4 — — V
V
OL Output Logic “0” Voltage IOL = 8mA — — 0.4 — — 0.4 — — 0.4 V
V
(3)
CC1
I
(3)
CC2
I
CC3(L)
I
NOTES: 2679 tbl 05
1. Measurements with 0.4 ≤ VIN ≤ VCC.
2.R ≥ V
3. I
CC measurements are made with outputs open (only capacitive loading).
4. Tested at f = 20MHz.
Input Leakage Current (Any Input) –10 — 10 –1 — 1 –10 — 10 µA
Output Leakage Current –10 — 10 –10 — 10 –10 — 10 µA
Active Power Supply Current — — 140
(4)
— 50 80 — 70 100 mA
Standby Current (R=W=RS=FL/RT=VIH)——20—58—815mA
(3)
Power Down Current (All Input = VCC - 0.2V) — — 0.9 — — 0.5 — — 0.9 mA
IH, 0.4 ≤ VOUT ≤ VCC.
5.03 3
IDT7200/7201A/7202A CMOS ASYNCHRONOUS FIFO
256 x 9, 512 x 9 and 1K x 9 MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS
(1)
(Commercial: VCC = 5.0V±10%, TA = 0°C to +70°C; Military: VCC = 5.0V±10%, TA = –55°C to +125°C)
Commercial Com'l & Mil. Com'l Military Com'l
7200L12 7200L15 7200L20 7200L25 7200L30 7200L35
7201LA12 7201LA15 7201LA20 7201LA25 7201LA30 7201LA35
7202LA12 7202LA15 7202LA20 7202LA25 7202LA30 7202LA35
Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
S Shift Frequency — 50 — 40 — 33.3 — 28.5 — 25 — 22.2 MHz
t
RC Read Cycle Time 20 — 25 — 30 — 35 — 40 — 45 — ns
t
A Access Time — 12 — 15 — 20 — 25 — 30 — 35 ns
t
RR Read Recovery Time 8 — 10 — 10 — 10 — 10 — 10 — ns
t
RPW Read Pulse Width
t
RLZ Read Pulse Low to Data Bus at Low Z
t
WLZ Write Pulse High to Data Bus at Low Z
t
DV Data Valid from Read Pulse High 5 — 5 — 5 — 5 — 5 — 5 — ns
t
RHZ Read Pulse High to Data Bus at High Z
t
WC Write Cycle Time 20 — 25 — 30 — 35 — 40 — 45 — ns
t
WPW Write Pulse Width
t
WR Write Recovery Time 8 — 10 — 10 — 10 — 10 — 10 — ns
t
DS Data Set-up Time 9 — 11 — 12 — 15 — 18 — 18 — ns
t
DH Data Hold Time 0 — 0 — 0 — 0 — 0 — 0 — ns
t
RSC Reset Cycle Time 20 — 25 — 30 — 35 — 40 — 45 — ns
t
RS Reset Pulse Width
t
RSS Reset Set-up Time
t
RSR Reset Recovery Time 8 — 10 — 10 — 10 — 10 — 10 — ns
t
RTC Retransmit Cycle Time 20 — 25 — 30 — 35 — 40 — 45 — ns
t
RT Retransmit Pulse Width
t
RTS Retransmit Set-up Time
t
RTR Retransmit Recovery Time 8 — 10 — 10 — 10 — 10 — 10 — ns
t
EFL Reset to Empty Flag Low — 12 — 25 — 30 — 35 — 40 — 45 ns
t
HFH,FFH Reset to Half-Full and Full Flag High — 17 — 25 — 30 — 35 — 40 — 45 ns
t
RTF Retransmit Low to Flags Valid — 20 — 25 — 30 — 35 — 40 — 45 ns
t
REF Read Low to Empty Flag Low — 12 — 15 — 20 — 25 — 30 — 30 ns
t
RFF Read High to Full Flag High — 14 — 15 — 20 — 25 — 30 — 30 ns
t
RPE Read Pulse Width after
t
WEF Write High to Empty Flag High — 12 — 15 — 20 — 25 — 30 — 30 ns
t
WFF Write Low to Full Flag Low — 14 — 15 — 20 — 25 — 30 — 30 ns
t
WHF Write Low to Half-Full Flag Low — 17 — 25 — 30 — 35 — 40 — 45 ns
t
RHF Read High to Half-Full Flag High — 17 — 25 — 30 — 35 — 40 — 45 ns
t
WPF Write Pulse Width after
t
XOL Read/Write to
t
XOH Read/Write to
t
XI
t
XIR
t
XIS
t
NOTES: 2679 tbl 06
1. Timings referenced as in AC Test Conditions. 3. Values guaranteed by design, not currently tested.
2. Pulse widths less than minimum value are not allowed. 4. Only applies to read data flow-through mode.
XI
Pulse Width
XI
Recovery Time 8 — 10 — 10 — 10 — 10 — 10 — ns
XI
Set-up Time 8 — 10 — 10 — 10 — 10 — 10 — ns
(2)
(2)
(2)
(3)
(2)
(3)
EF
High 12 — 15 — 20 — 25 — 30 — 35 — ns
FF
High 12 — 15 — 20 — 25 — 30 — 35 — ns
XO
Low — 12 — 15 — 20 — 25 — 30 — 35 ns
XO
High — 12 — 15 — 20 — 25 — 30 — 35 ns
(2)
12 — 15 — 20 — 25 — 30 — 35 — ns
(3)
3—5—5—5— 5 —5—ns
(3, 4)
3—5—5—5— 5 —10—ns
(3)
— 12 — 15 — 15 — 18 — 20 — 20 ns
12 — 15 — 20 — 25 — 30 — 35 — ns
12 — 15 — 20 — 25 — 30 — 35 — ns
12 — 15 — 20 — 25 — 30 — 35 — ns
12 — 15 — 20 — 25 — 30 — 35 — ns
12 — 15 — 20 — 25 — 30 — 35 — ns
12 — 15 — 20 — 25 — 30 — 35 — ns
5.03 4
IDT7200/7201A/7202A CMOS ASYNCHRONOUS FIFO
256 x 9, 512 x 9 and 1K x 9 MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS
(1)
(Continued)
(Commercial: VCC = 5.0V±10%, TA = 0°C to +70°C; Military: VCC = 5.0V±10%, TA = –55°C to +125°C)
Military Com'l & Mil. Military
7200 L40 7200L50 7200L65 7200L80 7200L120
7201LA40 7201LA50 7201LA65 7201LA80 7201LA120
7202LA40 7202LA50 7202LA65 7202LA80 7202LA120
Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
t
S Shift Frequency — 20 — 15 — 12.5 — 10 — 7 MHz
RC Read Cycle Time 50 — 65 — 80 — 100 — 140 — ns
t
A Access Time — 40 — 50 — 65 — 80 — 120 ns
t
RR Read Recovery Time 10 — 15 — 15 — 20 — 20 — ns
t
RPW Read Pulse Width
t
RLZ Read Pulse Low to Data Bus at Low Z
t
WLZ Write Pulse High to Data Bus at Low Z
t
DV Data Valid from Read Pulse High 5 — 5 — 5 — 5 — 5 — ns
t
RHZ Read Pulse High to Data Bus at High Z
t
WC Write Cycle Time 50 — 65 — 80 — 100 — 140 — ns
t
WPW Write Pulse Width
t
WR Write Recovery Time 10 — 15 — 15 — 20 — 20 — ns
t
DS Data Set-up Time 20 — 30 — 30 — 40 — 40 — ns
t
DH Data Hold Time 0 — 5 — 10 — 10 — 10 — ns
t
RSC Reset Cycle Time 50 — 65 — 80 — 100 — 140 — ns
t
RS Reset Pulse Width
t
RSS Reset Set-up Time
t
RSR Reset Recovery Time 10 — 15 — 15 — 20 — 20 — ns
t
RTC Retransmit Cycle Time 50 — 65 — 80 — 100 — 140 — ns
t
RT Retransmit Pulse Width
t
RTS Retransmit Set-up Time
t
RTR Retransmit Recovery Time 10 — 15 — 15 — 20 — 20 — ns
t
EFL Reset to Empty Flag Low — 50 — 65 — 80 — 100 — 140 ns
t
HFH,FFH Reset to Half-Full and Full Flag High — 50 — 65 — 80 — 100 — 140 ns
t
RTF Retransmit Low to Flags Valid — 50 — 65 — 80 — 100 — 140 ns
t
REF Read Low to Empty Flag Low — 30 — 45 — 60 — 60 — 60 ns
t
RFF Read High to Full Flag High — 35 — 45 — 60 — 60 — 60 ns
t
RPE Read Pulse Width after
t
WEF Write High to Empty Flag High — 35 — 45 — 60 — 60 — 60 ns
t
WFF Write Low to Full Flag Low — 35 — 45 — 60 — 60 — 60 ns
t
WHF Write Low to Half-Full Flag Low — 50 — 65 — 80 — 100 — 140 ns
t
RHF Read High to Half-Full Flag High — 50 — 65 — 80 — 100 — 140 ns
t
WPF Write Pulse Width after
t
XOL Read/Write to
t
XOH Read/Write to
t
XI
t
XIR
t
XIS
t
NOTES: 2679 tbl 07
1. Timings referenced as in AC Test Conditions 4. Values guaranteed by design, not currently tested.
2. Speed grades 65, 80 and 120 not available in the CERPACK 5. Only applies to read data flow-through mode.
3. Pulse widths less than minimum value are not allowed.
XI
Pulse Width
XI
Recovery Time 10 — 10 — 10 — 10 — 10 — ns
XI
Set-up Time 10 — 15 — 15 — 15 — 15 — ns
(3)
(3)
(3)
(4)
(3)
(4)
EF
High 40 — 50 — 65 — 80 — 120 — ns
FF
High 40 — 50 — 65 — 80 — 120 — ns
XO
Low — 40 — 50 — 65 — 80 — 120 ns
XO
High — 40 — 50 — 65 — 80 — 120 ns
(3)
40 — 50 — 65 — 80 — 120 — ns
(4)
5 — 10 — 10 — 10 — 10 — ns
(4, 5)
10 — 15 — 15 — 20 — 20 — ns
(4)
— 25 — 30 — 30 — 30 — 35 ns
40 — 50 — 65 — 80 — 120 — ns
40 — 50 — 65 — 80 — 120 — ns
40 — 50 — 65 — 80 — 120 — ns
40 — 50 — 65 — 80 — 120 — ns
40 — 50 — 65 — 80 — 120 — ns
40 — 50 — 65 — 80 — 120 — ns
(2)
5.03 5
IDT7200/7201A/7202A CMOS ASYNCHRONOUS FIFO
256 x 9, 512 x 9 and 1K x 9 MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC TEST CONDITIONS
Input Pulse Levels GND to 3.0V
Input Rise/Fall Times 5ns
Input Timing Reference Levels 1.5V
Output Reference Levels 1.5V
Output Load See Figure 1
2679 tbl 08
SIGNAL DESCRIPTIONS
INPUTS:
DATA IN (D0 – D8)
Data inputs for 9-bit wide data.
CONTROLS:
RESET (
taken to a low state. During reset, both internal read and write
pointers are set to the first location. A reset is required after
power up before a write operation can take place. Both the
Read Enable (
the high state during the window shown in Figure 2, (i.e.,
tRSS before the rising edge of
until tRSR after the rising edge of
will be reset to high after Reset (
WRITE ENABLE (
Full Flag (FF) is not set. Data set-up and hold times must be
adhered to with respect to the rising edge of the Write Enable
(W). Data is stored in the RAM array sequentially and
independently of any on-going read operation.
the next write operation, the Half-Full Flag (HF) will be set to
low and will remain set until the difference between the write
pointer and read pointer is less than or equal to one half of the
total memory of the device. The Half-Full Flag (HF) is then
reset by the rising edge of the read operation.
inhibiting further write operations. Upon the completion of a
valid read operation, the Full Flag (FF) will go high after t
allowing a valid write to begin. When the FIFO is full, the
internal write pointer is blocked from W, so external changes
in W will not affect the FIFO when it is full.
READ ENABLE (
Enable (R) provided the Empty Flag (EF) is not set. The data
is accessed on a First-In/First-Out basis, independent of any
ongoing write operations. After Read Enable (R) goes high,
RSRS)
Reset is accomplished whenever the Reset (RS) input is
RR) and Write Enable (
WW) inputs must be in
RSRS) and should not change
RSRS. Half-Full Flag (
HFHF)
RSRS).
WW)
A write cycle is initiated on the falling edge of this input if the
After half of the memory is filled and at the falling edge of
To prevent data overflow, the Full Flag (FF) will go low,
RFF,
RR)
A read cycle is initiated on the falling edge of the Read
5V
1.1K
TO
OUTPUT
PIN
680Ω
or equivalent circuit
Figure 1. Output Load
* Includes scope and jig capacitances.
30pF*
2679 drw 03
the Data Outputs (Q0 – Q8) will return to a high impedance
condition until the next Read operation. When all data has
been read from the FIFO, the Empty Flag (EF) will go low,
allowing the “final” read cycle but inhibiting further read
operations with the data outputs remaining in a high impedance state. Once a valid write operation has been accomplished, the Empty Flag (EF) will go high after tWEF and a valid
Read can then begin. When the FIFO is empty, the internal
read pointer is blocked from R so external changes in R will not
affect the FIFO when it is empty.
FIRST LOAD/RETRANSMIT (
FLFL/
RTRT)
This is a dual-purpose input. In the Depth Expansion Mode,
this pin is grounded to indicate that it is the first loaded (see
Operating Modes). In the Single Device Mode, this pin acts as
the restransmit input. The Single Device Mode is initiated by
grounding the Expansion In (XI).
The IDT7200/7201A/7202A can be made to retransmit
data when the Retransmit Enable control (RT) input is pulsed
low. A retransmit operation will set the internal read pointer to
the first location and will not affect the write pointer. Read
Enable (R) and Write Enable (W) must be in the high state
during retransmit. This feature is useful when less than 256/
512/1024 writes are performed between resets. The retransmit feature is not compatible with the Depth Expansion Mode
and will affect the Half-Full Flag (HF), depending on the
relative locations of the read and write pointers.
EXPANSION IN (
XIXI)
This input is a dual-purpose pin. Expansion In (XI) is
grounded to indicate an operation in the single device mode.
Expansion In (XI) is connected to Expansion Out (XO) of the
previous device in the Depth Expansion or Daisy Chain Mode.
OUTPUTS:
FULL FLAG (
The Full Flag (FF) will go low, inhibiting further write
operation, when the write pointer is one location less than the
read pointer, indicating that the device is full. If the read
pointer is not moved after Reset (RS), the Full-Flag (FF) will go
low after 256 writes for IDT7200, 512 writes for the IDT7201A
and 1024 writes for the IDT7202A.
FFFF)
5.03 6
IDT7200/7201A/7202A CMOS ASYNCHRONOUS FIFO
256 x 9, 512 x 9 and 1K x 9 MILITARY AND COMMERCIAL TEMPERATURE RANGES
EMPTY FLAG (
EFEF)
The Empty Flag (EF) will go low, inhibiting further read
operations, when the read pointer is equal to the write pointer,
indicating that the device is empty.
EXPANSION OUT/HALF-FULL FLAG (
XOXO/
HFHF)
This is a dual-purpose output. In the single device mode,
when Expansion In (XI) is grounded, this output acts as an
indication of a half-full memory.
After half of the memory is filled and at the falling edge of
the next write operation, the Half-Full Flag (HF) will be set low
and will remain set until the difference between the write
RS
W
R
pointer and read pointer is less than or equal to one half of the
total memory of the device. The Half-Full Flag (HF) is then
reset by using rising edge of the read operation.
In the Depth Expansion Mode, Expansion In (XI) is connected to Expansion Out (XO) of the previous device. This
output acts as a signal to the next device in the Daisy Chain
by providing a pulse to the next device when the previous
device reaches the last location of memory.
DATA OUTPUTS (Q0 – Q8)
Data outputs for 9-bit wide data. This data is in a high
impedance condition whenever Read (R) is in a high state.
tRSC
tRS
tRSS
tRSS
tEFL
t
RSR
EF
HF, FF
NOTES:
1. EF, FF, HF may change status during Reset, but flags will be valid at tRSC.
2. W and R = V
IH around the rising edge of
t
RS
.
t
RC
A
Figure 2. Reset
t
RR
R
t
Q0 – Q
RLZ
8
t
WPW
DATA OUT VALID DATA OUT VALID
t
WC
t
DV
t
WR
W
t
D0 – D
DS
8
DATA IN VALID DATA IN VALID
t
DH
HFH
, tFFHt
2679 drw 04
t
RPW
t
A
t
RHZ
Figure 3. Asynchronous Write and Read Operation
5.03 7
2679 drw 05
IDT7200/7201A/7202A CMOS ASYNCHRONOUS FIFO
256 x 9, 512 x 9 and 1K x 9 MILITARY AND COMMERCIAL TEMPERATURE RANGES
W
FF
W
LAST WRITERIGNORED
WRITE
FIRST READ ADDITIONAL
READS
FIRST
WRITE
tWFF tRFF
2679 drw 06
Figure 4. Full Flag From Last Write to First Read
LAST READ
IGNORED
READ
FIRST WRITE ADDITIONAL
WRITES
FIRST
READ
R
tREF tWEF
EF
DATA OUT
HF, EF, FF
RT
W,R
t A
VALID VALID
Figure 5. Empty Flag From Last Read to First Write
t
RTC
t
RT
t
RTS
RTF
Figure 6. Retransmit
t
RTR
2679 drw 07
FLAG VALID
2679 drw 08
5.03 8
IDT7200/7201A/7202A CMOS ASYNCHRONOUS FIFO
256 x 9, 512 x 9 and 1K x 9 MILITARY AND COMMERCIAL TEMPERATURE RANGES
W
t WEF
EF
tRPE
R
2679 drw 09
Figure 7. Minimum Timing for an Empty Flag Coincident Read Pulse
R
t RFF
FF
t
WPF
W
HF
2679 drw 10
Figure 8. Minimum Timing for an Full Flag Coincident Write Pulse
W
t
RHF
R
HALF-FULL OR LESS
t
WHF
MORE THAN HALF-FULL
HALF-FULL OR LESS
2678 drw 11
Figure 9. Half-Full Flag Timing
WRITE TO
LAST PHYSICAL
LOCATION
W
READ FROM
LAST PHYSICAL
LOCATION
R
t
t
XOL
XOH
t
XOL
t
XOH
XO
2679 drw 12
Figure 10. Expansion Out
5.03 9
IDT7200/7201A/7202A CMOS ASYNCHRONOUS FIFO
256 x 9, 512 x 9 and 1K x 9 MILITARY AND COMMERCIAL TEMPERATURE RANGES
tXIRt XI
XI
t XIS
W
R
WRITE TO
FIRST PHYSICAL
LOCATION
Figure 11. Expansion In
OPERATING MODES:
Care must be taken to assure that the appropriate flag is
monitored by each system (i.e. FF is monitored on the device
where W is used; EF is monitored on the device where R is
used). For additional information, refer to Tech Note 8:
ating FIFOs on Full and Empty Boundary Conditions
Tech Note 6:
Designing with FIFOs.
Single Device Mode
A single IDT7200/7201A/7202A may be used when the
application requirements are for 256/512/1024 words or less.
The IDT7200/7201A/7202A is in a Single Device Configuration when the Expansion In (XI) control input is grounded (see
Figure 12).
Depth Expansion
The IDT7200/7201A/7202A can easily be adapted to applications when the requirements are for greater than 256/512/
1024 words. Figure 14 demonstrates Depth Expansion using
three IDT7200/7201A/7202As. Any depth can be attained by
adding additional IDT7200/7201A/7202As. The IDT7200/
7201A/7202A operates in the Depth Expansion mode when
the following conditions are met:
1. The first device must be designated by grounding the First
Load (FL) control input.
2. All other devices must have FL in the high state.
3. The Expansion Out (XO) pin of each device must be tied to
the Expansion In (XI) pin of the next device. See Figure 14.
4. External logic is needed to generate a composite Full Flag
(FF) and Empty Flag (EF). This requires the ORing of all
EF
s and ORing of all FFs (i.e. all must be set to generate the
correct composite FF or EF). See Figure 14.
5. The Retransmit (RT) function and Half-Full Flag (HF) are
not available in the Depth Expansion Mode.
For additional information, refer to Tech Note 9:
FIFOs or FIFO Modules.
Oper-
and
Cascading
t XIS
READ FROM
FIRST PHYSICAL
LOCATION
2679 drw 13
USAGE MODES:
Width Expansion
Word width may be increased simply by connecting the
corresponding input control signals of multiple devices. Status flags (EF, FF and HF) can be detected from any one device.
Figure 13 demonstrates an 18-bit word width by using two
IDT7200/7201A/7202As. Any word width can be attained by
adding additional IDT7200/7201A/7202As (Figure 13).
Bidirectional Operation
Applications which require data buffering between two
systems (each system capable of Read and Write operations)
can be achieved by pairing IDT7200/7201A/7202As as shown
in Figure 16. Both Depth Expansion and Width Expansion
may be used in this mode.
Data Flow-Through
Two types of flow-through modes are permitted, a read
flow-through and write flow-through mode. For the read flowthrough mode (Figure 17), the FIFO permits a reading of a
single word after writing one word of data into an empty FIFO.
The data is enabled on the bus in (t
edge of W, called the first write edge, and it remains on the
bus until the R line is raised from low-to-high, after which the
bus would go into a three-state mode after tRHZ ns. The EF line
would have a pulse showing temporary deassertion and then
would be asserted.
In the write flow-through mode (Figure 18), the FIFO
permits the writing of a single word of data immediately after
reading one word of data from a full FIFO. The R line causes
the FF to be deasserted but the W line being low causes it to
be asserted again in anticipation of a new data word. On the
rising edge of W, the new word is loaded in the FIFO. The
line must be toggled when FF is not asserted to write new data
in the FIFO and to increment the write pointer.
WEF + tA) ns after the rising
W
Compound Expansion
The two expansion techniques described above can be
applied together in a straightforward manner to achieve large
FIFO arrays (see Figure 15).
5.03 10
IDT7200/7201A/7202A CMOS ASYNCHRONOUS FIFO
256 x 9, 512 x 9 and 1K x 9 MILITARY AND COMMERCIAL TEMPERATURE RANGES
IN
DATA
FULL FLAG (FF)
RESET (RS)
(D)
WRITE (W)
(HALF–FULL FLAG)
WRITE (W)
DATA IN (D)
FULL FLAG (FF)
RESET (RS)
EXPANSION IN (XI)
Figure 12. Block Diagram of Single 256/512/1024 x 9 FIFO
9918
9
HF
IDT
7200/
7201A/
7202A
(HF)
IDT
7200/
7201A/
7202A
9
9
READ (R)
DATA OUT (Q)
EMPTY FLAG (EF)
RETRANSMIT (RT)
HF
IDT
7200/
7201A/
7202A
9
2679 drw 14
READ (R)
EMPTY FLAG (EF)
RETRANSMIT (RT)
XI XI
18
DATA
Figure 13. Block Diagram of 256/512/1024 x 18 FIFO Memory Used in Width Expansion Mode
OUT
(Q)
2679 drw 15
TABLE I—RESET AND RETRANSMIT
Single Device Configuration/Width Expansion Mode
Inputs Internal Status Outputs
Mode
Reset 0 X 0 Location Zero Location Zero 0 1 1
Retransmit 1 0 0 Location Zero Unchanged X X X
Read/Write 1 1 0 Increment
NOTE: 2679 tbl 09
1. Pointer will increment if flag is High.
RS
RS
RT
RT
XI
XI
Read Pointer Write Pointer
(1)
Increment
(1)
EF
EF
FF
FF
HF
HF
XXX
TABLE II—RESET AND FIRST LOAD TRUTH TABLE
Depth Expansion/Compound Expansion Mode
Inputs Internal Status Outputs
Mode
Reset First Device 0 0 (1) Location Zero Location Zero 0 1
Reset All Other Devices 0 1 (1) Location Zero Location Zero 0 1
Read/Write 1 X (1) X X X X
NOTE: 2679 tbl 10
1.XI is connected to XO of previous device. See Figure 14. RS = Reset Input, FL/RT = First Load/Retransmit, EF = Empty Flag Output, FF = Flag Full Output,
XI
= Expansion Input, HF = Half-Full Flag Output
RS
RS
FL
FL
XI
XI
Read Pointer Write Pointer
EF
EF
FF
FF
5.03 11
IDT7200/7201A/7202A CMOS ASYNCHRONOUS FIFO
256 x 9, 512 x 9 and 1K x 9 MILITARY AND COMMERCIAL TEMPERATURE RANGES
XO
W
FF EF
IDT
R
7200/
D
9
7201A/
99
7202A
FL
Q
V
CC
XI
XO
FULL
RS
FF EF
9
IDT
7200/
7201A/
7202A
FL
XI
XO
FF EF
9
IDT
7200/
7201A/
7202A
FL
XI
Figure 14. Block Diagram of 768 x 9/1536 x 9/3072 x 9 FIFO Memory (Depth Expansion)
Q9–Q17Q0–Q8
•••
Q0–Q8 Q9–Q17
EMPTY
2679 drw 16
Q(N-8) -QN
Q(N-8) -QN
IDT7200/
IDT7201A/
R, W, RS
IDT7202A
DEPTH
EXPANSION
EXPANSION
BLOCK
D0 -D8
D0–DN
D9 -DN
Figure 15. Compound FIFO Expansion
NOTES:
1. For depth expsansion block see section on Depth Expansion and Figure 14.
2. For Flag detection see section on Width Expansion and Figure 13.
5.03 12
IDT7200/
IDT7201A/
IDT7202A
DEPTH
BLOCK
D9 -D17
D18 -DN
•••
•••
IDT7200/
IDT7201A/
IDT7202A
DEPTH
EXPANSION
BLOCK
D(N-8)-DN
D(N-8)-DN
2679 drw 17
IDT7200/7201A/7202A CMOS ASYNCHRONOUS FIFO
256 x 9, 512 x 9 and 1K x 9 MILITARY AND COMMERCIAL TEMPERATURE RANGES
DATA
Q
B 0-8
D
EF
HF
B 0-8
W
FF
R
B
B
B
B
B
2679 drw 18
W
A
FF
A
D
A 0-8
SYSTEM A SYSTEM B
A 0-8
Q
R
A
HF
A
EF
A
Figure 16. Bidirectional FIFO Mode
IN
IDT
7200/
IDT
7201A/
7201A
7202A
IDT
7200/
7201A/
7202A
W
tRPE
R
DATAOUT
W
FF
DATAIN
DATAOUT
EF
tREF
tWEF
tWLZ
tA
DATAOUT VALID
2679 drw 19
Figure 17. Read Data Flow-Through Mode
R
tWPF
t
RFF
t WFF t DH
DATAIN
VALID
t
DS
t
A
DATA
Figure 18. Write Data Flow-Through Mode
OUT
VALID
2679 drw 20
5.03 13
IDT7200/7201A/7202A CMOS ASYNCHRONOUS FIFO
256 x 9, 512 x 9 and 1K x 9 MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDT XXXX
XXX
X
X
Device Type
Power
Speed
PackageXProcess/
Temperature
Range
Blank
B
P
TP
D
TD
J
SO
L
XE
12
15
Commercial (0°C to + 70°C)
Military (–55°C to + 125°C)
Compliant to MIL-STD-883, Class B
Plastic DIP (7201 & 7202 Only)
Plastic THINDIP
CERDIP (7201 & 7202 Only)
Ceramic THINDIP
Plastic Leaded Chip Carrier
SOIC
Leadless Chip Carrier (7201 & 7202 Only)
CERPACK (7201 & 7202 Only)
Commerical Only
Commercial Only
20
25
30
35
40
Commercial Only
Military Only
Commercial Only
Military Only
50
65
80
120
Military only--
except XE
package
Access Time (tA)
Speed in Nanoseconds
* "A" to be included for 7201 and 7202 ordering part number.
LA Low Power*
7200
7201
7202
256 x 9-Bit FIFO
512 x 9-Bit FIFO
1024 x 9-Bit FIFO
2679 drw 21
5.03 14
Loading...