Datasheet IDT71V67603, IDT71V67803 Datasheet (IDT)

256K X 36, 512K X 18

A0-A18Address Inputs

Input

Synchronous

Chip Enable

Input

Synchronous

CS0,

1

Chip Selec ts

Input

Synchronous

Output Enable

Input

Asynchronous

Global Write Enable

Input

Synchronous

Byte Write Enable

Input

Synchronous

1

,

2

,

3

,

4

(1)

Individual Byte Write Selects

Input

Synchronous

CLK

Clock

Input

N/A

Burst Address Advance

Input

Synchronous

Add res s S tatus (Cache Controlle r)

Input

Synchronous

Address Status (Processor)

Input

Synchronous

Li ne ar / Inte rl e av e d Bu rs t Ord e r

Input

DCZZSleep Mode

Input

Asynchronous

I/O0-I/O31, I/OP1-I/OP4Data In p u t / Output

I/O

Synchronous

VDD, V

DD Q

Co re Po we r, I/ O P o we r

Su ppl y

N/A

VSSGround

Su ppl y

N/A

3.3V Synchronous SRAMs

3.3V I/O, Burst Counter
Pipelined Outputs, Single Cycle Deselect

IDT71V67603
IDT71V67803

Features

◆◆

◆

◆◆

256K x 36, 512K x 18 memory configurations

◆◆

◆

◆◆

Supports high system speed:

– 166MHz 3.5ns clock access time
– 150MHz 3.8ns clock access time
– 133MHz 4.2ns clock access time

◆◆

◆

◆◆

LBOLBO

LBO input selects interleaved or linear burst mode

LBOLBO

◆◆

◆

◆◆

Self-timed write cycle with global write control (
write enable (

◆◆

◆

◆◆

3.3V core power supply

◆◆

◆

◆◆

Power down controlled by ZZ input

◆◆

◆

◆◆

3.3V I/O supply (VDDQ)

◆◆

◆

◆◆

Packaged in a JEDEC Standard 100-pin thin plastic quad

BWEBWE

BWE), and byte writes (

BWEBWE

BWBW

BWx)

BWBW

GWGW

GW), byte

GWGW

flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch
ball grid array (fBGA).

Description

The IDT71V67603/7803 are high-speed SRAMs organized as

Pin Description Summary

CE

CS

256K x 36/512K x 18. The IDT71V67603/7803 SRAMs contain write,
data, address and control registers. Internal logic allows the SRAM to
generate a self-timed write based upon a decision which can be left until
the end of the write cycle.

The burst mode feature offers the highest level of performance to the
system designer, as the IDT71V67603/7803 can provide four cycles of
data for a single address presented to the SRAM. An internal burst address
counter accepts the first cycle address from the processor, initiating the
access sequence. The first cycle of output data will be pipelined for one
cycle before it is available on the next rising clock edge. If burst mode
operation is selected (ADV=LOW), the subsequent three cycles of output
data will be available to the user on the next three rising clock edges. The
order of these three addresses are defined by the internal burst counter
and the LBO input pin.

The IDT71V67603/7803 SRAMs utilize IDT’s latest high-performance
CMOS process and are packaged in a JEDEC standard 14mm x 20mm 100­pin thin plastic quad flatpack (TQFP), a 119 ball grid array (BGA) and a 165
fine pitch ball grid array (fBGA).

OE

GW

BWE

BW

BW

BW

BW

ADV

ADSC

ADSP

LBO

NOTE:

1. BW3 and BW4 are not applicable for the IDT71V67802.

5310 tbl 01

©2004 Integrated Device Technology, Inc.

SEPTEMBER 2004

1

DSC-5310/06

IDT71V67603, IDT71V67803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with

Symbol

Pin Function

I/O

Acti ve

Description

18

1

4

1

4

1

0-7

2

8-15

1

0

1

1

1

31

P4

DD

DDQ

SS

3.3V I/O, Pipelined Outputs, Single Cycle Deselect Commercial and Industrial Temperature Ranges

Pin Definitions

(1)

A0-A

ADSC

ADSP

ADV

Address Inputs I N/A Synchronous Address inputs. The address register is triggered by a combination of the

Address Status

(Cache Contro lle r)

Address Status

(Process or)

Burst Address

Advance

rising edge of CLK and

ADSC

Low o r

I LOW Synchronous Address Status from Cache Controller.

used to load the address registers with new addresses.

I LOW Synchronous Address Status from Processor.

load the address registers with new addresses.

I LOW Synchronous Address Advance.

ADV

internal burst counter, controlling burst access after the initial address is loaded. When the

Low and CE Low.

ADSP

is an active LOW input that is

ADSC

is an ac tiv e LO W inp u t that is us e d to

ADSP

is gated by CE.

ADSP

is an ac tiv e LO W inp u t that is us e d to ad v anc e the

input is HIGH the burst counter is not incremented; that is, there is no address advance.

BW

BWE

-

CE

BW

Byte Write Enable I LOW Synchronous byte write enable gates the byte write inputs

rising edge of CLK then

x inputs are passed to the next stage in the circuit. If

BW

HIGH then the byte write inputs are blocked and only

Individual Byte
Write Enables

Chip Enable I LOW Synchronous chip e nable. CE is us e d wi th CS0 and

I LOW Synchronous byte write enables.

Any active byte write causes all outputs to be disabled.

also g ates

CE

ADSP

.

controls I/O

BW

, I/OP1,

CS

-

. If

BW

BW

c an initiate a write cycle.

GW

controls I/O

BW

is LOW at the

BWE

, I/OP2, etc.

to e nable the IDT71V 67603/7803.

CLK Clock I N/A This is the clock input. All timing references for the device are made with respect to this

input.

CS

CS

GW

I/O0-I/O

I/OP1-I/O

Chip Select 0 I HIGH Synchrono us active HIGH chip select. CS0 is used with CE and
Chip Select 1 I LOW Synchronous active LOW chip select.

Global Write

Enab le

I LOW Synchronous global write enable. This input will write all four 9-bit data bytes when LOW

on the rising edge of CLK.

supersedes individual byte write enables.

GW

is used with CE and CS0 to e nab le th e ch ip .

CS

Data Input/Output I/O N/A Synchro nous data input/output (I/O) pins. Both the data input path and data output path are

registered and triggered by the rising edge of CLK.

to e nab le th e ch ip .

CS

BWE

is

LBO

Linear Burst Order I LOW Asynchronous burst order selection input. When

sequence is selected. When

is LOW the Linear burst sequence is selected.

LBO

is HIGH, the interleaved burst

LBO

static input and must not change state while the device is operating.

OE

Output Enabl e I LOW Asynchro nous o utput enab le . When OE is LOW the data output drivers are enabled on the

I/O pins if the chip is also selected. When

is HIGH the I/O pins are in a high-

OE

impe d ance s tate.

V

V

V

Power Supply N/A N/A 3.3V core power supply.
Power Supply N/A N/A 3.3V I/O Supply.

Ground N/A N/A Ground.

NC No Connect N/A N/A NC pins are not electrically connected to the device.

ZZ Sleep Mode I HIGH Asynchro nous sleep mode input. ZZ HIGH will gate the CLK internally and power down the

IDT71V67603/7803 to its lo wes t po we r consu mp tio n lev el. Data retention i s g uaranteed in
Sleep Mode.

NOTE:

1. All synchronous inputs must meet specified setup and hold times with respect to CLK.

LBO

5310 tbl 02

is a

6.42

2

IDT71V67603, IDT71V67803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with

3.3V I/O, Pipelined Outputs, Single Cycle Deselect Commercial and Industrial Temperature Ranges

Functional Block Diagram

LBO

ADV

CLK

ADSC

AD SP

CEN

CLR

Binary

Counter

Burst

Sequence

2

Burst

Logic

Q0
Q1

A0*
A1*

INTERNAL
ADDRESS

18/19

256K x 36/

512K x18-

BIT

MEMORY

ARRAY

A0–A

17/18

BW E

BW

BW

BW

BW

I/O0–I/O

I/OP1–I/O

GW

CE

CS

CS

ZZ

OE

CLK EN

ADDRESS

REGISTER

Byte 1

Write Register

1

Byte 2

Write Register

2

3

4

0

1

Powerdown

31
P4

36/18

Byte 3

Write Register

Byte 4

Write Register

D

Enable
Register

CLK EN

DQ

Enable
Delay
Register

18/19

Q

2

A0,A

1

A

2–A18

9

9

9

9

DATA INPUT

REGISTER

Byte 1
Write Driver

Byte 2
Write Driver

Byte 3
Write Driver

Byte 4
Write Driver

36/18

OE

OUTPUT

REGISTER

OUTPUT
BUFFER

36/18

,

5301 drw01

6.42

3

IDT71V67603, IDT71V67803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with

Symbol

Rati ng

Commercial

Uni t

TERM

TERM

DD

TERM

TERM

DDQ

A

BIAS

STG

T

OUT

Grade

Temperature

(1)

VSSVDDV

DDQ

Symbol

Parameter

Min.

Typ.

Max.

Uni t

DD

DDQ

SS

IH

DD

IH

DDQ

IL

Symbol

Parameter

(1)

Conditions

Max.

Unit

CINInp ut Cap ac itanc e

VIN = 3dV

5pFC

I/O

I/O Cap acitanc e

V

OUT

= 3dV

7

pF

5310 tbl 07

Symbol

Par a me t e r

(1)

Conditions

Max .

Unit

CINInput Cap aci tance

VIN = 3dV

7pFC

I/O

I/O Cap aci tance

V

OUT

= 3dV

7

pF

5310 tbl 07 a

Symbol

Parameter

(1)

Conditions

Max.

Uni t

CINInp ut Capa ci tanc e

VIN = 3dV

7pFC

I/O

I/O Cap aci tance

V

OUT

= 3dV

7

pF

5310 tbl 07b

3.3V I/O, Pipelined Outputs, Single Cycle Deselect Commercial and Industrial Temperature Ranges

Absolute Maximum Ratings

(1)

Recommended Operating

Temperature and Supply Voltage

(2)

V

(3,6)

V

(4,6)

V

(5,6)

V

(7)

T

T

T

P
I

NOTES:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.

2. VDD terminals only.

3. VDDQ terminals only.

4. Input terminals only.

5. I/O terminals only.

6. This is a steady-state DC parameter that applies after the power supplies have
ramped up. Power supply sequencing is not necessary; however, the voltage
on any input or I/O pin cannot exceed VDDQ during power supply ramp up.

7. TA is the "instant on" case temperature.

Terminal Voltage with

-0.5 to +4.6 V

Re sp e c t to GND
Terminal Voltage with

-0.5 to V

V

Re sp e c t to GND
Terminal Voltage with

-0.5 to VDD +0.5 V

Re sp e c t to GND
Terminal Voltage with

-0.5 to V

+0.5 V

Re sp e c t to GND

Operating Temperature

Temperatur e

-0 to + 70

-55 to +125

o

o

Under Bias
Storage

-55 to +125

o

Temperatur e
Power Dis sipation 2.0 W
DC Outp ut Cu rre nt 50 mA

5310 tbl 03

Comm erc ial 0°C to +70° C 0V 3.3V± 5% 3.3V± 5%

Industrial -40° C to + 85°C 0V 3.3V± 5% 3.3V ± 5%

NOTE:

1. TA is the "instant on" case temperature.

Recommended DC Operating

Conditions

C

V

Core S upp l y Vol tage 3.135 3.3 3.465 V

C

C

V

I/O Supp ly Vol tage 3.135 3.3 3.465 V

V

Supply Voltage 0 0 0 V

V

Input High Voltage - Inputs 2.0

V

I n put High Vol tage - I/O 2.0

V

Input Low Voltag e -0.3

NOTE:

1. VIL (min) = -1.0V for pulse width less than tCYC/2, once per cycle.

(1)

____

____

____

V

+0.3 V

V

+0.3 V

0.8 V

5310 tbl 04

5310 tbl 05

100 Pin TQFP Capacitance

(TA = +25°C, f = 1.0MHz)

165 fBGA Capacitance

(TA = +25°C, f = 1.0MHz)

119 BGA Capacitance

(TA = +25°C, f = 1.0MHz)

NOTE:

1. This parameter is guaranteed by device characterization, but not production tested.

6.42

4

IDT71V67603, IDT71V67803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with

3.3V I/O, Pipelined Outputs, Single Cycle Deselect Commercial and Industrial Temperature Ranges

Pin Configuration  256K x 36, 100-Pin TQFP

C

4

3

2

0

7

A6A

10099989796959493929190 8786858483828189 88

W

S

E

B

C

C

1

1

D

S

LK

D

W

W

W

B

B

B

S

S
C

C

V

V

E

W

W
B

G

P

S

V

S

D

E

A

O

8A9

D

D

A

A

A

I/O

I/O
I/O

V

DDQ

V
I/O
I/O
I/O
I/O

V

V

DDQ

I/O
I/O

VDD/NC

V

V
I/O
I/O

V

DDQ

V
I/O
I/O
I/O
I/O

V

V

DDQ

I/O
I/O

I/O

SS

SS

DD

NC

SS

SS

SS

1

P3

2

16

3

17

4
5
6

18

7

19

8

20

9

21

10
11
12

22

13

23

(1)

14
15
16
17
18

24

19

25

20
21
22

26

23

27

24

28

25

29

26
27
28

30

29

31

30

P4

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

O
LB

5

A0A1A2A3A4A

S

D

C

C

N

N

C

S

V

17

D

N

A

V

80

I/O

I/O

I/O
V
V
I/O
I/O
I/O
I/O
V
V
I/O
I/O
V

NC
V

ZZ
I/O
I/O
V
V
I/O
I/O
I/O
I/O
V
V
I/O
I/O

I/O

5301 drw 02

15

DDQ

SS

SS
DDQ

SS

DD

DDQ
SS

SS
DDQ

P2

14

13
12
11
10

9
8

(2)

7
6

5
4
3
2

1

,

0
P1

79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

14A13A12A11A10

16

A

A15A

Top View

NOTES:

1. Pin 14 can either be directly connected to VDD, or connected to an input voltage ≥ VIH, or left unconnected.

2. Pin 64 can be left unconnected and the device will always remain in active mode.

6.42

5

IDT71V67603, IDT71V67803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with

3.3V I/O, Pipelined Outputs, Single Cycle Deselect Commercial and Industrial Temperature Ranges

Pin Configuration  512K x 18, 100-Pin TQFP

C

2

0

7

A6A

100 99 98 97 96 95 94 93 92 91 90 87 86 85 84 83 82 8189 88

C

S

E

N

C

C

1

1

D

S

C

W

W

S

N

B

B

C

LK

D

S

C

V

V

E

W

W
B

G

P

S

V

S

E

D
A

O

8A9

D

D

A

A

A

V

DDQ

V

I/O
I/O
V

V

DDQ

I/O
I/O

VDD/NC

V

V
I/O
I/O

V

DDQ

V
I/O
I/O
I/O

V

V

DDQ

NC
NC
NC

NC
NC

NC

NC

NC
NC
NC

DD

1
2
3
4
5

SS

6
7
8

8

9

9

10

SS

11
12

10

13

11

(1)

14
15
16
17

SS

18

12

19

13

20
21

SS

22

14

23

15

24

P2

25
26

SS

27
28
29
30

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

O
LB

5

A0A1A2A3A4A

S

D

C

C
N

C

S

N

V

18

D

N

A

V

80

A

10

79

NC

78

NC

77

V

DDQ

76

V

SS

75

NC

74

I/O
I/O
I/O

V

V
I/O
I/O

V
NC

V

ZZ

I/O

I/O
V
V
I/O
I/O
NC
NC

V

V

NC

NC

NC

5310 drw 03

SS
DDQ

SS

DD

DDQ
SS

SS
DDQ

P1
7
6

5
4

(2)

3
2

1
0

,

73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

15A14A13A12A11

17

A

A16A

Top View

NOTES:

1. Pin 14 can either be directly connected to VDD, or connected to an input voltage ≥ VIH, or left unconnected.

2. Pin 64 can be left unconnected and the device will always remain in active mode.

6.42

6

IDT71V67603, IDT71V67803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with

3.3V I/O, Pipelined Outputs, Single Cycle Deselect Commercial and Industrial Temperature Ranges

Pin Configuration  256K x 36, 119 BGA

1234567

DDQ

A V
B NC CS

NC

C

16

I/O

D

17

I/O

E

DDQ

F V

20

I/O

G

22

H I/O

DDQ

V

J

24

K I/O

25

I/O

L

DDQ

M V

29

I/O

N

31

P I/O

NC A

R

T NC NC A

DDQ

U V

A

A
I/O
I/O
I/O
I/O
I/O

V
I/O
I/O
I/O
I/O
I/O

DNU

6

(4)

0

7

P3

18

19

21

23

DD

26

27

28

30

P4

5

(3)

4

A

3

A

2

A

SS

V

SS

V

SS

V

3

BW

SS

V

NC V

SS

V

4

BW

SS

V

SS

V

SS

V
LBO

10

(3)

DNU

ADSP
ADSC

DD

V
NC V

CE
OE

ADV BW

GW

DD

CLK V

NC

BWE

1

A

0

A

DD

V

VDD/NC

11

A

(3)

DNU

DNU

8

A

9

A

12

A

SS

SS

V

SS

V

2

SS

V
NC V

SS

1

BW

SS

V

SS

V

SS

V

(1)

14

A

(3)

16

A
A

17

15

A

P2

I/O

13

I/O

12

I/O

11

I/O

9

I/O

DD

6

I/O

4

I/O

3

I/O

2

I/O

P1

I/O

13

A
NC ZZ

(3)

DNU

DDQ

V

NC
NC

15

I/O

14

I/O

DDQ

V

10

I/O

8

I/O

DDQ

V

7

I/O

5

I/O

DDQ

V

1

I/O

0

I/O

NC

(2)

DDQ

V

5310 drw 04

,

Top View

Pin Configuration  512K x 18, 119 BGA

1234567

DDQ

V

A
B NC CS

C A

NC

8

D I/O

NC I/O

E

DDQ

V

F

G NC I/O

11

I/O

H

DDQ

V

J

NC I/O

K

13

L I/O

DDQ

M V

15

N I/O

P NC I/O
R NC A

T NC A

DDQ

V

U

6

A

(4)

0

7

NC V

9

NC V

10

NC V

DD

V

12

NC NC

14

I/O

NC V

P2

5

10

(3)

DNU

A
A
A

SS

SS

V

SS

BW

SS

NC

SS

V

SS

V

SS

V

SS

SS

V

LBO

A

DNU

4

3

2

2

15

(3)

ADSP

ADSC

DD

V

NC V

CE
OE

ADV

GW

DD

V

CLK V

BWE

1

A

0

A

DD

V

NC A

(3)

DNU

V

8

A

9

A

13

A

SS

SS

V

SS

V

SS

V

SS

V

NC V

SS

1

BW

SS

V

SS

V

SS

V

/NC NC

DD

14

DNU

(1)

(3)

16

A
A

18

17

A

P1

I/O

NC I/O

6

I/O

NC I/O

4

I/O

DD

NC I/O

2

I/O

NC V

1

I/O

NC I/O

12

A

11

A

(3)

DNU

DDQ

V

NC
NC
NC

7

DDQ

V

5

NC

DDQ

V

3

NC

DDQ

NC

0

(2)

ZZ

DDQ

V

5310 drw 05

,

Top View

NOTES:

1. R5 can either be directly connected to VDD, or connected to an input voltage ≥ VIH, or left unconnected.

2. T7 can be left unconnected and the device will always remain in active mode.

3. DNU= Do not use; these signals can either be left unconnected or tied to Vss.

4. On future 18M device CS0 will be removed, B2 will be used for address expansion.

6.42

7

IDT71V67603, IDT71V67803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with

7

3BW2CS1

8

6CS0BW4BW1

9

DDQVSSVSSVSSVSSVSSVDDQ

P2

16VDDQVDDVSSVSSVSSVDDVDDQ

15

14

18VDDQVDDVSSVSSVSSVDDVDDQ

13

12

20VDDQVDDVSSVSSVSSVDDVDDQ

11

10

22VDDQVDDVSSVSSVSSVDDVDDQ

9

8

DD

DDVSSVSSVSSVDD

24VDDQVDDVSSVSSVSSVDDVDDQ

7

6

26VDDQVDDVSSVSSVSSVDDVDDQ

5

4

28VDDQVDDVSSVSSVSSVDDVDDQ

3

30VDDQVDDVSSVSSVSSVDDVDDQ

1

0

DDQVSS

SSVDDQ

P1

5A2

1

10A13A14A17

4A3

0

11A12A15A16

5310 tbl 17a

3.3V I/O, Pipelined Outputs, Single Cycle Deselect Commercial and Industrial Temperature Ranges

Pin Configuration  256K x 36, 165 fBGA

1234567891011

LBO

(3)

A

(1)

NC NC V

(3)

(3)

NC

CE BW

A
A

NC NC

(4)

DNU

(4)

DNU

CLK

A
A

BWE ADSC ADV

GW OE ADSP

(3)

NC V

(4)

DNU

(4)

DNU

NC

NC

(3)

A
A

NC I/O
I/O
I/O
I/O

I/O

NC NC ZZ

I/O
I/O
I/O
I/O

I/O
I/O
I/O

I/O

I/O
I/O
I/O
I/O

(2)

2

NC I/O

A

A

ANC
BNC A
CI/OP3NC V
DI/O17I/O
EI/O19I/O

FI/O21I/O
GI/O23I/O
HV

JI/O25I/O
KI/O27I/O

LI/O29I/O
MI/O31I/O
NI/OP4NC V
PNCNC
R

Pin Configuration  512K x 18, 165 fBGA

1234567891011

DD

LBO

(3)

(1)

13

15

A

7

CE BW

0
DDQ
DDQ
DDQ
DDQ
DDQ

NC NC V

DDQ

NC V

NC V

(3)

(3)

NC

DDQ
DDQ
DDQ
DDQ

A
A

5
4

NC

2

NC

V

SS

V

DD

V

DD

V

DD

V

DD
DD

V

DD

V

DD

V

DD

V

DD

V

SS

A

2

A

3

BW

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

NC NC
DNU
DNU

CS

1

CLK

1

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

(3)

(4)

A

1

(4)

A

0

ANC

BNC A6CS
CNC NCV
DNC I/O8V
ENC I/O9V
FNCI/O10V

GNC I/O11V

HV
JI/O12NC V
KI/O
LI/O14NC V

MI/O

NI/OP2NC V
PNC NC

R

BWE ADSC AD V

GW OE ADSP

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

NC V
DNU
DNU

V

SS

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD
SS

(4)

A

(4)

A

12

V
V
V
V
V

V
V
V
V
V

11

A
A

A

8

DDQ
DDQ
DDQ
DDQ
DDQ

A
NC I/O
NC I/O
NC I/O
NC I/O
NC I/O

NC

9

NC NC ZZ

DDQ
DDQ
DDQ
DDQ
DDQ

14
13

I/O

3

I/O

2

I/O

1

I/O

0

NC NC

A

15

A

16

5310 tb l 17b

A

A
A

10

(3)

P1

7

6

5
4

(2)

NC
NC
NC
NC

18
17

NOTES:

1. H1 can either be directly connected to VDD, or connected to an input voltage ≥ VIH, or left unconnected.

2. H11 can be left unconnected and the device will always remain in active mode.

3. Pin N6, B11, A1, R2 and P2 are reserved for 18M, 36M, 72M, and 144M and 288M respectively.

4. DNU= Do not use; these signals can either be left unconnected or tied to Vss.

6.42

8

IDT71V67603, IDT71V67803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with

Symbol

Parameter

Test Conditions

Min.

Max.

Uni t

L

I

DD

LZZ

DD

OUT

DDQ

OL

OH

5310 tbl 08

(2)

(2,3)

(2,3)

3.3V I/O, Pipelined Outputs, Single Cycle Deselect Commercial and Industrial Temperature Ranges

DC Electrical Characteristics Over the Operating

Temperature and Supply Voltage Range

(VDD = 3.3V ± 5%)

|I

| Input Leak age Current VDD = Max., VIN = 0V to V

|I

ZZ and

|

Input Leakag e Current

LBO

|ILO| Output Leakage Current V
V
V

NOTE:

1. The LBO pin will be internally pulled to VDD if it is not actively driven in the application and the ZZ pin will be internally pulled to VSS if not actively driven.

Output Low Voltage IOL = +8mA, VDD = Min.
Outp ut Hig h Vol tag e IOH = -8mA, VDD = Min. 2.4

(1)

VDD = Max., VIN = 0V to V

= 0V to V

, De v i ce De s e l e c te d

___

___

___

___

5µA

30 µA

5µA

0.4 V

___

DC Electrical Characteristics Over the Operating

MAX

MAX

(1)

166MHz 150MHz 133MHz Uni t

Com' l o nly Co m'l In d Com'l Ind

340 305 325 260 280

50 50 70 50 70

160 155 175 150 170

50 50 70 50 70

Temperature and Supply Voltage Range

Symbo l Parameter Test Conditions

Ope rating Po wer Supply

I

DD

Current

I

CMOS Stand by Power

SB1

Supply Curre nt

I

Clock Running Power

SB2

Supply Curre nt
Full Sleep Mode Supply

I

ZZ

Current

NOTES:

1. All values are maximum guaranteed values.

2. At f = fMAX, inputs are cycling at the maximum frequency of read cycles of 1/tCYC while ADSC = LOW; f=0 means no input lines are changing.

3. For I/Os VHD = VDDQ - 0.2V, VLD = 0.2V. For other inputs VHD = VDD - 0.2V, VLD = 0.2V.

Device Se lec ted , Outputs Ope n, VDD = Max.,

V

= Max., VIN > VIH or < VIL, f = f

DDQ

Device Deselected, Outputs Open, VDD = Max.,

V

= Max., VIN > VHD or < VLD, f = 0

DDQ

Device Deselected, Outputs Open, VDD = Max.,

V

= Max., VIN > VHD or < VLD, f = f

DDQ

ZZ >

V

HD, VDD

= Max.

V

mA

mA

mA

mA

5310 t bl 0 9

(VDDQ = 3.3V)

Inp ut Pu ls e Le v e l s
Inp ut Ris e / F all Time s
Inp ut Timi ng Re fe re nc e L e ve l s
Output Timing Refe renc e Le v e ls

AC Te st Lo ad

0 to 3V

2ns

1.5V

1.5V

See Figure 1

5310 tbl 10

6.42

9

AC Test LoadAC Test Conditions

CD

∆t

(Typical, ns)

Figure 2. Lumped Capacitive Load, Typical Derating

V

50Ω

I/O

6
5
4
3
2
1

20 30 50 100 200

0

=50Ω

Z

Figure 1. AC Test Load

80

Capacitance (pF)

DDQ

5310 drw 06

/2

,

,

5310 drw 07

IDT71V67603, IDT71V67803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with

Operati on

Address

UsedCECS

0CS1

(2)

CLK

I/O

3.3V I/O, Pipelined Outputs, Single Cycle Deselect Commercial and Industrial Temperature Ranges

Synchronous Truth Table

(1,3)

ADSP AD SC ADV G W BWE BWxOE

De se l ec te d Cyc l e, P owe r Do wn No ne H X X X L X X X X X - HI-Z
De se l ec te d Cyc l e, P owe r Do wn No ne L X H L X X X X X X - HI -Z
De se l ec te d Cyc l e, P owe r Do wn No ne L L X L X X X X X X - HI-Z
De se l ec te d Cyc l e, P owe r Do wn No ne L X H X L X X X X X - HI-Z
De se l ec te d Cyc l e, P owe r Do wn No ne L L X X L X X X X X - HI-Z
Read Cycle, Begin Burst External L H L L X X X X X L - D
Read Cycle, Begin Burst External L H L L X X X X X H - HI-Z
Read Cycle, Begin Burst External L H L H L X H H X L - D
Read Cycle, Begin Burst External L H L H L X H L H L - D
Read Cycle, Begin Burst External L H L H L X H L H H - HI-Z

Write Cycle, Begin Burst External L H L H L X H L L X - D

Write Cycle, Begin Burst External L H L H L X L X X X - D
Read Cyc le, Continue Burs t Ne xt X X X H H L H H X L - D
Re ad Cyc le , Co ntin ue Bur st Nex t X X X H H L H H X H - HI-Z
Read Cyc le, Continue Burs t Ne xt X X X H H L H X H L - D
Re ad Cyc le , Co ntin ue Bur st Nex t X X X H H L H X H H - HI-Z
Read Cyc le, Continue Burs t Ne xt H X X X H L H H X L - D
Re ad Cyc le , Co ntin ue Bur st Nex t H X X X H L H H X H - HI-Z
Read Cyc le, Continue Burs t Ne xt H X X X H L H X H L - D
Re ad Cyc le , Co ntin ue Bur st Nex t H X X X H L H X H H - HI-Z

Write Cyc le, Continue Burst Next X X X H H L H L L X - D

Write Cyc le, Continue Burst Next X X X H H L L X X X - D

Write Cyc le, Continue Burst Next H X X X H L H L L X - D

Write Cyc le, Continue Burst Next H X X X H L L X X X - D
Read Cycle, Suspend Burst Curre nt X X X H H H H H X L - D
Read Cycle, Suspend Burst Curre nt X X X H H H H H X H - HI-Z
Read Cycle, Suspend Burst Curre nt X X X H H H H X H L - D
Read Cycle, Suspend Burst Curre nt X X X H H H H X H H - HI-Z
Read Cycle, Suspend Burst Curre nt H X X X H H H H X L - D
Read Cycle, Suspend Burst Curre nt H X X X H H H H X H - HI-Z
Read Cycle, Suspend Burst Curre nt H X X X H H H X H L - D
Read Cycle, Suspend Burst Curre nt H X X X H H H X H H - HI-Z

Write Cycle, Suspend Burst Current X X X H H H H L L X - D

Write Cycle, Suspend Burst Current X X X H H H L X X X - D

Write Cycle, Suspend Burst Current H X X X H H H L L X - D

Write Cycle, Suspend Burst Current H X X X H H L X X X - D

NOTES:

1. L = VIL, H = VIH, X = Don’t Care.

2. OE is an asynchronous input.

3. ZZ = low for this table.

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

5310 tbl 11

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

6.42

10

IDT71V67603, IDT71V67803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with

Operatio n

1BW2BW3BW4

Sequence 1

Sequence 2

Sequence 3

Sequence 4

A1A0A1A0A1A0A1

A0

Sequence 1

Sequence 2

Sequence 3

Sequence 4

A1A0A1A0A1A0A1

A0

Operatio n

(2 )

ZZ

I/O Status

Power

3.3V I/O, Pipelined Outputs, Single Cycle Deselect Commercial and Industrial Temperature Ranges

Synchronous Write Function Truth Table

(1, 2)

GW BWE BW

Read HHXXXX

Read HLHHHH
Write all BytesLXXXXX
Write all BytesHLLLLL

Write B y te 1
Write B y te 2
Write B y te 3
Write B y te 4

NOTES:

1. L = VIL, H = VIH, X = Don’t Care.

2. BW3 and BW4 are not applicable for the IDT71V67803.

3. Multiple bytes may be selected during the same cycle.

Asynchronous Truth Table

(3 )

(3 )

(3 )

(3 )

HLLHHH
HLHLHH
HLHHLH
HLHHHL

53 10 tbl 12

(1)

OE

Rea d L L Data Out Ac tiv e
Rea d H L Hig h-Z Ac tiv e

Write X L High-Z – Data In Activ e

Deselected X L High-Z Standby

Sleep Mode X H High-Z Sleep

NOTES:

1. L = VIL, H = VIH, X = Don’t Care.

2. Synchronous function pins must be biased appropriately to satisfy operation requirements.

53 10 tbl 13

Interleaved Burst Sequence Table (LBO=VDD)

First Address 0 0 0 1 1 0 1 1
Second Address 0 1 0 0 1 1 1 0

Third Address 1 0 1 1 0 0 0 1

Fourth Address

NOTE:

1. Upon completion of the Burst sequence the counter wraps around to its initial state.

(1)

11100100

Linear Burst Sequence Table (LBO=VSS)

First Address 0 0 0 1 1 0 1 1
Second Address 0 1 1 0 1 1 0 0

Third Address 1 0 1 1 0 0 0 1

Fourth Address

NOTE:

1. Upon completion of the Burst sequence the counter wraps around to its initial state.

(1)

11000110

53 10 tbl 14

53 10 tbl 15

6.42

11

IDT71V67603, IDT71V67803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with

166MHz

150MHz

133MHz

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Uni t

CYC

CH

CL

Output Parameters

CD

CDC

CLZ

CHZ

OE

OLZ

OHZ

Set Up Times

SA

SS

SD

SW

SAV

SC

Hold Times

HA

HS

HD

HW

HAV

HC

S lee p Mo de and Configur ation Par am e ter s

ZZPW

ZZR

CFG

3.3V I/O, Pipelined Outputs, Single Cycle Deselect Commercial and Industrial Temperature Ranges

AC Electrical Characteristics

(VDD = 3.3V ±5%, Commercial and Industrial Temperature Ranges)

t

(1)

t

(1)

t

t
t

(2)

t

(2)

t
t

(2)

t

(2)

t

t
t
t
t
t
t

Clock Cycle Time 6
Clock High Pulse Width 2.4
Clock Low Pulse Width 2.4

Clo c k High to Val i d Data

____

Cloc k Hig h to Data Change 1.5
Clo c k High to O utp ut A c tiv e 0

Clo c k High to Da ta Hi g h-Z 1. 5 3. 5 1 .5 3.8 1.5 4. 2 ns
Output Enabl e A cc e ss Time

____

Output Enabl e Lo w to O utput Activ e 0
Output Enabl e Hig h to Output High-Z

____

Addre ss Setup Time 1.5
Address Status Setup Time 1.5
Data In S e tup Tim e 1. 5
Write Setup Time 1.5
Address Advance Setup Time 1.5
Chip Enable/Select Setup Time 1.5

____

____

____

3.5

____

____

3.5

____

3.5

____

____

____

____

____

____

6.7

2.6

2.6

____

1.5
0

____

0

____

1.5

1.5

1.5

1.5

1.5

1.5

____

____

____

3.8

____

____

3.8

____

3.8

____

____

____

____

____

____

7.5

____

1.5

____

____

1.5

1.5

1.5

1.5

1.5

1.5

____

3
3

____

____

ns
ns
ns

4.2 ns

____

0

____

ns
ns

4.2 ns

0

____

ns

4.2 ns

____

____

____

____

____

____

ns
ns
ns
ns
ns
ns

t
t
t
t
t
t

t

(3)

t

(4)

t

Address Hold Time 0.5
Ad dre ss S tatus Hold Time 0. 5
Data In Ho l d Tim e 0. 5
Write Hold Time 0.5
Addre ss Advance Hold Time 0.5
Chip Enab le/Se lect Hold Time 0.5

ZZ Pu l s e W i d th 10 0
ZZ Re c ov e r y Ti me 10 0
Config uration Se t-up Time 24

____

____

____

____

____

____

____

____

____

0.5

0.5

0.5

0.5

0.5

0.5

100
100

27

____

____

____

____

____

____

____

____

____

0.5

0.5

0.5

0.5

0.5

0.5

100
100

30

____

____

____

____

____

____

____

____

____

NOTES:

1. Measured as HIGH above VIH and LOW below VIL.

2. Transition is measured ±200mV from steady-state.

3. Device must be deselected when powered-up from sleep mode.

4. tCFG is the minimum time required to configure the device based on the LBO input. LBO is a static input and must not change during normal operation.

6.42

12

ns
ns
ns
ns
ns
ns

ns
ns
ns

5310 tbl 16

IDT71V67603, IDT71V67803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with

3.3V I/O, Pipelined Outputs, Single Cycle Deselect Commercial and Industrial Temperature Ranges

suspends
H
IG

H

V
D
A

(1,2)

08
drw

5310

,

y)
2(A

O

Z
H
C

t

y)
1(A

O

around

y)

initial state)

raps

4(A

its

O

to

urst w
(B

ead

burst

y)
3(A

O

R

Timing Waveform of Pipelined Read Cycle

ipelined

urst P

ipelined
P

utput
O

B

ead
R

isabled
D

y)
2(A

W
H

t

V
A
H

t

V
A
S

L
C

t

C
Y
C

t

H
C

t

S
H

t

S
S

t

(1)

A
S

t

W
S

t

y
A

A
H

t

x
A

C
H

t

C
S

t

t

D
C

t

E
O

t

O

C
D

y)

C

t

1(A
O

LZ
C

t

Z
H
O

t

x)
1(A

O

LZ
O

t

0 timing transitions are identical but inverted to the CE and CS1 signals. For example, when CE and CS1 are LOW on this waveform, CS0 is HIGH.

LK
C

C

P

S

S

D

D

A

A

S
S
E
R
D
D
A

x
,BW

E
,BW

W

1

S
,C

E
C

V

3)

D
A

ote
(N

E
O

T
U
O

TA
A
D

the burst sequence of the base address Ay, etc. where A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input.

NOTES:

1. O1 (Ax) represents the first output from the external address Ax. O1 (Ay) represents the first output from the external address Ay; O2 (Ay) represents the next output data in

2. ZZ input is LOW and LBO is Don't Care for this cycle.

3. CS

6.42

13

IDT71V67603, IDT71V67803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with

3.3V I/O, Pipelined Outputs, Single Cycle Deselect Commercial and Industrial Temperature Ranges

Timing Waveform of Combined Pipelined Read and Write Cycles

09

z)
3(A

O

drw
5310

,

(1,2,3)

z)
2(A

O

C
D

z)

z)

C

t

1(A

1(A
O

O

LZ
O

t

z
A

W
H

t

L
C

t

C
Y
C

t

W
S

y

t

H
C

t

A

D
H

t

D
S

t

y)
I1(A

Z

x)

H
O

t

1(A
O

ead

urst R
B

ipelined
P

D
C

t

rite
W

ipelined
P

LK
C

E
O

t

D

LZ

C

t

C

t

x

(2)

S
H

t

S
S

t

P
S
D
A

A

A

A

H

t

S

t

S
S
E
R
D
D
A

W
G

V
D
A

E
O

6.42

14

IN

AT A
D

T
U
O

TA
A
D

ead
R

ingle
S

Az; O2 (Az) represents the next output data in the burst sequence of the base address Az, etc. where A0 and A1 are advancing for the four word burst in the sequence defined by the state

NOTES:

1. Device is selected through entire cycle; CE and CS1 are LOW, CS0 is HIGH.

of the LBO input.

2. ZZ input is LOW and LBO is Don't Care for this cycle.

3. O1 (Ax) represents the first output from the external address Ax. I1 (Ay) represents the first input from the external address Ay; O1 (Az) represents the first output from the external address

IDT71V67603, IDT71V67803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with

3.3V I/O, Pipelined Outputs, Single Cycle Deselect Commercial and Industrial Temperature Ranges

Timing Waveform of Write Cycle No. 1  GW Controlled

z)
I3(A

(1,2,3)

10
drw

5310

rite

,

z)

D

I2(A

tH

W
H

t

W
S

t

z
A

V
A
H

t

z)
I1(A

y)

D
S

t

I4(A

y)

urst W
B

I3(A

y)

e
edg

rising
clock

next
the

on
pled

sam
is

and
cycle

a

urst)

V
A
S

t

b
ends

susp
H
IG

H

V
D
A

(

I2(A

y)

rite

urst W
B

I2(A

y)
I1(A

L
C

t

C
Y
C

t

H
C

t

LK
C

S
H

t

S
S

t

P
S
D
A

A
H

A

t

S

t

C
S
D
A

initiates

y

P

A

S
D
A

ead

urst R
B

rite

ingle

W

S

0 timing transitions are identical but inverted to the CE and CS1 signals. For example, when CE and CS1 are LOW on this waveform, CS0 is HIGH.

from the external address Ay; I2 (Ay) represents the next input data in the burst sequence of the base address Ay, etc. where A0 and A1 are advancing for the four word burst in the

NOTES:

sequence defined by the state of the LBO input. In the case of input I2 (Ay) this data is valid for two cycles because ADV is high and has suspended the burst.

1. ZZ input is LOW, BWE is HIGH and LBO is Don't Care for this cycle.

2. O4 (Aw) represents the final output data in the burst sequence of the base address Aw. I1 (Ax) represents the first input from the external address Ax. I1 (Ay) represents the first input

3. CS

hen
w

ignored
is

W
G

x
A

C
H

t

C
S

t

S
S
E
R
D
D

W
G

1

S
,C

E
C

3)
ote

(N

V
D
A

6.42

15

E
O

x)
I1(A

IN

TA

A
D

Z
H
O

t

)
w

4(A
O

)
w

3(A
O

T
U
O

TA

A
D

IDT71V67603, IDT71V67803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with

3.3V I/O, Pipelined Outputs, Single Cycle Deselect Commercial and Industrial Temperature Ranges

Timing Waveform of Write Cycle No. 2  Byte Controlled

z)
I3(A

(1,2,3)

11
drw

5310

,

z)

D

I2(A

tH

W
H

t

z
A

W
H

t

W
S

t

W
S

t

V
A
S

t

z)
I1(A

D

y)

y)

S

t

I4(A

I4(A

rite

xtended

urst W

E

B

y)
I3(A

y)
I2(A

edge

rising

next clock
on

pled
sam

is
and

cycle
a

L
C

t

C
Y
C

t

H
C

t

S
H

t

S
S

t

A
S

t

initiates

P

y

S

A

D
A

hen
w

ignored
is

E
W

B

x
A

A
H

t

edge

rising

next clock
on

pled
sam

is
and

cycle
a

initiates

P
S
D
A

hen
w

ignored
is

x

W
B

burst)

y)
I2(A

suspends

V
D
A

(

rite

urst W
B

y)
I1(A

Z
H
O

x)

t

I1(A

C
H

t

C
S

t

rite

ingle

W

S

)
w

4(A
O

)
w

urst

ead

B

R

3(A
O

LK
C

1

P
S
D
A

C
S
D
A

S
S
E
R
D
D

E
W

B

x

S

W
B

,C
E
C

6.42

3)
ote

(N

16

V
D
A

E
O

IN

TA

A
D

T
U
O

ATA
D

from the external address Ay; I2 (Ay) represents the next input data in the burst sequence of the base address Ay, etc. where A0 and A1 are advancing for the four word burst in the

NOTES:

sequence defined by the state of the LBO input. In the case of input I2 (Ay) this data is valid for two cycles because ADV is high and has suspended the burst.

1. ZZ input is LOW, GW is HIGH and LBO is Don't Care for this cycle.

2. O4 (Aw) represents the final output data in the burst sequence of the base address Aw. I1 (Ax) represents the first input from the external address Ax. I1 (Ay) represents the first input

3. CS0 timing transitions are identical but inverted to the CE and CS1 signals. For example, when CE and CS1 are LOW on this waveform, CS0 is HIGH.

IDT71V67603, IDT71V67803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with

3.3V I/O, Pipelined Outputs, Single Cycle Deselect Commercial and Industrial Temperature Ranges

Timing Waveform of Sleep (ZZ) and Power-Down Modes

z
A

ZR
tZ

(1,2,3)

12
drw

5310

,

ode
M

nooze
S

W
P

L
C

t

C
Y
C

t

x)

H
C

t

A
H

t

x
A

S
H

t

S
S

t

A
S

t

C
H

t

C
S

t

E
O

t

1(A
O

LZ
O

t

tZZ

ead
R

ingle
S

LK
C

P
S
D
A

C

S

S

S

D

E

A

R
D
D

W
G

1

S
,C

E
C

6.42

V

4)

D
A

ote
(N

E
O

17

T
U
O

A
T
A
D

Z

Z

NOTES:

1. Device must power up in deselected Mode

2. LBO is Don't Care for this cycle.

3. It is not necessary to retain the state of the input registers throughout the Power-down cycle.

4. CS0 timing transitions are identical but inverted to the CE and CS1 signals. For example, when CE and CS1 are LOW on this waveform, CS0 is HIGH.

IDT71V67603, IDT71V67803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with

3.3V I/O, Pipelined Outputs, Single Cycle Deselect Commercial and Industrial Temperature Ranges

Non-Burst Read Cycle Timing Waveform

CLK

ADSP

ADSC

ADDRESS

Av Aw Ax Ay Az

GW,BWE,BWx

1

CE, CS

CS

0

OE

DATA

OUT

NOTES:

1. ZZ input is LOW, ADV is HIGH and LBO is Don't Care for this cycle.

2. (Ax) represents the data for address Ax, etc.

3. For read cycles, ADSP and ADSC function identically and are therefore interchangable.

(Av) (Aw) (Ax) (Ay)

Non-Burst Write Cycle Timing Waveform

CLK

5310drw14

,

ADSP

ADSC

ADDRES S

Av Aw Ax AzAy

GW

CE, CS

1

CS

0

DATA

IN

NOTES:

1. ZZ input is LOW, ADV and OE are HIGH, and LBO is Don't Care for this cycle.

2. (Ax) represents the data for address Ax, etc.

3. Although only GW writes are shown, the functionality of BWE and BWx together is the same as GW.

4. For write cycles, ADSP and ADSC have different limitations.

(Av) (Aw) (Ax) (Az)(Ay)

6.42

18

5310 drw 15

,

IDT71V67603, IDT71V67803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with

3.3V I/O, Pipelined Outputs, Single Cycle Deselect Commercial and Industrial Temperature Ranges

100-Pin Plastic Thin Quad Flatpack (TQFP) Package Diagram Outline

6.42

19

IDT71V67603, IDT71V67803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with

3.3V I/O, Pipelined Outputs, Single Cycle Deselect Commercial and Industrial Temperature Ranges

119 Ball Grid Array (BGA) Package Diagram Outline

6.42

20

IDT71V67603, IDT71V67803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with

3.3V I/O, Pipelined Outputs, Single Cycle Deselect Commercial and Industrial Temperature Ranges

165 Fine Pitch Ball Grid Array (fBGA) Package Diagram Outline

6.42

21

IDT71V67603, IDT71V67803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with

3.3V I/O, Pipelined Outputs, Single Cycle Deselect Commercial and Industrial Temperature Ranges

Ordering Information

ID T XXX

Device

Type

S

Power

X

SpeedXXPackage

X

X

P roce ss/T emp eratu re R ange

Blank
I

G
PF

BG
BQ

166*
150
133

71V 67603
71V 67803

* Industrial temp erature not a vailable on 166M Hz devices

Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)

Res tricted ha zardous substance device
100-pin Plasti c Thin Quad Flatpack (TQFP)

119 Ball Grid Array (BGA)
165 fi ne Pi t ch Bal lGrid Array

Frequency in M egahertz

256K x 36 Pipelined B urstSynchronous S RAM
512K x 18 Pipelined B urstSynchronous S RAM

,

5310 drw 13

6.42

22

IDT71V67603, IDT71V67803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with

3.3V I/O, Pipelined Outputs, Single Cycle Deselect Commercial and Industrial Temperature Ranges

Datasheet Document History

12/31/99 Created datasheet from 71V676 and 71V678 datasheets.

I/O voltage and speed grade offerings have been split into separate part numbers.
See the following datasheets for:

3.3V I/O, 133–166MHz 71V67603

2.5V I/O, 133–166MHz 71V67602

3.3V I/O, 183–200MHz 71V67613

2.5V I/O, 183–200MHz 71V67612

04/26/00 Pg. 4 Add capacitance for BGA package; Insert clarification note to Absolute Max Ratings and Recommended

Operating Temperature tables.
Pg. 7 Replace Pin U6 with TRST pin in BGA pin configuration; Add pin description note in pinout
Pg. 18 Inserted 100 pin TQFP Package Diagram Outline

05/24/00 Pg. 1,8,4,21 Add new package offering, 13 x 15 fBGA

22
Pg. 5,6,7,8 Correct note 2 in BGA and TQFP pinouts
Pg. 20 Correction in the119BGA Package Diagram Outline

07/12/00 Pg. 5,6 Remove note from TQFP pinout

Pg. 7 Add/Remove reference note from BG119 pinout
Pg. 9 Remove note from BQ165 pinout
Pg. 20 Update BG119 Package Diagram Outline dimensions

12/18/00 Pg. 9 Updated ISB2 levels for F=133-166MHz
10/29/01 Pg. 1,2 Remove 166MHz and JTAG pins

Pg. 7,8 Updated pins U2-U6 to DNU and P5,P7,R5 & R7 to DNU
Pg. 9 Remove 166MHz and raise range by 10mA on 150Mhz and 133MHz
Pg. 12,22 Remove 166MHz

10/22/02 Pg.1-22 Changed datasheet from Advanced to final release.

Pg. 4,9,12, Added I temp to datasheet.
22

11/19/02 Pg.1,9,12,22Added 166MHz to datasheet.
04/15 /03 Pg.4 Updated165fBGA table from TBD to 7.
09/30/04 Pg.7 Updated 119BGA pin configurations-reordered I/O signals on P6, P7 (128K x 36)

and P7, N6, L6, K7, H6, G7, F6, E7, D6 (256K x 18).
Pg.22 Added "Restricted hazardous substance device" to ordering information.

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Santa Clara, CA 95054 fax: [phone]

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6.42

23