Datasheet IDT71V3577S, IDT71V3579S, IDT71V3577SA, IDT71V3579SA Datasheet (IDT)

查询IDT71V3577S75BGG供应商

128K X 36, 256K X 18

3.3V Synchronous SRAMs

3.3V I/O, Flow-Through Outputs
Burst Counter , Single Cycle Deselect

Features

◆

128K x 36, 256K x 18 memory configurations

◆◆

◆

◆◆

Supports fast access times:

Commercial:
– 7.5ns up to 117MHz clock frequency
Commercial and Industrial:
– 8.0ns up to 100MHz clock frequency
– 8.5ns up to 87MHz clock frequency

◆

LBOLBO

LBO input selects interleaved or linear burst mode

LBOLBO

◆◆

◆

◆◆

Self-timed write cycle with global write control (
enable (

◆◆

◆

◆◆

3.3V core power supply

◆◆

◆

◆◆

Power down controlled by ZZ input

◆◆

◆

◆◆

3.3V I/O

◆◆

◆

◆◆

Optional - Boundary Scan JTAG Interface (IEEE 1149.1

BWEBWE

BWE), and byte writes (

BWEBWE

BWBW

BWx)

BWBW

compliant)

◆◆

◆

◆◆

Packaged in a JEDEC Standard 100-pin plastic thin quad
flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch ball
grid array

GWGW

GW), byte write

GWGW

IDT71V3577S

IDT71V3579S
IDT71V3577SA
IDT71V3579SA

Description

The IDT71V3577/79 are high-speed SRAMs organized as
128K x 36/256K x 18. The IDT71V3577/79 SRAMs contain write, data,
address and control registers. There are no registers in the data output
path (flow-through architecture). Internal logic allows the SRAM to gen­erate a self-timed write based upon a decision which can be left until the
end of the write cycle.

The burst mode feature offers the highest level of performance to the
system designer, as the IDT71V3577/79 can provide four cycles of data
for a single address presented to the SRAM. An internal burst address
counter accepts the first cycle address from the processor, initiating the
access sequence. The first cycle of output data will flow-through from the
array after a clock-to-data access time delay from the rising clock edge of
the same cycle. If burst mode operation is selected (ADV=LOW), the
subsequent three cycles of output data will be available to the user on the
next three rising clock edges. The order of these three addresses are
defined by the internal burst counter and the LBO input pin.

The IDT71V3577/79 SRAMs utilize IDT’s latest high-performance
CMOS process and are packaged in a JEDEC standard 14mm x 20mm
100-pin thin plastic quad flatpack (TQFP) as well as a 119 ball grid array
(BGA) and a 165 fine pitch ball grid array (fBGA).

Pin Description Summary

A0-A

17

CE

,

CS

CS

0

1

OE

GW

BWE

BW

(1)

,

BW

3

4

P4

,

,

BW

BW

1

2

CLK Clo ck Inpu t N/A

ADV

ADSC

ADSP

LBO

TMS Test Mode Select Input Synchronous
TDI Test Data Inp ut Inpu t Sy nchr ono us
TCK Test Clock Input N/A
TDO Test Data Outp ut Outp ut S y nchr ono us

TRST

ZZ Sleep Mode Input Asynchronous
I/O0-I/O31, I/OP1-I/O
VDD, V

DDQ

V

SS

NOTE:

1. BW3 and BW4 are not applicable for the IDT71V3579.

©2005 Integrated Device Technology, Inc.

Address Inputs Input Synchronous
Chip Enable Input Sy nchronous
Chip S e l e c ts Input Sy nc hr o no us
Output Enable Input Asynchronous
Global Write Enable Input Synchronous
Byte Write Enable Input Sy nchronous
Indi v idua l By te Wri te S e l e c ts Inpu t Sy nc hr o no us

Burs t A d d r e s s A d v anc e Inpu t Sy nc hr o no us
Ad d r e ss S tatus (Cac he Contro l l e r) Inpu t Sy nc hr o no us
Ad d re ss Status (Pr oc e ss o r) Inpu t Sy nchr ono us
Linear / Interleaved Burst Order Input DC

JTAG Reset (Optional) Input Asynchronous

Data Inp ut / Outp ut I/O Sy nc hrono us
Co re P owe r, I/O P o we r Supp l y N/A
Ground Supply N/A

FEBRUARY 2005

1

5280 tb l 01

DSC-5280/08

IDT71V3577, IDT71V3579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

Symbol

Pin Function

I/O

Active

Descrip tion

3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges

Pin Definitions

17

A0-A

ADSC

ADSP

ADV

Address Inputs I N/A Synchronous Address inputs. The address register is triggered by a combi-nation of the rising edge of CLK

Address Status

(Cache Co ntrol le r)

Address Status

(Processor)

Burst Address

Ad vance

(1)

and

ADSC

Low or

ADSP

Low and CE Low.

I LOW Synchronous Address Status from Cache Controller.

address registers with new addresses.

I LOW Synchronous Address Status from Processor.

registers with new addresses.

ADSP

I LOW Synchronous Address Advance.

controlling burst access after the initial address is loaded. When the input is HIGH the burst counter is not

ADSC

is an ac tive LOW inp ut that is used to lo ad the

ADSP

is an active LOW inp ut that is used to l oad the add res s

is gated by CE.

ADV

is an active LOW input that is used to advance the internal burst counter,

incremented; that is, there is no address advance.

1

4

BW

BW

BWE

Byte Write Enable I LOW Synchronous byte write enable gates the byte write inputs

then BWx inputs are passed to the next stage in the circuit. If

BWE

-

. If

BWE

is LOW at the rising edge of CLK

is HIGH then the byte write inputs are

blocked and only GW can initiate a write cycle .

BW

1

CE

-

BW

4

Individual Byte
Write E nabl e s

I LOW Synchronous byte write enables.

write causes all outputs to be disabled.

Chip Enable I LOW Sy nchronous chip enable. CE is used with CS0 and

1

BW

controls I/O

0-7

, I/OP1,

CS

2

BW

controls I/O

1

to enabl e the IDT71V3577/79. CE also gate s

8-15

, I/OP2, etc. Any active byte

ADSP

CLK Clock I N/A This is the clock input. All timing references for the device are made with respect to this input.
CS

CS

GW

I/O0-I/O

I/OP1-I/O

LBO

0

1

Chip Select 0 I HIGH Synchronous active HIGH chip select. CS0 is used with CE and

1

Chip S el ec t 1 I LOW Sync hro no us active LOW chip s el ec t.

Global Write

Enab l e

31

Data Input/Output I/O N/A Synchronous data input/output (I/O) pins. The data input path is registered, triggered by the rising edge of

P4

I LOW Sy nchronous global write enable. This input will write all fo ur 9-bit data b ytes when LOW on the rising edge of

CLK. GW supersedes individual byte write enables.

CLK. The data o utput path is flow-through (no output register).

Linear Burst Order I LOW Asynchronous burst order selection input. When

LBO

When

is LOW the Linear burst sequence is selected.

CS

is used with CE and CS0 to e nab le th e c hip .

LBO

is HIGH, the inter-leaved burst sequence is selected.

1

CS

to enable the chip.

LBO

is a static inp ut and must no t chang e s tate

while the device is operating.

OE

Output Enabl e I LOW A sy nchro nous o utput enab le . Whe n OE is LOW the data output drivers are enabled on the I/O pins if the chip

is also selected. When

OE

is HIGH the I/O pins are in a high-impedance state.

TMS Test ModeSelect I N/A Gives input command for TAP controller. Sampled on rising edge of TDK. This pin has an internal pullup.

TDI Test Da ta Inp ut I N/ A

TCK Test Clock I N/A

TDO Test Data Outp ut O N/ A

TRST

JTAG Reset

(Optional)

ILOW

Serial input of registers placed between TDI and TDO. Sampled on rising edge of TCK. This pin has an
internal pullup.

Clock input of TAP controller. Each TAP event is clocked. Test inputs are captured on rising edge of TCK,
while test outputs are driven from the falling edge of TCK. This pin has an internal pullup.

Serial output of registers placed be tween TDI and TDO. This output is active depending on the state of the
TAP controller.

Optional Asynchronous JTAG reset. Can be used to reset the TAP contro ller, but not required. JTAG reset
occurs automatically at p ower up and also resets using TMS and TCK pe r IEEE 1149.1. If not us ed

TRST

be left floating. This pin has an internal pullup. Only available in BGA package.
Asynchronous sleep mode input. ZZ HIGH will g ate the CLK inte rnally and po wer down the IDT71V3577/79 to

ZZ Sleep Mode I HIGH

its lowest power consumption level. Data retention is guaranteed in Sleep Mode.This pin has an internal pull
down.

DD

V

DDQ

V

V

SS

Power Supply N/A N/A 3.3V core power supply.
Power Supply N/A N/A 3.3V I/O Supply.

Ground N/A N /A Ground.

NC No Connect N/A N/A NC pins are not electrically connected to the device.

NOTE:

1. All synchronous inputs must meet specified setup and hold times with respect to CLK.

.

can

5280 tbl 02

6.422

IDT71V3577, IDT71V3579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges

Functional Block Diagram

LBO

ADV

CLK

ADSC

ADSP

CEN

CLR

Binary

Counter

Burst

Sequence

2

Burst

Logic

Q1

Q0

A0*

A1*

INTERNAL
ADDRESS

17/18

128K x 36/
256K x 18-

BIT

MEMORY

ARRAY

A0-A

BWE

BW

BW

BW

BW

I/O0-I/O

I/OP1- I/O

16/17

GW

CE

CS

CS

ZZ

OE

CLK EN

ADDRESS

REGISTER

Byte 1

Write Register

1

Byte 2

Write Register

2

Byte 3

Write Register

3

Byte 4

WriteRegister

4

0

1

Powerdown

D

Enable
Register

CLK EN

17/18

Q

2

A0,A

1

A

2-A17

9

9

9

9

DATA INPUT

REGISTER

Byte 1
Write Driver

Byte 2
Write Driver

Byte 3
Write Driver

Byte 4
Write Driver

36/18

OE

OUTPUT
BUFFER

36/18

,

31

P4

36/18

TMS

TDI

TCK

TRST

(Optional)

JTAG

(SA Version)

5280 drw 01

TDO

6.42

3

IDT71V3577, IDT71V3579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

Symbol

Rati ng

Commercial &

Industrial Values

Uni t

TERM

TERM

DD

TERM

TERM

DDQ

A

Commercial

Industrial

BIAS

STG

T

OUT

Grade

Temperature

(1)

VSSVDDV

DDQ

Symbol

Parameter

Min.

Typ.

Max.

Unit

DD

DDQ

SS

IH

DD

IH

DDQ

IL

Symbol

Parameter

(1)

Conditions

Max.

Unit

CINInp ut Cap ac itanc e

VIN = 3dV

5pFC

I/O

I/O Cap acitanc e

V

OUT

= 3dV

7

pF

5280 tbl 07

Symb ol

Par a me t er

(1)

Con dit io ns

Max .

Unit

CINInp ut Cap ac itanc e

VIN = 3dV

7pFC

I/O

I/O Cap aci tance

V

OUT

= 3dV

7

pF

5280 tbl 07a

Symbo l

Par a me t er

(1)

Con dit io ns

Max .

Unit

CINInp ut Cap ac itanc e

VIN = 3dV

7pFC

I/O

I/O Cap acitanc e

V

OUT

= 3dV

7

pF

5280 tb l 07b

3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges

Absolute Maximum Ratings

(1)

Recommended Operating

Temperature Supply Voltage

(2)

V

(3,6)

V

(4,6)

V

(5,6)

V

(7)

T

T

T

P
I

NOTES:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.

2. VDD terminals only.

3. VDDQ terminals only.

4. Input terminals only.

5. I/O terminals only.

6. This is a steady-state DC parameter that applies after the power supplies have
ramped up. Power supply sequencing is not necessary; however, the voltage
on any input or I/O pin cannot exceed VDDQ during power supply ramp up.

7. TA is the "instant on" case temperature.

Terminal Voltage with

-0.5 to +4.6 V

Re sp e c t to GND
Terminal Voltage with

-0.5 to V

Re sp e c t to GND
Terminal Voltage with

-0.5 to VDD +0.5 V

Re sp e c t to GND
Terminal Voltage with

-0.5 to V

+0.5 V

Re sp e c t to GND

-0 to + 70

o

Operating Temperature

-40 to + 85

o

Operating Temperature
Temperature

-55 to +125

o

Under Bias
Storage

-55 to +125

o

Temperature
Power Dis sipation 2.0 W
DC Outp ut Cu rre nt 50 mA

5280 tbl 03

Comm ercial 0° C to +70°C 0V 3.3V± 5% 3. 3V± 5%

V

Ind us tria l -40° C to + 8 5° C 0 V 3.3V ±5% 3. 3V ±5%

NOTES:

1. TA is the "instant on" case temperature.

Recommended DC Operating

Conditions

C

V

C

C

C

NOTES:

1. V IH (max) = VDDQ + 1.0V for pulse width less than tCYC/2, once per cycle.

2. VIL (min) = -1.0V for pulse width less than tCYC/2, once per cycle.

Core Supply Voltage 3. 135 3.3 3.465 V

V

I/O Supply Voltage 3.135 3.3 3.465 V

V

Supply Voltage 0 0 0 V

V

Input High Voltage - Input s 2. 0

V

Input H igh Voltage - I /O 2. 0

V

Input Low Voltage -0.3

5280 tbl 04

____

V

+0.3 V

____

V

(2)

____

(1)

+0.3

0.8 V

5280 tbl 06

V

100 Pin TQFP Capacitance

(TA = +25° C, f = 1.0mhz)

165 fBGA Capacitance

(TA = +25° C, f = 1.0mhz)

NOTE:

1. This parameter is guaranteed by device characterization, but not production tested.

6.424

119 BGA Capacitance

(TA = +25° C, f = 1.0mhz)

IDT71V3577, IDT71V3579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges

Pin Configuration  128K x 36

P

4

3

2

1

0

E

S

W

A6A7C

10099989796959493929190 8786858483828189 88

W

B

B

C

1

D

S

S

W

W

B

B

C

LK

D

S

V

C

V

W
G

C

E

E

W

O

B

V

S

S

D

D

D
A

8A9

A

A

A

V

I/O

V

V

V

V

I/O

I/O
I/O

I/O
I/O
I/O
I/O

I/O
I/O

I/O
I/O

I/O
I/O
I/O
I/O

I/O
I/O

DDQ

V

V

DDQ

SS

V

NC

V

DDQ

V

V

DDQ

DD

1

P3

2

16

3

17

4
5

SS

6

18

7

19

8

20

9

21

10

SS

11
12

22

13

23

14

(1)

15
16
17

SS

18

24

19

25

20
21

SS

22

26

23

27

24

28

25

29

26

SS

27
28

30

29

31

30

P4

313233 34 35 363738 39 40 41 42 43 44 45 46 47 48 49 50

1

O
LB

3

5

A

A4A

0

2

A

A

A

S

D

C

C

C

S

N

N

V

C

D

N

N

V

12

10

A

13

11

A

A

A

80

I/O
I/O
I/O
V

DDQ
SS

V
I/O
I/O
I/O
I/O
V

SS

V

DDQ

I/O
I/O
V

SS

NC
V

DD

ZZ
I/O
I/O
V

DDQ

V

SS

I/O
I/O

I/O
I/O
V

SS

V

DDQ

I/O
I/O

I/O

5280 drw 02a

P2
15
14

13
12
11
10

9
8

(2)

7
6

,

5
4

3
2

1
0

P1

79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

16

14

15

A

A

A

100 TQFP

Top View

NOTES:

1. Pin 14 does not have to be directly connected to VSS as long as the input voltage is < VIL.

2. Pin 64 can be left unconnected and the device will always remain in active mode.

6.42

5

IDT71V3577, IDT71V3579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges

Pin Configuration  256K x 18

P

C

2

1

0

C

E

A6A7C

100 99 98 97 96 95 94 93 92 91 9 0 87 86 8 5 84 83 82 8189 88

C

S

N

N

C

1

D

S

S

W
B

D

W
B

S

C

V

V

LK
C

E

E

W

W
B

O

G

V

S

S

D

D

D
A

8A9

A

A

A

V

V

V

V

I/O

V

I/O
I/O

SS

I/O
I/O

I/O
I/O

NC
NC
NC

DDQ

V

SS

NC

NC
I/O
I/O
V

SS

DDQ

V

DD

NC
V

SS

DDQ

V

SS

NC
V

SS

DDQ

NC

NC

NC

1
2
3
4
5
6
7
8

8

9

9

10
11
12

10

13

11

(1)

14
15
16
17
18

12

19

13

20
21
22

14

23

15

24

P2

25
26
27
28
29
30

313233 34 35 363738 39 40 41 42 43 44 45 46 47 48 49 50

0

O
LB

5

2

1

3

A

A4A

A

C

A

A

N

D

S

C
N

C

C

S

D

V

V

11

N

N

A

14

12

13

A

A

A

80

A

79
78
77
76
75
74
73

72

71

70

69

68
67
66
65
64

63
62
61
60

59
58
57
56

55
54
53
52

51

16

17

15

A

A

A

10

NC
NC
V

DDQ

V

SS

NC
I/O
I/O
I/O
V

SS

V

DDQ

I/O
I/O
V

SS

NC
V

DD

ZZ
I/O
I/O
V

DDQ

V

SS

I/O
I/O

NC
NC
V

SS

V

DDQ

NC
NC
NC

5280 drw 02b

P1
7
6

5
4

(2)

3
2

1
0

,

100 TQFP

Top View

NOTES:

1. Pin 14 does not have to be directly connected to VSS as long as the input voltage is < VIL.

2. Pin 64 can be left unconnected and the device will always remain in active mode.

6.426

IDT71V3577, IDT71V3579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges

Pin Configuration  128K x 36, 119 BGA

1234567

DDQ

V

A

NC CS

B
C

NC

16

I/O

D

17

I/O

E

DDQ

V

F

20

I/O

G

22

I/O

H

DDQ

V

J

24

I/O

K

25

I/O

L

DDQ

V

M

29

I/O

N

31

I/O

P

NC A

R

NC NC A

T

DDQ

V

U

6

A

7

A

P3

I/O

18

I/O

19

I/O

21

I/O

23

I/O

DD

V

26

I/O

27

I/O

28

I/O

30

I/O

P4

I/O

5

NC/TMS

0

(2)

4

A

3

A

2

A

SS

V

SS

V

SS

V

3

BW

SS

V

NC V

SS

V

4

BW

SS

V

SS

V

SS

V
LBO

10

(2)

NC/TDI

ADSP
ADSC

DD

V

NC V

CE
OE

ADV BW

GW

DD

CLK V

NC

BWE

1

A

0

A

DD

V

11

A

(2)

NC/TCK

8

A

9

A

12

A

SS

SS

V

SS

V

2

SS

V

NC V

SS

1

BW

SS

V

SS

V

SS

V

SS

V

14

A

NC/TDO

(2)

16

A

1

CS

15

A

P2

I/O

13

I/O

12

I/O

11

I/O

9

I/O

DD

6

I/O

4

I/O

3

I/O

2

I/O

0

I/O

13

NC

NC/TRST

V

I/O
I/O

V

I/O

V

V

(2,4)

V

5280 drw02c

DDQ

NC
NC

DDQ

I/O

DDQ

I/O
I/O

DDQ

I/O
I/O

NCA

ZZ

DDQ

15

14

10

8

7

5

1

P1

(3)

Top View

Pin Configuration  256K x 18, 119 BGA

1234567

DDQ

A V
B NC CS

NC

C

8

D I/ O

NC I/O

E

DDQ

F V

NC I/O

G

11

H I/O

DDQ

V

J

K NC I/O

13

L I/O

DDQ

M V

15

I/O

N

NC I/O

P
R NC A
T NC A

DDQ

U V

NOTES:

1. R5 does not have to be directly connected to VSS as long as the input voltage is < VIL.

2. These pins are NC for the "S" version or the JTAG signal listed for the "SA" version. Note: If NC, these pins can either be tied to VSS, VDD or left floating.

3. T7 can be left unconnected and the device will always remain in active mode.

4. TRST is offered as an optional JTAG Reset if required in the application. If not needed, can be left floating and will internally be pulled to V DD.

6

A

7

A

NC V

NC V

10

NC V

DD

V

12

NC

14

I/O

NC V

P2

5

10

NC/TMS

4

A

0

A
A

SS

9

SS

V

SS

SS

NC V

SS

V

SS

V

SS

V

SS

SS

V
LBO

A

(2)

NC/TDI

15

3

2

2

(2)

ADSP
ADSC

V

NC V

CE
OE

ADVBW

GW

CLK V

NC

BWE

A
A

V

NC A

NC/TCK

DD

DD

1

0

DD

(2)

A
A

A

V
V
V
V

NC V

BW
V
V
V

V

NC/TDO

SS

SS

SS

SS

SS

SS

SS

SS

SS

13

SS

14

8

9

1

(2)

16

A

1

CS

17

A

7

I/O

NC I/O

5

I/O

NC I/O

3

I/O

DD

NC I/O

1

I/O

NC V

0

I/O

NC I/O

12

11

A

NC/TRST

(2,4)

5280 drw 02d

V

V

V

V

DDQ

NC
NC
NC

DDQ

NC

DDQ

NC

DDQ

NC

NCA

ZZ

DDQ

6

4

2

P1

(3)

,

Top View

6.42

7

IDT71V3577, IDT71V3579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

7CE1BW3BW2CS1

8

6CS0BW4BW1

9

DDQVSSVSSVSSVSSVSSVDDQ

P2

16VDDQVDDVSSVSSVSSVDDVDDQ

15

14

18VDDQVDDVSSVSSVSSVDDVDDQ

13

12

20VDDQVDDVSSVSSVSSVDDVDDQ

11

10

22VDDQVDDVSSVSSVSSVDDVDDQ

9

8

SS

DDVSSVSSVSSVDD

24VDDQVDDVSSVSSVSSVDDVDDQ

7

6

26VDDQVDDVSSVSSVSSVDDVDDQ

5

4

28VDDQVDDVSSVSSVSSVDDVDDQ

3

2

30VDDQVDDVSSVSSVSSVDDVDDQ

1

0

DDQVSS

NC/

SSVDDQ

P1

5A2

1

10A13A14

4A3

0

11A12A15A16

5280 tbl 17

7CE1BW2

1

8A10

0

1

9

DDQVSSVSSVSSVSSVSSVDDQ

P1

DDQVDDVSSVSSVSSVDDVDDQ

7

DDQVDDVSSVSSVSSVDDVDDQ

6

DDQVDDVSSVSSVSSVDDVDDQ

5

DDQVDDVSSVSSVSSVDDVDDQ

4

SS

DDVSSVSSVSSVDD

DDQVDDVSSVSSVSSVDDVDDQ

3

13

DDQVDDVSSVSSVSSVDDVDDQ

2

DDQVDDVSSVSSVSSVDDVDDQ

1

DDQVDDVSSVSSVSSVDDVDDQ

0

P2

DDQVSS

NC/

SSVDDQ

5A2

1

11A14A15

4A3

0

12A13A16A17

5280 tbl 17a

3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges

Pin Configuration  128K x 36, 165 fBGA

1234567891011

ANC

BNC A
CI/OP3NC V

(4)

A

CLK

BWE ADSC AD V

GW OE ADSP

A
A

NC

NC

(4)

NC I/O
DI/O17I/O
EI/O19I/O
FI/O21I/O
GI/O23I/O
HV

(1)

NC NC V
JI/O25I/O
KI/O27I/O
LI/O29I/O

MI/O31I/O

NI/OP4NC V

NC

(4)

(4)

PNCNC
R

LBO

(2, 5)

TRST

A
A

NC/TDI

NC/TMS

(2)

(2)

NC

(4)

A
A

Pin Configuration  256K x 18, 165 fBGA

1234567891011

ANC

(4)

BNC A6CS
CNC NCV

A

NC

NC

BW

CS

CLK

NC V

(2)

NC/TDO

NC/TCK

A

(2)

A

BWE ADSC ADV

GW OE ADSP

I/O
I/O
I/O

I/O
I/O
I/O

I/O

NC NC ZZ

I/O
I/O
I/O

I/O

NC I/O

NC

A
A
NC I/O

I/O

I/O
I/O
I/O
I/O

NC

(3)

(4)

(4)

DNC I/O8V
ENC I/O9V
FNCI/O10V

GNC I/O11V

HV

(1)

NC NC V
JI/O12NC V
KI/O

NC V
LI/O14NC V

MI/O15NC V

NI/O
PNC NC

R

LBO

NC V

(4)

(4)

NC

NC NC ZZ

(2, 5)

TRST

A
A

NC/TDI

NC/TMS

(2)

(2)

NC

(4)

A

A

NC V

NC/TDO

(2)

NC/TCK

(2)

A

A

NC I/O
NC I/O
NC I/O
NC I/O

I/O
I/O
I/O
I/O

NC NC

NC

(3)

NC
NC
NC
NC

(4)

NOTES:

1. H1 does not have to be directly VSS as long as input voltage is < VIL

2. These pins are NC for the "S" version or the JTAG signal listed for the "SA" version. Note: If NC, these pins can either be tied to VSS, VDD or left floating.

3. H11 can be left unconnected and the device will always remain in active mode.

4. Pins P11, N6, B11, A1, R2 and P2 are reserved for 9M, 18M, 36M, 72M, 144M and 288M respectively.

5. TRST is offered as an optional JTAG Reset if required in the application. If not needed, can be left floating and will internally be pulled to VDD.

6.428

IDT71V3577, IDT71V3579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

Symbol

Parameter

Test Conditions

Min.

Max.

Unit

Symbol

Parameter

Test Conditions

7.5ns

8ns

8.5ns

Unit

Com'l Only

Com'l

Ind

Com'l

Ind

DD

DDQ

MAX

SB1

DDQ

SB2

DDQ

MAX

ZZ

HD, VDD

52 80 tbl 09

3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges

DC Electrical Characteristics Over the Operating

Temperature and Supply Voltage Range

(VDD = 3.3V ± 5%)

|ILI| Inp ut Le akag e Current VDD = Max., VIN = 0V to V

and JTAG Input Leakage Current

ZZ ,

LI

|

|I

|ILO| Output Leakage Current V

OL

V

OH

V

NOTE:

1. The LBO, TMS, TDI, TCK and TRST pins will be internally pulled to VDD and the ZZ in will be internally pulled to VSS if they are not actively driven in the application.

LBO

Output Low Vol tage IOL = +8mA, VDD = Min.
Output Hig h Voltage IOH = -8mA, VDD = Min. 2.4

(1)

VDD = Max., VIN = 0V to V

OUT

= 0V to V

DDQ

DD

DD

, Device De selected

___

___

___

___

5µA

30 µ A

5µA

0.4 V

___

V

5280 tbl 08

DC Electrical Characteristics Over the Operating

Temperature and Supply Voltage Range

Operating Power Supply Current Device Selected, Outputs Open, VDD = Max.,

I

I

CMOS Stand by Power
Supply Current

I

Cloc k Running Po wer
Supply Current

Full Sleep Mode Supply Current ZZ > V

I

NOTES:

1. All values are maximum guaranteed values.

2. At f = fMAX, inputs are cycling at the maximum frequency of read cycles of 1/tCYC while ADSC = LOW; f=0 means no input lines are changing.

3. For I/Os VHD = VDDQ - 0.2V, VLD = 0.2V. For other inputs VHD = VDD - 0.2V, VLD = 0.2V.

V

= Max., VIN > VIH or < VIL, f = f

Device Deselecte d, Outputs Open, VDD = Max.,

V

= Max., VIN > VHD or < VLD, f = 0

Device Deselecte d, Outputs Open, VDD = Max.,

V

= Max., VIN > VHD or < VLD, f = f

= Max. 30 30 35 30 35 mA

(1)

(2,3)

(2)

255 200 210 180 190 mA

30 30 35 30 35 mA

(2,.3)

90 85 95 80 90 mA

(VDDQ = 3.3V)

Inp ut Pu ls e Le v e l s
Inp ut Ris e / F all Time s
Inp ut Timi ng Re fe re nc e L e ve l s
Output Timing Refe renc e Le v e ls
AC Test Lo ad

0 to 3V

2ns

1.5V

1.5V

See Figure 1

5280 tbl 10

6.42

9

AC Test LoadAC Test Conditions

∆tCD

(Typical, ns)

Figure 2. Lumped Capacitive Load, Typical Derating

V

50Ω

I/O

6

0

=50Ω

Z

Figure 1. AC Test Load

5
4
3
2
1

20 30 50 100 200

80

Capacitance (pF)

DDQ

5280drw 03

5280 drw05

/2

,

,

IDT71V3577, IDT71V3579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

Operation

Address

UsedCECS

0CS1

(2 )

CLK

I/O

3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges

Synchronous Truth Table

(1,3)

ADSP ADSC ADV GW BWE BWxOE

Des ele cte d Cycle , P owe r Down No ne H X X X L X X X X X

↑

Des ele cte d Cycle , P owe r Down No ne L X H L X X X X X X ↑ HI-Z
Des ele cte d Cycle , P owe r Down No ne L L X L X X X X X X ↑ HI-Z
Des ele cte d Cycle , P owe r Down No ne L X H X L X X X X X ↑ HI-Z
Des ele cte d Cycle , P owe r Down No ne L L X X L X X X X X ↑ HI-Z
Read Cy cle , Be g in Bu rst Ex ternal L H L L X X X X X L

↑

Read Cy cle , Be g in Bu rst Ex ternal L H L L X X X X X H ↑ HI-Z
Read Cy cle , Be g in Bu rst Ex ternal L H L H L X H H X L ↑ D
Read Cy cle , Be g in Bu rst Ex ternal L H L H L X H L H L

↑

Read Cy cle , Be g in Bu rst Ex ternal L H L H L X H L H H ↑ HI-Z
Write Cycle, Begin Burst External L H L H L X H L L X ↑ D
Write Cycle, Begin Burst External L H L H L X L X X X ↑ D
Re ad Cy c le , Co nti nue B urs t Ne xt X X X H H L H H X L ↑ D
Re ad Cy c le , Co nti nue B urs t Ne xt X X X H H L H H X H ↑ HI-Z
Re ad Cy c le , Co nti nue B urs t Ne xt X X X H H L H X H L ↑ D
Re ad Cy c le , Co nti nue B urs t Ne xt X X X H H L H X H H ↑ HI-Z
Re ad Cy c le , Co nti nue B urs t Ne xt H X X X H L H H X L

↑

Re ad Cy c le , Co nti nue B urs t Ne xt H X X X H L H H X H ↑ HI -Z
Re ad Cy c le , Co nti nue B urs t Ne xt H X X X H L H X H L ↑ D
Re ad Cy c le , Co nti nue B urs t Ne xt H X X X H L H X H H ↑ HI -Z
Write Cyc le , Co ntinue Bu rst Nex t X X X H H L H L L X ↑ D
Write Cyc le , Co ntinue Bu rst Nex t X X X H H L L X X X ↑ D
Write Cyc le , Co ntinue Bu rst Nex t H X X X H L H L L X ↑ D
Write Cyc le , Co ntinue Bu rst Nex t H X X X H L L X X X ↑ D
Read Cy cl e, Su sp e nd B urst Curre nt X X X H H H H H X L ↑ D
Read Cy cl e, Su sp e nd B urst Curre nt X X X H H H H H X H ↑ HI-Z
Read Cy cl e, Su sp e nd B urst Curre nt X X X H H H H X H L ↑ D
Read Cy cl e, Su sp e nd B urst Curre nt X X X H H H H X H H

↑

Read Cy cl e, Su sp e nd B urst Curre nt H X X X H H H H X L ↑ D
Read Cy cl e, Su sp e nd B urst Curre nt H X X X H H H H X H ↑ HI-Z
Read Cy cl e, Su sp e nd B urst Curre nt H X X X H H H X H L ↑ D
Read Cy cl e, Su sp e nd B urst Curre nt H X X X H H H X H H ↑ HI-Z
Write Cycle, Suspend Burst Current X X X H H H H L L X ↑ D
Write Cycle, Suspend Burst Current X X X H H H L X X X ↑ D
Write Cycle, Suspend Burst Current H X X X H H H L L X ↑ D
Write Cycle, Suspend Burst Current H X X X H H L X X X

NOTES:

↑

5280 tbl 11

1. L = VIL, H = VIH, X = Don’t Care.

2. OE is an asynchronous input.

3. ZZ - low for the table.

6.4210

HI-Z

D

D

D

HI-Z

D

OUT

OUT

OUT

IN

IN

OUT

OUT

OUT

OUT

IN

IN

IN

IN

OUT

OUT

OUT

OUT

IN

IN

IN

IN

IDT71V3577, IDT71V3579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

(3)

(3)

(3)

(3)

52 80 t b l 12

(2)

52 80 t b l 13

(1)

52 80 t b l 14

(1)

52 80 t b l 15

3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges

Synchronous Write Function Truth Table

Operation

GW BWE BW

(1, 2)

1

BW

2

BW

3

BW

4

Read HHXXXX

Read HLHHHH
Write all Bytes LXXXXX
Write all Bytes HLLLLL
Write Byte 1
Write Byte 2
Write Byte 3
Write Byte 4

HLLHHH
HLHLHH
HLHHLH
HLHHHL

NOTES:

1. L = VIL, H = VIH, X = Don’t Care.

2. BW3 and BW4 are not applicable for the IDT71V3579.

3. Multiple bytes may be selected during the same cycle.

OE

(1)

ZZ I/ O Stat us P ower

Asynchronous Truth Table

Operation

Read L L Data Out Activ e
Read H L Hig h-Z Acti ve
Wri te X L Hi g h-Z – Da ta In A ct iv e

Deselected X L High-Z Standby

Sleep Mode X H High-Z Sleep

NOTES:

1. L = VIL, H = VIH, X = Don’t Care.

2. Synchronous function pins must be biased appropriately to satisfy operation requirements.

Interleaved Burst Sequence Table ( LBO=VDD)

Seq uen ce 1 Seq uen ce 2 Sequ en ce 3 Seque nce 4

A1 A0 A1 A0 A1 A0 A1 A0

Firs t Address 0 0 0 1 1 0 1 1
Second Address 0 1 0 0 1 1 1 0
Third Addres s 1 0 1 1 0 0 0 1

Fourth Address

NOTE:

1. Upon completion of the Burst sequence the counter wraps around to its initial state.

11100100

Linear Burst Sequence Table ( LBO=VSS)

Seq uen ce 1 Seq uen ce 2 Sequ en ce 3 Seque nce 4

A1 A0 A1 A0 A1 A0 A1 A0

Firs t Address 0 0 0 1 1 0 1 1
Second Address 0 1 1 0 1 1 0 0
Third Addres s 1 0 1 1 0 0 0 1

Fourth Address

NOTE:

1. Upon completion of the Burst sequence the counter wraps around to its initial state.

11000110

6.42

11

IDT71V3577, IDT71V3579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

7.5ns

(5)

8ns

8.5ns

Symbol

Parame t er

Min.

Max.

Min.

Max.

Min.

Max.

Unit

Cl ock P aramet er

CYC

CH

CL

Output Parameters

CD

CDC

CLZ

CHZ

OE

OLZ

OHZ

Set Up Ti mes

SA

SS

SD

SW

SAV

SC

Hold Times

HA

HS

HD

HW

HAV

HC

S le ep M ode an d Con figur ation Pa r am et ers

ZZPW

ZZR

CFG

3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges

AC Electrical Characteristics

(VDD = 3.3V ±5%, Commercial and Industrial Temperature Ranges)

____

____

____

____

____

____

7.5

____

____

3.5

____

3.5

____

____

____

____

____

____

t

(1)

t

(1)

t

t
t

(2)

t
t

t
t
t

t
t
t
t
t
t

Clo ck Cycle Time 8.5
Clock High Pulse Width 3
Clock Low Pulse Width 3

Clo ck Hi g h to Vali d Data
Clo c k Hig h to Data Chang e 2

Clock High to Output Active 0

(2)

Clo c k Hig h to Data High- Z 2 3 .5 2 3.5 2 3. 5 ns
Output Enable Access Time

(2)

Outp ut E nable Lo w to Output Ac tive 0

(2)

Outp ut E nable Hig h to Output Hig h-Z

Address Setup Time 1.5
Address Status Setup Time 1.5
Data In S e tup Time 1. 5
Write Setup Time 1.5
Address Advance Setup Time 1.5
Chip Enable/Select Setup Time 1.5

____

____

____

____

10

____

4

____

4

8

____

2

____

0

3.5

____

0

3.5

____

2

____

2

____

2

____

2

____

2

____

2

11.5

4.5

4.5

____

____

____

2
0

0

2
2
2
2
2
2

____

____

____

8.5 ns

____

____

3.5 ns

____

3.5 ns

____

____

____

____

____

____

ns
ns
ns

ns
ns

ns

ns
ns
ns
ns
ns
ns

t
t
t
t
t
t

t

(3)

t
t

Address Hold Time 0.5
Address Status Hold Time 0.5
Data In Ho l d Time 0.5
Write Ho l d Tim e 0.5
Address Advance Hold Time 0.5
Chip Ena bl e/ Se le c t Hol d Time 0. 5

ZZ Pulse Width 100
ZZ Re co v e ry Tim e 1 00

(4)

Configuratio n Set-up Time 34

NOTES:

1. Measured as HIGH above VIH and LOW below VIL.

2. Transition is measured ±200mV from steady-state.

3. Device must be deselected when powered-up from sleep mode.

4. tCFG is the minimum time required to configure the device based on the LBO input. LBO is a static input and must not change during normal operation.

5. Commercial temperature range only.

6.4212

____

____

____

____

____

____

____

____

____

0.5

0.5

0.5

0.5

0.5

0.5

100
100

40

____

____

____

____

____

____

____

____

____

0.5

0.5

0.5

0.5

0.5

0.5

100
100

50

____

____

____

____

____

____

____

____

____

ns
ns
ns
ns
ns
ns

ns
ns
ns

5280 tbl 16

IDT71V3577, IDT71V3579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges

Timing Waveform of Flow-Through Read Cycle

around
raps

urst w

burst

(B

suspends
H
IG

H

V
D
A

W
H

t

V
A
H

t

V
A
S

L
C

t

C
Y
C

t

H
C

t

S
H

t

S
S

t

(1)

A
S

t

W
S

t

y
A

A
H

t

x
A

C
H

t

C
S

t

t

C
D
C

t

D
C

t

Z
H
O

t

E
O

t

(1,2)

06
rw

d
0

8
52

,

y)
2(A

O

Z
H
C

t

y)
1(A

O

y)

initial state)

4(A
O

its
to

y)

ead

3(A

R

O

-through
low

y)

urst F

2(A
O

B

y)
1(A

O

x)
1(A

O

-through

ead
R

low

LZ
O

t

F

utput

isabled

O

D

LK
C

1

P
S
D
A

C
S
D
A

S
S
E
R
D
D
A

x

W
B

E,
W

B

,

W

6.42

V

S

3)

D

C

A

ote

E,

(N

C

13

E
O

T
U
O

A

T
A
D

NOTES:

0 timing transitions are identical but inverted to the CE and CS1 signals. For example, when CE and CS1 are LOW on this waveform, CS0 is HIGH.

of the base address Ay, etc. where A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input.

1. O1 (Ax) represents the first output from the external address Ax. O1 (Ay) represents the first output from the external address Ay; O2 (Ay) represents the next output data in the burst sequence

2. ZZ input is LOW and LBO is Don't Care for this cycle.

3. CS

IDT71V3577, IDT71V3579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges

Timing Waveform of Combined Flow-Through Read and Write Cycles

07

z)
4(A

O

drw
5280

,

(1,2,3)

z)
3(A

O

ead

z)
2(A

O

C
D

z)

z)

C

t

1(A

1(A
O

O

LZ
O

t

z
A

W
H

t

L
C

t

C
Y
C

t

W
S

y

t

H
C

t

A

D
H

t

D
S

t

y)
I1(A

Z

x)

H
O

t

1(A
O

urst R
B

-through
low

F

D
C

t

rite
W

LK
C

E

D

O

t

C

t

LZ
C

x

(2)

S
H

t

S
S

t

P
S
D
A

A

A

A

H

t

S

t

S
S
E
R
D
D
A

W
G

V
D
A

E
O

t

ead
R

ingle
S

IN

T
U

A

O

T
A
D

A
T
A
D

NOTES:

the next output data in the burst sequence of the base address Az, etc. where A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input.

1. Device is selected through entire cycle; CE and CS1 are LOW, CS0 is HIGH.

2. ZZ input is LOW and LBO is Don't Care for this cycle.

3. O1 (Ax) represents the first output from the external address Ax. I1 (Ay) represents the first input from the external address Ay; O1 (Az) represents the first output from the external address Az; O2 (Az) represents

6.4214

IDT71V3577, IDT71V3579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges

Timing Waveform of Write Cycle No. 1 - GW Controlled

z)
I3(A

z)

D
tH

I2(A

W
H

t

W
S

t

z
A

z)
I1(A

D

y)

S

t

(1,2,3)

08
rw

d
5280

,

I4(A

V
A
H

t

y)
I3(A

(2)

y)
I2(A

V
A
S

edge

rising

nextcycle
the

on
pled

sam
is

and
cycle

L
C

t

C
Y
C

t

H
C

t

(1)

LK
C

S
H

t

S
S

t

P
S
D
A

A
H

A

t

S

t

C
S
D
A

a

y
A

initiates

P
S
D
A

hen
w

ignored
is

W
G

x
A

C
H

t

C
S

t

S
S
E
R
D
D

W
G

t

1

3)

S

ote

, C

(N

E
C

burst)

suspends

V
D
A

(

V
D
A

E
O

y)
(A

I2

y)
I1(A

Z
H
O

x)

t

I1(A

)
w

4(A
O

)
w

(A

3
O

address Ay; I2 (Ay) represents the next input data in the burst sequence of the base address Ay, etc. where A0 and A1 are advancing for the four word burst in the sequence defined by the state of the

T
U

IN

A

T
A
D

O

A
T
A
D

NOTES:

LBO input. In the case of input I2 (Ay) this data is valid for two cycles because ADV is high and has suspended the burst.

1. ZZ input is LOW, BWE is HIGH and LBO is Don't Care for this cycle.

2. O4 (Aw) represents the final output data in the burst sequence of the base address Aw. I1 (Ax) represents the first input from the external address Ax. I1 (Ay) represents the first input from the external

3. CS0 timing transitions are identical but inverted to the CE and CS1 signals. For example, when CE and CS1 are LOW on this waveform, CS0 is HIGH.

6.42

15

IDT71V3577, IDT71V3579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges

Timing Waveform of Write Cycle No. 2 - Byte Controlled

z)
I3(A

(1,2,3)

09
drw

5280

,

z)

D

I2(A

tH

W
H

t

z
A

W
H

t

W
S

t

W
S

t

V
A
S

t

z)
I1(A

D

y)

y)

S

t

I4(A

I4(A

y)
(A
I3

rite

xtended

urst W

E

B

y)

edge
g

risin

ext cycle
n

the
on

led
p

sam
is

and
cycle

a

ge
ed

rising

next clock
the

on
pled

sam
is

and
cycle

a

burst)
nds

suspe
H
IG

H

V
D
A

(

I2(A

y)
I2(A

y)
(A
I1

rite

urst W
B

L
C

t

C
Y
C

t

H
C

t

S
H

t

S
S

t

K

L
C

P
S
D
A

A
H

A

t

S

t

C
S
D
A

initiates

P

y

S

A

D
A

hen
w

ored
ign

is

E
W

B

x
A

S
S
E
R
D
D

initiates

P
S
D
A

hen
w
d

ignore
is

x

W
B

C
H

t

C
S

t

1

E
W

B

x

S

W
B

,C
E
C

V

3)

D
A

ote
(N

E
O

Z
H
O

x)

t

I1(A

IN

A
T
A
D

gle

rite

in

W

S

)
w

4(A
O

)

d

w

urst

ea

B

R

3(A
O

0 timing transitions are identical but inverted to the CE and CS1 signals. For example, when CE and CS1 are LOW on this waveform, CS0 is HIGH.

address Ay; I2 (Ay) represents the next input data in the burst sequence of the base address Ay, etc. where A0 and A1 are advancing for the four word burst in the sequence defined by the state of the

T
U
O

A
T
A
D

NOTES:

LBO input. In the case of input I2 (Ay) this data is valid for two cycles because ADV is high and has suspended the burst.

1. ZZ input is LOW, GW is HIGH and LBO is Don't Care for this cycle.

2. O4 (Aw) represents the final output data in the burst sequence of the base address Aw. I1 (Ax) represents the first input from the external address Ax. I1 (Ay) represents the first input from the external

3. CS

6.4216

IDT71V3577, IDT71V3579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges

Timing Waveform of Sleep (ZZ) and Power-Down Modes

z
A

R
Z

tZ

(1,2,3)

13
drw

5280

,

ode
M

nooze
S

W
P

L

C

t

C
Y
C

t

H
C

t

x)

A
H

t

x
A

S
H

t

S
S

t

A
S

t

C
H

t

E
O

t

C
S

t

1(A
O

LZ
O

t

tZZ

ead
R

ingle
S

LK
C

P
S
D
A

C

S

S

S

D

E

A

R
D
D

W
G

1

S
,C

E
C

4)
ote

(N

6.42

V
D
A

E
O

17

T
U
O

A
T
A
D

Z

Z

NOTES:

0 timing transitions are identical but inverted to the CE and CS1 signaals. For example, when CE and CS1 are LOW on this waveform, CS0 is HIGH.

1. Device must power up in deselected Mode.

2. LBO is Don't Care for this cycle.

3. It is not necessary to retain the state of the input registers throughout the Power-down cycle.

4. CS

IDT71V3577, IDT71V3579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges

Non-Burst Read Cycle Timing Waveform

CLK

ADSP

ADSC

ADDRESS

Av Aw Ax Ay Az

GW, BWE, BWx

CE, CS

1

CS

0

OE

DATA

OUT

NOTES:

1. ZZ input is LOW, ADV is HIGH and LBO is Don't Care for this cycle.

2. (Ax) represents the data for address Ax, etc.

3. For read cycles, ADSP and ADSC function identically and are therefore interchangable.

(Av) (Aw) (Ax) (Ay)

Non-Burst Write Cycle Timing Waveform

CLK

5280 drw 10

,

ADSP

ADSC

ADDRESS

Av Aw Ax AzAy

GW

CE,CS

1

CS

0

DATA

IN

NOTES:

1. ZZ input is LOW, ADV and OE are HIGH, and LBO is Don't Care for this cycle.

2. (Ax) represents the data for address Ax, etc.

3. Although only GW writes are shown, the functionality of BWE and BWx together is the same as GW.

4. For write cycles, ADSP and ADSC have different limitations.

(Av) (Aw) (Ax) (Az)(Ay)

6.4218

5280 drw 11

,

IDT71V3577, IDT71V3579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

x

Symbol

Param eter

Min.

Max .

Units

JCYC

JCH

JCL

JR

JF

JRST

JRSR

JCD

JDC

JS

JH

Register Name

Bit S ize

3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges

JTAG Interface Specification (SA Version only)

JCYC

t

t

t

JF

TCK

(1)

Device Inputs

/

TDI/TMS

(2)

Device Outputs

/

TDO

3)

(

TRST

JRST

t

NOTES:

1. Device inputs = All device inputs except TDI, TMS and TRST.

2. Device outputs = All device outputs except TDO.

3. During power up, TRST could be driven low or not be used since the JTAG circuit resets automatically. TRST is an optional JTAG reset.

JCL

t

JR

t

JRSR

t

t

JStJH

JCH

JDC

t

JCD

t

M5280 drw 01

JTAG AC Electrical

Characteristics

t

t

t

t

t
t
t

t
t

t
t

NOTES:

1. Guaranteed by design.

2. AC Test Load (Fig. 1) on external output signals.

3. Refer to AC Test Conditions stated earlier in this document.

4. JTAG operations occur at one speed (10MHz). The base device may run at any speed specified in this datasheet.

JTAG Clock Input Period 100

JTAG Clock HIGH 40

JTAG Clock Low 40

JTAG Clock Rise Time

JTAG Clock Fall Time

JTAG Reset Recovery 50

JTAG Data Output

JTAG Data Output Ho l d 0

(1,2,3,4)

____

____

JTAG Reset 50

____

JTAG Setup 25

JTAG Hold 25

____

____

____

(1)

5

(1)

5

____

____

20 ns

____

____

____

I5280 tbl 01

Scan Register Sizes

ns
ns
ns
ns
ns
ns
ns

ns
ns
ns

Instruc tion (IR) 4
Bypass (BYR) 1
JTAG Id e nti fic ati o n (J IDR) 32
Bound ary Sc an (BSR) Note (1)

NOTE:

1. The Boundary Scan Descriptive Language (BSDL) file for this device is available
by contacting your local IDT sales representative.

I5280 tbl 03

6.42

19

IDT71V3577, IDT71V3579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

Instruction Field

Value

Description

Instru ction

Description

OPCODE

EX T EST

Forces contents of the boundary scan cells onto the device

o

utputs

(1)

.

Places the boundary scan re giste r (BSR) between TDI and TDO.

0000

SAMPLE/PRELOAD

Places the boundary scan re giste r (BSR) between TDI and TDO.

SAMPLE allows data from device inputs

(2)

and outputs

(1)

to be captured

in the b o undary sc an c e lls and s hifted se riall y throug h TDO. PRELOA D

allows d ata to be input serially into the bo undary scan cells via the TDI.

0001

DEVICE_ID

Load s the J TAG ID re g is te r (JIDR) with the v e ndor ID c o d e and p lac e s

the register between TDI

and TDO.

0010

HIGHZ

Places the bypass register (BYR) between TDI and TDO. Forces all

device output drivers to a High-Z state.

0011

RESERVED

Se v er al c om b inati ons are re s e rv ed . Do no t use c od e s o the r than tho se

id e ntifie d for EXTEST, SA MPLE / PRELOA D, DEVICE_ID, HIGHZ, CLAM P,

VALIDATE and BY PASS instruc tions .

0100

RESERVED

0101

RESERVED

0110

RESERVED

0111

CLAMP

Uses BYR. Fo rces contents of the boundary scan ce lls onto the device

outputs. Places the bypass register (BYR) between TDI and TDO.

1000

RESERVED

Same as ab o ve .

1001

RESERVED

1010

RESERVED

1011

RESERVED

1100

VALIDAT E

Automatically loade d into the instruction register whenever the TAP

co ntrol le r pass es throug h the CAP TURE-IR state. The lo wer two b its '01'

are mand ate d b y the IEE E std . 1149.1 s pe c ifi cati on.

1101

RESERVED

Same as ab o ve .

1110

BYP ASS

The BYPASS instruction is used to truncate the boundary scan register

as a sing le bit in le ng th.

1111

I5280 tbl 04

3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges

JTAG Identification Register Definitions (SA Version only)

Revision Number (31:28) 0x2 Reserved for version number.
IDT Dev i ce ID (2 7:1 2) 0 x2 2C, 0x 22E De fin e s IDT p art n umb e r 71V 3577S A and 71V 357 9SA , re s p e c tiv e ly.
IDT JEDEC ID (11:1) 0x33 Allows unique identification of device vendor as IDT.
ID Register Indicator Bit (Bit 0) 1 Indicates the presence of an ID register.

I5280 tbl 02

Available JTAG Instructions

NOTES:

1. Device outputs = All device outputs except TDO.

2. Device inputs = All device inputs except TDI, TMS, and TRST.

6.4220

IDT71V3577, IDT71V3579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

g

3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges

Ordering Information

IDT XXX

Device

Type

S

X

Power

X

Speed

XX

Package

X

X

Process/

Temperature

Range

Blank
I

G

PF**
BG
BQ

75*
80
85

S
SA

Blank
Y

Commercial (0°C to +70°C)
Industrial (-40°C to+85°C)

Restricted hazardous substance device

100-pin Plastic Thin QuadFlatpack (TQFP)
119 Ball Grid Array (BGA)
165 Fine Pitch Ball Grid Array (fBGA)

Access Time in Tenths of Nanoseconds

Standard Power
Standard Power with JTAG Interface

First Generation or current stepping
SecondGenerationdie step

,

71V3577
71V3579

128K x 36 Flow-Through Burst Synchronous SRAM with 3.3V I/O
256K x 18 Flow-Through Burst Synchronous SRAM with 3.3V I/O

*Commercial temperaturerange only.
** JTAG (SA version)is not available with 100 pin TQFP packa

5280 drw 12

e

Package Information

100-Pin Thin Quad Plastic Flatpack (TQFP)
119 Ball Grid Array (BGA)
165 Fine Pitch Ball Grid Array (fBGA)
Information available on the IDT website

6.42

21

IDT71V3577, IDT71V3579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges

Datasheet Document History

7/23/99 Updated to new format
9/17/99 Pg. 2 Revised I/O pin description

Pg. 3 Revised block diagram for flow-through functionality
Pg. 8 Revised ISB1 and IZZ for speeds 7.5 to 8.5ns
Pg. 18 Added 119-lead BGA package diagram

Pg. 20 Added Datasheet Document History
12/31/99 Pp. 1, 4, 8, 11, 19 Added Industrial Temperature range offerings
04/03/00 Pg. 18 Added 100pinTQFP Package Diagram Outline

Pg. 4 Add capacitance table for BGA package; add Industrial temperature to table; Insert note to

Absolute Max Ratings and Recommended Operating Temperature tables

06/01/00 Add new package offering, 13 x 15mm 165 fBGA

Pg. 20 Correct 119BGA Package Diagram Outline
07/15/00 Pg. 7 Add note reference to BG119 pinout

Pg. 8 Add DNU reference note to BQ165 pinout

Pg. 20 Update BG119 Package Diagram Outline Dimensions
10/25/00 Remove Preliminary status

Pg.8 Add reference note to pin N5 on BQ165 pinout, reserved for JTAG TRST
04/22/03 Pg.4 Updated 165 BGA table information from TBD to 7
06/30/03 Pg. 1,2,3,5-9 Updated datasheet with JTAG information

Pg. 5-8 Removed note for NC pins (38,39(PF package); L4, U4 (BG package) H2, N7 (BQ package))

requiring NC or connection to Vss.
Pg. 19,20 Added two pages of JTAG Specification, AC Electrical, Definitions and Instructions
Pg. 21-23 Removed old package information from the datasheet
Pg. 24 Updated ordering information with JTAG and Y stepping information. Added information

regarding packages available IDT website.

02/18/05 Pg. 21 Addedd "restricted hazardous substance device" to ordering information.

CORPORATE HEADQUARTERS for SALES: for Tech Support:

2975 Stender Way 800-345-7015 or 408-727-6116 [e-mail]
Santa Clara, CA 95054 fax: [phone], x4033

www.idt.com

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

6.4222