Datasheet IDT71V35761S183BQ, IDT71V35761S183BQI, IDT71V35761S183PF, IDT71V35761S183PFI, IDT71V35761S200BG Datasheet (Integrated Device Technology Inc)

128K x 36, 256K x 18

3.3V Synchronous SRAMs

3.3V I/O, Pipelined Outputs
Burst Counter, Single Cycle Deselect

IDT71V35761S

IDT71V35781S
IDT71V35761SA
IDT71V35781SA

Features

◆◆

◆

◆◆

128K x 36, 256K x 18 memory configurations

◆◆

◆

◆◆

Supports high system speed:

Commercial:
– 200MHz 3.1ns clock access time
Commercial and Industrial:
– 183MHz 3.3ns clock access time
– 166MHz 3.5ns clock access time

◆◆

◆

◆◆

LBO input selects interleaved or linear burst mode

◆◆

◆

◆◆

Self-timed write cycle with global write control (GW), byte write
enable (BWE), and byte writes (BWx)

◆◆

◆

◆◆

3.3V core power supply

◆◆

◆

◆◆

Power down controlled by ZZ input

◆◆

◆

◆◆

3.3V I/O

◆◆

◆

◆◆

Optional - Boundary Scan JTAG Interface (IEEE 1149.1
compliant)

◆◆

◆

◆◆

Packaged in a JEDEC Standard 100-pin plastic thin quad
flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch ball
grid array

Description

The IDT71V35761/781 are high-speed SRAMs organized as
128K x 36/256K x 18. The IDT71V35761/781 SRAMs contain write, data,
address and control registers. Internal logic allows the SRAM to generate
a self-timed write based upon a decision which can be left until the end of
the write cycle.

The burst mode feature offers the highest level of performance to the
system designer, as the IDT71V35761/81 can provide four cycles of data
for a single address presented to the SRAM. An internal burst address
counter accepts the first cycle address from the processor, initiating the
access sequence. The first cycle of output data will be pipelined for one
cycle before it is available on the next rising clock edge. If burst mode
operation is selected (ADV=LOW), the subsequent three cycles of output
data will be available to the user on the next three rising clock edges. The
order of these three addresses are defined by the internal burst counter
and the LBO input pin.

The IDT71V35761/781 SRAMs utilize IDT’s latest high-performance
CMOS process and are packaged in a JEDEC standard 14mm x 20mm
100-pin thin plastic quad flatpack (TQFP) as well as a 119 ball grid array
(BGA) and 165 fine pitch ball grid array.

Pin Description Summary

17

A0-A

CE

0

1

, CS

CS

OE

GW

BWE

BW

BW

1

2

,

,

CLK Clock Input N/A

ADV

ADSC

ADSP

LBO

TMS Test Mode Select Input Synchronous
TDI Test Data Inp ut Inp ut Sy nc hro no u s
TCK Test Clock Input N/A
TDO Tes t Data O utp ut Outp ut Syn ch ro no us

TRST

ZZ Sleep Mode Input Asynchronous

0

-I/O31, I/OP1-I/O

I/O

DD

DDQ

, V

V

SS

V

NOTE:

1. BW3 and BW4 are not applicable for the IDT71V35781.

©2003 Integrated Device Technology, Inc.

BW

(1)

BW

3

4

,

P4

Ad d re s s Inp uts Inp ut Sy nc hro no u s
Chip Enable Input Synchronous
Chip Se le c ts Input Synchro no us
Outp ut E na b le Inp ut As y nc hrono u s
Glob al Write Enab le Input Synch rono us
Byte Write Enab le Input Synchro no us
Individual Byte Write Selects Input Synchronous

Burst Address Advance Input Synchronous
Add re ss Status (Cache Co ntroll er) Input Sync hrono us
Address Status (Processor) Input Synchronous
Linear / Interleaved Burst Order Input DC

JTAG Reset (Optional) Input Asynchronous

Data Inp ut / Ou tp ut I/O Sy nc hro no u s
Core Power, I/O Power Supply N/A
Ground Supply N/A

JUNE 2003

1

5301 tbl 01

DSC-5301/03

IDT71V35761, IDT71V35781, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

Symbol

Pin Function

I/O

Active

Descri ption

11

3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges

Pin Definitions

17

A0-A

Address Inputs I N/A Synchronous Address inputs. The address register is triggered by a combination of the rising edge of CLK

(1)

and ADSC Low or ADSP Low and CE Low.

ADSC

ADSP

ADV

Address Status

(Cache Co ntrol le r)

Address Status

(Processor)

Burst Address

Ad v ance

I LOW Synchronous Address Status from Cache Controller. ADSC is an active LOW input that is used to load the

address registers with new addresses.

I LOW Synchronous Address Status from Processor. ADSP is an activ e LOW i nput that is use d to lo ad the add re ss

registers with new addresses. ADSP is gated by CE.

I LOW Synchronous Address Advance.

ADV

is an activ e LOW i nput that is use d to adv ance the i nternal b urs t
counter, controlling burst access after the initial address is lo aded . When the input is HIGH the burst counter is
not incremented; that is, there is no address advance.

BWE

Byte Write Enable I LOW Synchronous byte write enable gates the byte write inputs BW

1

-BW4. If BWE is LOW at the rising edge of CLK
then BWx inputs are passed to the next stage in the circuit. If BW E is HIGH then the byte write inputs are
blocked and only GW can initiate a write cycle .

BW

1

CE

-BW

4

Individual Byte
Write E nab le s

I LOW Synchronous byte write enables. BW1 controls I/O

write causes all outputs to be disabled.

0-7

, I/OP1, BW2 controls I/O

Chip Enable I LOW Sy nchronous chip enable. CE is us ed with CS0 and CS1 to e nabl e the IDT71V35761/781. CE also g ate s

8-15

, I/OP2, etc. Any active b yte

ADSP.

CLK Clock I N/A This is the clock input. All timing references for the device are made with respect to this input.
CS

CS

GW

0

I/O

-I/O

I/OP1-I/O

LBO

0

1

Chip Select 0 I HIGH Synchronous active HIGH chip select. CS0 is used with CE and CS1 to enable the chip.
Chip Select 1 I LOW Synchronous active LOW chip select. CS1 is used with CE and CS0 to e n ab le th e c hip .

Global Write

Enabl e

31

Data Input/Output I/O N/A Synchronous data input/output (I/O) pins. Both the data input path and data output path are registered and

P4

I LOW Sy nchronous glob al write enable. This input will write all four 9-bit data bytes when LOW o n the rising edge of

CLK. GW supersedes individual byte write enables.

triggered by the rising edge of CLK.

Linear Burst Order I LOW Asynchronous b urst order selection input. When LBO is HIGH, the interleaved burst sequence is selected.

When LBO is LOW the Line ar burst sequence is selected. LBO is a s tatic inp ut and must no t chang e s tate
while the device is operating.

OE

Output Enab le I LO W A sy nchro no us o utput e nabl e . Whe n OE is LOW the data output drivers are enabled on the I/O pins if the chip

is also selected. When OE is HIGH the I/O pins are in a high-impedance state.

TMS Test ModeSelect I N/A Gives input command for TAP contro ller. Sampled on rising edge of TDK. This pin has an internal pullup.

TDI Test Da ta Inp ut I N/ A

TCK Test Clock I N/A

TDO Test Da taOu tp ut O N/ A

TRST

JTAG Reset

(Optional)

ILOW

Serial input of registers placed between TDI and TDO. Sampled on rising edge of TCK. This pin has an
internal pullup.

Clock input of TAP controller. Each TAP event is clocked. Test inputs are c aptured on rising edge of TCK,
while test outputs are driven from the falling edge of TCK. This pin has an internal pullup.

Serial output of registers placed between TDI and TDO. This output is active depending on the state of the
TAP co ntroller.

Optional Asynchronous JTAG reset. Can be used to reset the TAP controller, but not required. JTAG reset
oc curs autom atical ly at p o wer up and also res e ts usi ng TMS and TCK p er IE EE 1149.1. If not use d TRST can
be left floating. This pin has an internal pullup. Only available in BGA package.

Asynchronous sleep mode input. ZZ HIGH will gate th e CLK internally and po wer down the IDT71V35761/35781

ZZ Sleep Mode I HIGH

to its lowest power consumption level. Data retention is guaranteed in Sleep Mode.This pin has an internal
pull down.

DD

V

DDQ

V

SS

V

Power Supply N/A N/A 3.3V core power supply.
Power Supply N/A N/A 3.3V I/O Supply.

Ground N/A N/A Ground.

NC No Connect N/A N/A NC pins are not electrically connected to the device.

NOTE:

1. All synchronous inputs must meet specified setup and hold times with respect to CLK.

5301tbl 02

6.42

2

IDT71V35761, IDT71V35781, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges

Functional Block Diagram

LBO

ADV

CLK

ADSC

ADSP

CEN

CLR

Binary

Counter

Burst

Sequence

2

Burst
Logic

Q0
Q1

A0*
A1*

INTERNAL
ADDRESS

17/18

128K x 36/
256K x 18-

BIT

MEMORY

ARRAY

A0-A

BWE

BW

BW

BW

BW

I/O0—I/O

I/OP1— I/O

16/17

GW

CE

CS

CS

ZZ

OE

CLK EN

ADDRESS

REGISTER

Byte 1

Write Register

1

Byte 2

Write Register

2

3

4

0

1

Powerdown

31

P4

36/18

Byte 3

Write Register

Byte 4

Write Register

D

Enable
Register

CLK EN

DQ

Enable
Delay
Register

17/18

Q

2

A0,A

1

2–A17

A

Byte1
Write Driver

9

Byte2
Write Driver

9

Byte3
Write Driver

9

Byte4
Write Driver

9

DATA INPUT

REGISTER

36/18

OE

OUTPUT

REGISTER

OUTPUT
BUFFER

36/18

,

5301 drw 01

TMS

TDI

TCK

JTAG

(SA Version)

TDO

TRST

(Optional)

6.42

3

IDT71V35761, IDT71V35781, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

(2)

(3,6)

(4,6)

(5,6)

(7)

o

o

o

o

5301 t bl 03

Grade

Temperature

(1)

VSSVDDV

DDQ

Symbol

Parameter

Min.

Typ.

Max.

Unit

(1)

(1)

(1)

3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges

Absolute Maximum Ratings

Commercial &

Symbol Rating

V

TERM

Termi nal Vol tage wi th
Re s p e c t to G ND

V

TERM

Termi nal Vol tage wi th
Re s p e c t to G ND

V

TERM

Termi nal Vol tage wi th

Industrial Unit

-0.5 to +4.6 V

-0.5 to V

-0.5 to VDD +0.5 V

(1)

DD

Recommended Operating
Temperature and Supply Voltage

Com me rci al 0° C to +70 ° C 0V 3.3V ± 5% 3.3V ± 5%

Industrial -40° C to +85° C 0V 3.3V± 5% 3.3V± 5%

V

NOTES:

1. TA is the "instant on" case temperature.

5301 t b l 04

Re s p e c t to G ND

V

TERM

Termi nal Vol tage wi th
Re s p e c t to G ND

Commercial

A

T

Operating Temperature

Industrial

Operating Temperature

T

BIAS

T emperature
Under Bias

T

STG

Storage
T emperature

P

T

OUT

I

NOTES:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.

2. VDD terminals only.

3. VDDQ terminals only.

4. Input terminals only.

5. I/O terminals only.

6. This is a steady-state DC parameter that applies after the power supplies have
ramped up. Power supply sequencing is not necessary; however, the voltage
on any input or I/O pin cannot exceed VDDQ during power supply ramp up.

7. TA is the "instant on" case temperature.

Po we r Di s si p atio n 2.0 W
DC Output Curre nt 50 mA

-0.5 to V

-0 to +7 0

-40 to + 85

-55 to +125

-55 to +125

DDQ

+0.5 V

Recommended DC Operating
Conditions

C

DD

V

C

C

C

NOTES:

1. VIH (max) = VDDQ + 1.0V for pulse width less than tCYC/2, once per cycle.

2. VIL (min) = -1.0V for pulse width less than tCYC/2, once per cycle.

Core Supply Voltage 3.135 3.3 3.465 V

DDQ

V

I/O Sup pl y Vo ltage 3.135 3.3 3.465 V

SS

V

Supply Voltage 0 0 0 V
VIHInput High Voltage - Inputs 2.0
VIHI n pu t High Voltage - I / O 2.0
VILInput Low Voltage -0. 3

____

____

(2)

____

DD

V

+0.3 V

DDQ

V

+0.3

0.8 V

(1)

5301 tbl 06

V

100 Pin TQFP Capacitance

(TA = +25°C, f = 1.0MHz)

Symbol P arameter

Inp ut Cap ac i tanc e VIN = 3dV 5 p F

C

IN

I/O Cap ac ita nce V

C

I/O

Conditions Max. Unit

= 3dV 7 p F

OUT

5301 tbl 07

165 fBGA Capacitance

(TA = +25°C, f = 1.0MHz)

Symbo l Para me t e r

Inp ut Cap a ci tanc e VIN = 3dV 7 pF

C

IN

I/O Cap aci tance V

C

I/O

NOTE:

1. This parameter is guaranteed by device characterization, but not production tested.

Conditions Max . Unit

= 3dV 7 pF

OUT

5301 tb l 07b

6.42

4

119 BGA Capacitance

(TA = +25°C, f = 1.0MHz)

Symbol Parame te r

Input Capacitance VIN = 3dV 7 p F

C

IN

I/O Cap acitanc e V

C

I/O

Con dit ion s Max. Un it

= 3dV 7 p F

OUT

5301 tbl 07a

IDT71V35761, IDT71V35781, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges

Pin Configuration  128K x 36

C

4

3

2

0

7

A6A

10099989796959493929190 8786858483828189 88

W

S

E

B

C

C

1

1

D

S

LK

D

W

W

W

B

B

B

S

S
C

C

V

V

E

W

W
B

G

P

S

S

V

D

E

A

O

8A9

D

D

A

A

A

I/O
I/O
I/O

DDQ

V

V
I/O
I/O
I/O
I/O

V

DDQ

V

I/O
I/O

VDD/NC

V

V
I/O
I/O

DDQ

V

V
I/O
I/O
I/O
I/O

V

DDQ

V

I/O
I/O
I/O

DD

NC

1

P3

2

16

3

17

4
5

SS

6

18

7

19

8

20

9

21

10

SS

11
12

22

13

23

(1)

14
15
16
17

SS

18

24

19

25

20
21

SS

22

26

23

27

24

28

25

29

26

SS

27
28

30

29

31

30

P4

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

O
LB

5

A0A1A2A3A4A

S

D

C

C

S

N

N

V

C

C

D

N

N

V

80
79
78
77
76
75
74
73
72

71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

14A13A12A11A10

16

A

A15A

I/O

I/O

I/O
V
V
I/O
I/O
I/O
I/O
V
V
I/O
I/O
V

NC
V

ZZ
I/O
I/O
V
V
I/O
I/O
I/O
I/O
V
V
I/O
I/O

I/O

5301drw 02

15
14

DDQ

SS

13
12
11

10
SS
DDQ

9

8
SS

DD

(2)

DDQ
SS

5

4

3

2
SS
DDQ

P2

7
6

1

,

0
P1

100 TQFP

Top View

NOTES:

1. Pin 14 can either be directly connected to VDD, or connected to an input voltage ≥ VIH, or left unconnected.

2. Pin 64 can be left unconnected and the device will always remain in active mode.

6.42

5

IDT71V35761, IDT71V35781, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges

Pin Configuration  256K x 18

C

2

0

7

A6A

10099989796959493929190 8786858483828189 88

C

S

E

N

C

C

1

1

D

S

C

W

W

S

B

N

B

C

LK

D

S

C

V

V

E

W

W
B

G

P

S

V

S

E

D
A

O

8A9

D

D

A

A

A

DDQ

V

V

I/O
I/O
V

DDQ

V

I/O
I/O

VDD/NC

V

V
I/O
I/O

DDQ

V

V
I/O
I/O
I/O

V

DDQ

V

NC
NC
NC

NC
NC

NC

NC

NC
NC
NC

1
2
3
4
5

SS

6
7
8

8

9

9

10

SS

11
12

10

13

11

(1)

14
15

DD

16
17

SS

18

12

19

13

20
21

SS

22

14

23

15

24

P2

25
26

SS

27
28
29
30

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

O
LB

5

A0A1A2A3A4A

S

D

C

C

C

S

N

N

V

C

D

N

N

V

80

10

A

79

NC

78

NC

77

DDQ

V

76

SS

V

75

NC

74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

15A14A13A12A11

17

A

A16A

I/O
I/O
I/O
V
V
I/O
I/O
V

NC
V

ZZ
I/O
I/O
V
V
I/O
I/O
NC
NC
V
V
NC
NC

NC

5301 drw 03

SS
DDQ

SS

DD

DDQ
SS

SS
DDQ

P1
7
6

5
4

(2)

3
2

1
0

,

100 TQFP

Top View

NOTES:

1. Pin 14 can either be directly connected to VDD, or connected to an input voltage ≥ VIH, or left unconnected.

2. Pin 64 can be left unconnected and the device will always remain in active mode.

6.42

6

IDT71V35761, IDT71V35781, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges

Pin Configuration  128K x 36, 119 BGA

1234567

DDQ

V

A

NC CS

B

NC

C A

16

I/O

D

17

I/O

E

DDQ

V

F

20

I/O

G

22

I/O

H

DDQ

V

J

24

I/O

K

25

I/O

L

DDQ

M V

29

I/O

N

31

I/O

P

NC A

R

NC NC A

T

DDQ

U V

A

I/O
I/O
I/O
I/O
I/O

DD

V
I/O
I/O
I/O
I/O
I/O

NC/TMS

6

0

7

P3

18

19

21

23

26

27

28

30

P4

5

(2)

4

A

3

A

2

A

SS

V

SS

V

SS

V

BW

SS

V
NC V

SS

V

BW

SS

V

SS

V

SS

V

LBO

10

NC/TDI

3

4

(2)

ADSP
ADSC

DD

V

NC V
CE

OE
ADV BW
GW

DD

CLK V

NC

BWE

1

A

0

A

DD

V

11

A

NC/TCK

(2)

A
A

A

SS

SS

V

SS

V

SS

V
NC V

SS

BW

SS

V

SS

V

SS

V

DD

V

A

NC/TDO

8

9

12

2

1

/NC

14

(1)

(2)

16

A

1

CS

15

A

P2

I/O

13

I/O

12

I/O

11

I/O

9

I/O

DD

6

I/O

4

I/O

3

I/O

2

I/O

0

I/O

13

A
NC

NC/TRST

(2,4)

DDQ

V

NC
NC

15

I/O

14

I/O

DDQ

V

10

I/O

8

I/O

DDQ

V

7

I/O

5

I/O

DDQ

V

1

I/O

P1

I/O

NC

(3)

ZZ

DDQ

V

5301 drw 04

,

Top View

Pin Configuration  256K x 18, 119 BGA

1234567

DDQ

V

A

NC CS

B

NC

C

8

I/O

D

NC I/O

E

DDQ

V

F

NC I/O

G

11

I/O

H

DDQ

V

J

NC I/O

K

13

I/O

L

DDQ

V

M

15

I/O

N

NC I/O

P

NC A

R

NC A

T

DDQ

V

U

NOTES:

1. R5 can either be directly connected to VDD, or connected to an input voltage ≥ VIH, or left unconnected.

2. These pins are NC for the "S" version or the JTAG signal listed for the "SA" version. Note: If NC, these pins can either be tied to VSS, VDD or left floating.

3. T7 can be left unconnected and the device will always remain in active mode.

4. TRST is offered as an optional JTAG Reset if required in the application. If not needed, can be left floating and will internally be pulled to VDD.

6

A

0

7

A

NC V

9

NC V

10

NC V

DD

V

12

NC NC

14

I/O

NC V

P2

5

10

NC/TMS

(2)

4

A

3

A

2

A

SS

SS

V

SS

BW

SS

NC V

SS

V

SS

V

SS

V

SS

SS

V
LBO

15

A

NC/TDI

2

(2)

ADSP

ADSC

DD

V

A
A

A

NC V

CE
OE

ADV

GW

V
V
V
V

DD

NC V

CLK V

BW

BWE

A
A

V

V

1

V

0

V

DD

V

DD

NC A

(2)

NC/TCK

NC/TDO

Top View

8

9

13

SS

SS

SS

SS

SS

SS

SS

SS

SS

/NC

14

1

(1)

(2)

16

A

1

CS

17

A

7

I/O
NC I/O

5

I/O
NC I/O

3

I/O

DD

NC I/O

1

I/O
NC V

0

I/O
NC I/O

12

A

11

A

NC/TRST

(2,4)

DDQ

V

NC
NC
NC

6

DDQ

V

4

NC

DDQ

V

2

NC

DDQ

NC

P1

NC

(3)

ZZ

DDQ

V

5301 drw 05

,

6.42

7

IDT71V35761, IDT71V35781, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

7CE1BW3BW2CS1

8

6CS0BW4BW1

9

DDQVSSVSSVSSVSSVSSVDDQ

P2

16VDDQVDDVSSVSSVSSVDDVDDQ

15

14

18VDDQVDDVSSVSSVSSVDDVDDQ

13

12

20VDDQVDDVSSVSSVSSVDDVDDQ

11

10

22VDDQVDDVSSVSSVSSVDDVDDQ

9

8

DD

DDVSSVSSVSSVDD

24VDDQVDDVSSVSSVSSVDDVDDQ

7

6

26VDDQVDDVSSVSSVSSVDDVDDQ

5

4

28VDDQVDDVSSVSSVSSVDDVDDQ

3

2

30VDDQVDDVSSVSSVSSVDDVDDQ

1

0

DDQVSS

NC/

SSVDDQ

P1

5A2

1

10A13A14

4A3

0

11A12A15A16

5301 tbl 17

7CE1BW2

1

8

0

1

9

DDQVSSVSSVSSVSSVSSVDDQ

P1

DDQVDDVSSVSSVSSVDDVDDQ

7

DDQVDDVSSVSSVSSVDDVDDQ

6

DDQVDDVSSVSSVSSVDDVDDQ

5

DDQVDDVSSVSSVSSVDDVDDQ

4

DD

DDVSSVSSVSSVDD

DDQVDDVSSVSSVSSVDDVDDQ

3

DDQVDDVSSVSSVSSVDDVDDQ

2

DDQVDDVSSVSSVSSVDDVDDQ

1

DDQVDDVSSVSSVSSVDDVDDQ

0

P2

DDQVSS

NC/

SSVDDQ

5A2

1

11A14A15

4A3

0

12A13A16A17

5301 tbl 17a

3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges

Pin Configuration  128K x 36, 165 fBGA

1234567891011

ANC

(4)

A
BNC A
CI/OP3NC V
DI/O17I/O
EI/O19I/O

FI/O21I/O
GI/O23I/O
HV

(1)

NC NC V

JI/O25I/O
KI/O27I/O

LI/O29I/O
MI/O31I/O
NI/OP4NC V

NC

(4)

(4)

PNCNC
R

LBO

BWE ADSC AD V

CLK

GW OE ADSP

NC NC ZZ

NC

(4)

A
A

NC V
NC/TDO
NC/TCK

(2)

A

(2)

A

(2,5)

TRST

A
A

NC/TDI

NC/TMS

(2)

(2)

A
A

NC I/O
I/O
I/O

I/O

I/O

I/O
I/O
I/O
I/O

NC I/O

I/O
I/O
I/O

NC

I/O

I/O
I/O
I/O
I/O

NC

NC

(4)

(3)

(4)

Pin Configuration  256K x 18, 165 fBGA

1234567891011

ANC

(4)

BNC A6CS
CNC NCV
DNC I/O8V
ENC I/O9V
FNCI/O10V

GNC I/O11V

HV

(1)

JI/O12NC V
KI/O13NC V
LI/O14NC V

MI/O15NC V

NI/O
PNC NC

R

LBO

A

NC NC V

NC V

NC

(4)

(4)

A
A

NC

NC

BW

TRST

NC/TDI

NC/TMS

CS

CLK

(2,5)

NC

(2)

A

(2)

A

BWE ADSC ADV

GW OE ADSP

(4)

NC V
NC/TDO
NC/TCK

(2)

(2)

A
A

NC

A

10

(4)

NC I/O
NC I/O
NC I/O
NC I/O
NC I/O

NC NC ZZ

I/O
I/O

I/O

I/O

(3)

NC
NC
NC
NC

NC NC

A

NC

(4)

A

NOTES:

1. H1 can either be directly connected to VDD, or connected to an input voltage ≥ VIH, or left unconnected.

2. These pins are NC for the "S" version or the JTAG signal listed for the "SA" version. Note: If NC, these pins can either be tied to VSS, VDD or left floating.

3. H11 can be left unconnected and the device will always remain in active mode.

4. Pins P11, N6, B11, A1, R2 and P2 are reserved for 9M, 18M, 36M, 72M, 144M and 288M respectively.

5. TRST is offered as an optional JTAG Reset if required in the application. If not needed, can be left floating and will internally be pulled to VDD.

6.42

8

IDT71V35761, IDT71V35781, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

Symbol

Parameter

Test Conditions

Min.

Max.

Unit

Symbol

Parameter

Test Conditions

200MHz

183MHz

166 MHz

Unit

Com'l

Com'l

Ind

Com'l

Ind

3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges

DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VDD = 3.3V ± 5%)

|ILI| Input Le ak ag e Curren t VDD = Max., VIN = 0V to V

LZZ

|I

LO

|I
V
V

NOTE:

1. The LBO, TMS, TDI, TCK & TRST pins will be internally pulled to VDD and the ZZ pin will be internally pulled to VSS if they are not actively driven in the application.

ZZ, LBO and J TAG Input Le akag e Current

|

| Output Le akag e Current V

OL

Output Low Vo ltage IOL = +8mA, VDD = Min.

OH

Output High Vo ltage IOH = -8mA, VDD = Mi n. 2.4

(1)

VDD = Max., VIN = 0V to V

OUT

= 0V to V

DDQ

DD

DD

, Device Deselected

___

___

___

___

5µA

30 µA

5µA

0.4 V

___

V

5301 tbl 08

DC Electrical Characteristics Over the Operating

MAX

MAX

(2,3)

(1)

(2)

360 340 350 320 330 mA

30 30 35 30 35 mA

(2,3)

130 120 130 110 120 mA

30 30 35 30 35 mA

5301 tbl 0 9

Temperature and Supply Voltage Range

Operating Power Supply

DD

I

Current

SB1

I

CMOS Standby Power
Supply Current

SB2

I

Cloc k Running Po we r
Supply Current

Full Sleep Mode Supply

ZZ

I

Current

NOTES:

1. All values are maximum guaranteed values.

2. At f = fMAX, inputs are cycling at the maximum frequency of read cycles of 1/tCYC while ADSC = LOW; f=0 means no input lines are changing.

3. For I/Os VHD = VDDQ - 0.2V, VLD = 0.2V. For other inputs VHD = VDD - 0.2V, VLD = 0.2V.

Device Selected, Outputs Open, VDD = Max.,

DDQ

V

= Max., VIN > VIH or < VIL, f = f

Device Deselected, Outputs Open, VDD = Max.,

DDQ

V

= Max., VIN > VHD or < VLD, f = 0

Device Deselected, Outputs Open, VDD = Max.,

DDQ

V

= Max., VIN > VHD or < VLD, f = f

HD, VDD

ZZ >

V

= Max.

(VDDQ = 3.3V)

Inp ut P ul s e Le v e ls
Input Rise/ Fall Times
Inp ut Ti mi ng Re fe re n c e Le v e ls
Output Timi ng Re fere nc e Le ve ls
AC Test Lo ad

0 to 3V

2ns

1.5V

1.5V

See Figure 1

5301 t b l 10

6.42

9

AC Test LoadAC Test Conditions

∆tCD

(Typical,ns)

Figure 2. Lumped Capacitive Load, Typical Derating

50

I/O

0

Z

=50Ω

Figure 1. AC Test Load

6
5
4
3
2
1

20 30 50 100 200

80

Capacitance (pF)

V

Ω

DDQ

/2

5301 drw 06

5301 drw 07

,

,

IDT71V35761, IDT71V35781, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

Operation

Address

UsedCECS

0CS1

(2)

CLK

I/O

Des elec ted Cycle, P owe r Do wn

NoneHXXXLXXXXX-HI-Z

Des elec ted Cycle, P owe r Do wn

NoneLXHLXXXXXX-HI-Z

Des elec ted Cycle, P owe r Do wn

NoneLLXLXXXXXX-HI-Z

Des elec ted Cycle, P owe r Do wn

NoneLXHXLXXXXX -HI-Z

Des elec ted Cycle, P owe r Do wn

NoneLLXXLXXXXX-HI-Z

Read Cycle , Beg in Burst

External

LHLLXXXXXL-

D

Read Cycle , Beg in Burst

External

LHLLXXXXXH-

HI-Z

Read Cycle , Beg in Burst

External

LHLHLXHHXL-

D

Read Cycle , Beg in Burst

External

LHLHLXHLHL-

D

Read Cycle , Beg in Burst

External

LHLHLXHLHH-

HI-Z

Write Cycle, Begin Burst

External

LHLHLXHLLX-

DINWrite Cycle, Begin Burst

External

LHLHLXLXXX-

DINRead Cycle , Continue B urst

NextXXXHHLHHXL-D

Read Cycle , Continue B urst

NextXXXHHLHHXH-HI-Z

Read Cycle , Continue B urst

NextXXXHHLHXHL-D

Read Cycle , Continue B urst

NextXXXHHLHXHH-HI-Z

Read Cycle , Continue B urst

NextHXXXHLHHXL-D

Read Cycle , Continue B urst

NextHXXXHLHHXH-HI-Z

Read Cycle , Continue B urst

NextHXXXHLHXHL-D

Read Cycle , Continue B urst

NextHXXXHLHXHH-HI-Z

Write Cy cle, Co ntinue B urst

NextXXXHHLHLLX-DINWrite Cy cle, Co ntinue B urst

NextXXXHHLLXXX-DINWrite Cy cle, Co ntinue B urst

NextHXXXHLHLLX-DINWrite Cy cle, Co ntinue B urst

NextHXXXHLLXXX-DINRead Cycle, Suspend Burst

Current

XXXHHHHHXL-

D

Read Cycle, Suspend Burst

Current

XXXHHHHHXH-

HI-Z

Read Cycle, Suspend Burst

Current

XXXHHHHXHL-

D

Read Cycle, Suspend Burst

Current

XXXHHHHXHH-

HI-Z

Read Cycle, Suspend Burst

Current

HXXXHHHHXL-

D

Read Cycle, Suspend Burst

Current

HXXXHHHHXH-

HI-Z

Read Cycle, Suspend Burst

Current

HXXXHHHXHL-

D

Read Cycle, Suspend Burst

Current

HXXXHHHXHH-

HI-Z

Write Cycle, Suspend Burst

Current

XXXHHHHLLX-

DINWrite Cycle, Suspend Burst

Current

XXXHHHLXXX-

DINWrite Cycle, Suspend Burst

Current

HXXXHHHLLX-

DINWrite Cycle, Suspend Burst

Current

HXXXHHLXXX-

D

3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges

Synchronous Truth Table

(1,3)

ADSP AD SC ADV GW BWE BWxOE

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

NOTES:

1. L = VIL, H = VIH, X = Don’t Care.

2. OE is an asynchronous input.

3. ZZ = low for this table.

6.42

10

IN

5301tbl 11

IDT71V35761, IDT71V35781, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

Operation

1BW2BW3BW4

Sequence 1

Sequence 2

Sequence 3

Sequence 4

A1A0A1A0A1A0A1

A0

Sequence 1

Sequence 2

Sequence 3

Sequence 4

A1A0A1A0A1A0A1

A0

Operation

(2)

ZZ

I/O Status

Power

3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges

Synchronous Write Function Truth Table

(1, 2)

GW BWE BW

Read HHXXXX

Read HLHHHH
Write all Bytes LXXXXX
Write all BytesHLLLLL
Write By te 1
Write By te 2
Write By te 3
Write By te 4

NOTES:

1. L = VIL, H = VIH, X = Don’t Care.

2. BW3 and BW4 are not applicable for the IDT71V35781.

3. Multiple bytes may be selected during the same cycle.

(3)

(3)

(3)

(3)

HLLHHH
HLHLHH
HLHHLH
HLHHHL

5301 tbl 12

Asynchronous Truth Table

(1)

OE

Re ad L L Data Ou t Ac tiv e
Re ad H L Hig h-Z Ac tiv e

Write X L Hig h-Z – Data In Ac ti ve

Deselected X L High-Z Standby

Sleep Mode X H High-Z Sleep

NOTES:

1. L = VIL, H = VIH, X = Don’t Care.

2. Synchronous function pins must be biased appropriately to satisfy operation requirements.

Interleaved Burst Sequence Table (LBO=VDD)

First Address 0 0 0 1 1 0 1 1
Second Address 0 1 0 0 1 1 1 0
Third Address 1 0 1 1 0 0 0 1

Fourth Address

NOTE:

1. Upon completion of the Burst sequence the counter wraps around to its initial state.

(1)

11100100

5301 tbl 13

5301 tbl 14

Linear Burst Sequence Table (LBO=VSS)

First Address 0 0 0 1 1 0 1 1
Second Address 0 1 1 0 1 1 0 0
Third Address 1 0 1 1 0 0 0 1

Fourth Address

NOTE:

1. Upon completion of the Burst sequence the counter wraps around to its initial state.

(1)

11000110

6.42

11

5301 tbl 15

IDT71V35761, IDT71V35781, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

200MHz

(5)

166MHz

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Unit

Output Parameters

Set Up Ti m es

Ho ld T ime s

Sl ee p Mo de an d Conf ig u rat i on Param eter s

3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges

AC Electrical Characteristics

(VDD = 3.3V ±5%, Commercial and Industrial Temperature Ranges)

183MHz

CYC

t
t
t

t
t

t
t

t
t
t

CH

CL

CD

CDC

CLZ

CHZ

OE

OLZ

OHZ

(1)

(1)

(2)

(2)

(2)

(2)

Clo c k Cy c le Time 5 — 5.5 — 6 — ns
Clock High Pulse Width 2 — 2.2 — 2.4 — ns

Clock Low Pulse Width 2 — 2.2 — 2.4 — ns

Clock High to Valid Data — 3.1 — 3.3 — 3.5 ns
Clo ck Hig h to Data Chang e 1.0 — 1.0 — 1.0 — ns
Clo c k H ig h to Ou tp ut A c ti v e 0 — 0 — 0 — n s

Clo ck Hig h to Data Hig h-Z 1.5 3. 1 1. 5 3.3 1. 5 3.5 ns
Output Enable Access Time — 3.1 — 3.3 — 3.5 ns
Outpu t Enabl e Lo w to Outp ut Ac tive 0 — 0 — 0 — ns

Output Enable High to Output High-Z — 3.1 — 3.3 — 3.5 ns

SA

t

SS

t

SD

t

SW

t

SAV

t

SC

t

HA

t

HS

t

HD

t

HW

t

HAV

t

HC

t

ZZPW

t

ZZR

t

CFG

t

(3)

(4)

Ad d res s S etup Time 1.2 — 1.5 — 1.5 — ns
Ad d res s Status Se tup Time 1.2 — 1.5 — 1.5 — ns
Data In Setup Time 1.2 — 1.5 — 1.5 — ns
Write S e tup Time 1.2 — 1.5 — 1.5 — ns
Ad d res s Ad v anc e Se tup Time 1.2 — 1.5 — 1.5 — ns
Chip Enab l e/ Se l e ct S etup Time 1.2 — 1.5 — 1.5 — ns

Ad d res s Ho ld Time 0.4 — 0.5 — 0.5 — ns
Ad d res s Status Hol d Time 0.4 — 0. 5 — 0. 5 — ns
Data In Hold Time 0.4 — 0.5 — 0.5 — ns
Write Hol d Time 0.4 — 0. 5 — 0.5 — ns
Ad d re ss Ad v anc e Hol d Time 0.4 — 0.5 — 0.5 — ns
Chip Enab l e/ Se l e ct Ho ld Time 0. 4 — 0. 5 — 0. 5 — ns

ZZ Pulse Width 100 — 100 — 100 — ns
ZZ Rec o ve ry Time 100 — 100 — 100 — ns

Config ura tio n Se t-up Time 20 — 22 — 24 — ns

NOTES:

1. Measured as HIGH above VIH and LOW below VIL.

2. Transition is measured ±200mV from steady-state.

3. Device must be deselected when powered-up from sleep mode.

4. tCFG is the minimum time required to configure the device based on the LBO input. LBO is a static input and must not change during normal operation.

5. Commercial temperature range only.

53 01 tbl 16

6.42

12

IDT71V35761, IDT71V35781, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges

Timing Waveform of Pipelined Read Cycle

suspends
H
IG

H

V
D
A

(1,2)

08
drw

5301

,

y)
2(A

O

Z
H
C

t

y)
1(A

O

around

y)

initial state)

raps

4(A

its

O

to

urst w
(B

ead
R

burst

y)
3(A

O

ipelined

urst P
B

y)
2(A

W
H

t

V
A
H

t

V
A
S

L
C

t

C
Y
C

t

H
C

t

S
H

t

S
S

t

(1)

W
S

t

y
A

A
H

t

x
A

A
S

t

C
H

t

C
S

t

t

D
C

t

E
O

t

O

C
D

y)

C

t

1(A
O

LZ
C

t

Z
H
O

t

x)
1(A

O

ead
R

ipelined

LZ
O

t

P

utput

isabled

O

D

0 timing transitions are identical but inverted to the CE and CS1 signals. For example, when CE and CS1 are LOW on this waveform, CS0 is HIGH.

LK
C

P
S
D
A

S

S

E

D

R

A

D
D
A

S

C

x
E,BW

,BW
W

1

S
,C

E
C

V

3)
ote

(N

E

D

O

A

T
U
O

TA

A
D

of the base address Ay, etc. where A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input.

NOTES:

1. O1 (Ax) represents the first output from the external address Ax. O1 (Ay) represents the first output from the external address Ay; O2 (Ay) represents the next output data in the burst sequence

2. ZZ input is LOW and LBO is Don't Care for this cycle.

3. CS

6.42

13

IDT71V35761, IDT71V35781, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges

Timing Waveform of Combined Pipelined Read and Write Cycles

09
drw

z)
3(A

O

5301

,

(1,2,3)

z)
2(A

O

C
D

z)

z)

C

t

1(A

1(A
O

O

LZ
O

t

z
A

W
H

t

L
C

t

C
Y
C

t

W
S

y

t

H
C

t

A

D
H

t

D
S

t

y)
I1(A

Z

x)

H
O

t

1(A
O

ead

urstR
B

ipelined
P

D
C

t

rite
W

ipelined
P

LK
C

E
O

t

D

LZ

C

t

C

t

x

(2)

S
H

t

S
S

t

P
S
D
A

A

A

A

H

t

S

t

S
S
E
R
D
D
A

W
G

V
D
A

E
O

6.42

14

IN

TA
A
D

T
U
O

TA
A
D

ead
R

ingle
S

NOTES:

the next output data in the burst sequence of the base address Az, etc. where A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input.

1. Device is selected through entire cycle; CE and CS1 are LOW, CS0 is HIGH.

2. ZZ input is LOW and LBO is Don't Care for this cycle.

3. O1 (Ax) represents the first output from the external address Ax. I1 (Ay) represents the first input from the external address Ay; O1 (Az) represents the first output from the external address Az; O2 (Az) represents

IDT71V35761, IDT71V35781, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges

rite

(1,2,3)

10
drw

5301

,

Timing Waveform of Write Cycle No. 1 - GW Controlled

z)
I3(A

z)

D

I2(A

tH

W
H

t

W
S

t

z
A

V
A
H

t

z)
I1(A

y)

D
S

t

I4(A

y)

urst W
B

I3(A

y)

edge

rising

next clock
the

on
pled

sam
is

and

cycle
a

I2(A

burst)
V
A
S

t

suspends

H

IG

H

V

D

A

(

y)
I2(A

y)
I1(A

rite

urst W
B

L
C

t

C
Y
C

t

H
C

t

LK
C

S
H

t

S
S

t

P
S
D
A

A
H

A

t

S

t

C
S
D
A

initiates

y

P

A

S
D
A

hen
w

ignored

W is
G

x
A

C
H

t

C
S

t

S
S
E
R
D
D

W
G

1

S
,C

E
C

3)
ote

(N

V
D
A

6.42

15

E
O

Z
H
O

x)

t

I1(A

)
w

4(A
O

)
w

3(A
O

IN

ATA
D

T
U
O

TA

A
D

rite

ingle

W

S

ead

urst R
B

0 timing transitions are identical but inverted to the CE and CS1 signals. For example, when CE and CS1 are LOW on this waveform, CS0 is HIGH.

address Ay; I2 (Ay) represents the next input data in the burst sequence of the base address Ay, etc. where A0 and A1 are advancing for the four word burst in the sequence defined

NOTES:

by the state of the LBO input. In the case of input I2 (Ay) this data is valid for two cycles because ADV is high and has suspended the burst.

1. ZZ input is LOW, BWE is HIGH and LBO is Don't Care for this cycle.

2. O4 (Aw) represents the final output data in the burst sequence of the base address Aw. I1 (Ax) represents the first input from the external address Ax. I1 (Ay) represents the first input from the external

3. CS

IDT71V35761, IDT71V35781, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges

Timing Waveform of Write Cycle No. 2 - Byte Controlled

z)
I3(A

(1,2,3)

11
drw

5301

,

z)

D

I2(A

tH

W
H

t

z
A

W
H

t

W
S

t

W
S

t

V
A
S

t

z)
I1(A

D

y)

y)

S

t

I4(A

I4(A

rite

xtended

urst W

E

B

y)
I3(A

y)
I2(A

edge

rising

next clock
on

pled
sam

is
and

cycle
a

L
C

t

C
Y
C

t

H
C

t

S
H

t

S
S

t

A
H

A

t

S

t

P initiates

y

S

A

D
A

hen
w

ignored

E is
W

B

x
A

edge

rising

next clock
on

pled
sam

is
and

cycle
a

P initiates
S
D
A

hen
w

ignored
is

Wx
B

burst)

y)
I2(A

V suspends
D
A

(

rite

urst W
B

y)
I1(A

Z
H
O

x)

t

I1(A

)
w

4(A
O

C
H

t

C
S

t

)
w

3(A
O

rite

ingle

W

S

ead

urst
B

R

LK
C

1

P
S
D
A

C
S
D
A

S
S
E
R
D
D

E
W

B

x

S

W
B

,C
E
C

6.42

V

3)

D
A

ote
(N

E
O

IN

ATA
D

T
U
O

ATA
D

address Ay; I2 (Ay) represents the next input data in the burst sequence of the base address Ay, etc. where A0 and A1 are advancing for the four word burst in the sequence defined

NOTES:

by the state of the LBO input. In the case of input I2 (Ay) this data is valid for two cycles because ADV is high and has suspended the burst.

1. ZZ input is LOW, GW is HIGH and LBO is Don't Care for this cycle.

2. O4 (Aw) represents the final output data in the burst sequence of the base address Aw. I1 (Ax) represents the first input from the external address Ax. I1 (Ay) represents the first input from the external

3. CS0 timing transitions are identical but inverted to the CE and CS1 signals. For example, when CE and CS1 are LOW on this waveform, CS0 is HIGH.

16

IDT71V35761, IDT71V35781, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges

Timing Waveform of Sleep (ZZ) and Power-Down Modes

z
A

R
Z

tZ

(1,2,3)

12
drw

5301

,

ode
M

nooze
S

W
P
Z

L
C

t

C
Y
C

t

x)

H
C

t

A
H

t

x
A

S
H

t

S
S

t

A
S

t

C
H

t

C
S

t

E
O

t

1(A
O

LZ
O

t

tZ

ead
R

ingle
S

LK
C

P
S
D
A

C

S

S

S

D

E

A

R
D
D

1

S

W
G

,C
E
C

6.42

V

4)

D
A

ote
(N

E
O

17

T
U
O

A
T
A
D

Z

Z

NOTES:

1. Device must power up in deselected Mode

2. LBO is Don't Care for this cycle.

3. It is not necessary to retain the state of the input registers throughout the Power-down cycle.

4. CS0 timing transitions are identical but inverted to the CE and CS1 signals. For example, when CE and CS1 are LOW on this waveform, CS0 is HIGH.

IDT71V35761, IDT71V35781, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges

Non-Burst Read Cycle Timing Waveform

CLK

ADSP

ADSC

ADDRESS

Av Aw Ax Ay Az

GW,BWE,BWx

CE, CS

1

CS

0

OE

DATA

OUT

NOTES:

1. ZZ input is LOW, ADV is HIGH and LBO is Don't Care for this cycle.

2. (Ax) represents the data for address Ax, etc.

3. For read cycles, ADSP and ADSC function identically and are therefore interchangable.

(Av) (Aw) (Ax) (Ay)

Non-Burst Write Cycle Timing Waveform

CLK

5301 drw 14

,

ADSP

ADSC

ADDRESS

Av Aw Ax AzAy

GW

1

CE, CS

CS

0

DATA

IN

NOTES:

1. ZZ input is LOW, ADV and OE are HIGH, and LBO is Don't Care for this cycle.

2. (Ax) represents the data for address Ax, etc.

3. Although only GW writes are shown, the functionality of BWE and BWx together is the same as GW.

4. For write cycles, ADSP and ADSC have different limitations.

(Av) (Aw) (Ax) (Az)(Ay)

6.42

18

5301 drw 15

,

IDT71V35761, IDT71V35781, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

3

)

x

____

____

____

____

____

____

____

____

____

____

____

Regi ste r Na me

Bit Size

3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges

JTAG Interface Specification (SA Version only)

JCYC

t

t

t

JF

TCK

(1)

Device Inputs

/

TDI/TMS

(2)

Device Outputs

/

TDO

(

TRST

t

JRST

NOTES:

1. Device inputs = All device inputs except TDI, TMS and TRST.

2. Device outputs = All device outputs except TDO.

3. During power up, TRST could be driven low or not be used since the JTAG circuit resets automatically. TRST is an optional JTAG reset.

t

JCL

JR

t

JRSR

t

JCH

JDC

t

t

JS

JH

t

t

JCD

M5301 drw 01

JTAG AC Electrical
Characteristics

Symbol Parameter Min. Max. Units

JCYC

t

JCH

t

JCL

t

JR

t

JF

t

JRST

t

JRSR

t

JCD

t

JDC

t

JS

t

JH

t

NOTES:

1. Guaranteed by design.

2. AC Test Load (Fig. 1) on external output signals.

3. Refer to AC Test Conditions stated earlier in this document.

4. JTAG operations occur at one speed (10MHz). The base device may run at any speed specified in this datasheet.

JTAG Cloc k Inp ut Peri od 100

JTAG Clock HIGH 40

JTAG Clock Low 40

JTAG Clock Rise Time

JTAG Clock Fall Time

JTAG Reset Recovery 50

JTAG Data O utp ut

JTAG Data Ou tput Ho l d 0

(1,2,3,4)

JTAG Reset 50

JTAG Setup 25

JTAG Hold 25

(1)

5

(1)

5

20 ns

I5301 tbl 01

Scan Register Sizes

ns
ns
ns
ns
ns
ns
ns

ns
ns
ns

Instruc tio n (IR) 4
Bypass (BYR) 1
JTAG Id e ntifi cati o n (J IDR) 32
Boundary Scan (BSR) Note (1)

NOTE:

1. The Boundary Scan Descriptive Language (BSDL) file for this device is available
by contacting your local IDT sales representative.

I5301 tb l 03

6.42

19

IDT71V35761, IDT71V35781, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

I5301 tbl 02

(1)

(2)

(1)

I5301 tbl 04

3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges

JTAG Identification Register Definitions (SA Version only)

Instruction Field Value Description

Rev is io n Numb e r (31:28) 0x2 Re se rv ed fo r v ers io n numb e r.
IDT Devic e ID (27:12) 0x23C, 0x23E Defines IDT part numb e r 71V3576 1SA an d 7 1V35781S A, res p e ctiv e ly.
IDT JEDEC ID (11:1) 0x33 A llo ws un iq ue ide ntific atio n of de v ic e v e nd o r as IDT.
ID Register Indicator Bit (Bit 0) 1 Indicates the presence of an ID register.

Available JTAG Instructions

Instruction Description OPCODE

EXT EST

Forces contents of the boundary scan cells onto the de vice outputs
Places the boundary scan register (BSR) between TDI and TDO.

.

0000

Places the boundary scan register (BSR) between TDI and TDO.

SAMPLE/PRELOAD

SAMPLE allows data from device inputs

and o utp uts

in the b o und ary s can ce lls and shi fted s e riall y thro ugh TDO. P RELOA D

to be captured

0001

allows data to be input serially into the boundary scan cells via the TDI.

DEVICE_ID

HIGHZ

RESERVED
RES ERV E D 0101

Load s the J TAG ID reg is ter (JIDR) with the ve nd or ID co d e and p lac e s
the register between TDI and TDO.

Places the bypass register (BYR) between TDI and TDO. Forces all
device output drivers to a High-Z state.

Se ve ral c o mb inatio ns are re se rve d . Do no t use co d e s o the r than those

0010

0011

0100

id e ntifie d fo r EXTES T, SA MP LE/ PRE LOA D, DEV ICE_ID, HIGHZ, CLA MP,

RES ERV E D 0110

VALIDATE and BYPAS S i nstructio ns .

RES ERV E D 0111

CLAM P

RESERVED

Uses BYR. Forces contents of the boundary scan cells onto the device
outputs. Places the bypass register (BYR) between TDI and TDO.

1000

1001

RESERVED 1010

Same as above.

RESERVED 1011
RESERVED 1100

Automatically loaded into the instruction register whenever the TAP

VALIDATE

controller passes through the CAPTURE-IR state. The lower two bits '01'

1101

are mand ated by the IEEE std. 1149.1 sp ec ific ation.

RESERVED Same as above. 1110

BYPASS

NOTES:

1. Device outputs = All device outputs except TDO.

2. Device inputs = All device inputs except TDI, TMS, and TRST.

The BYPASS instruction is used to truncate the boundary scan register
as a single bit in length.

6.42

20

1111

IDT71V35761, IDT71V35781, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

O
O

y

3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges

Ordering Information

X

IDT XXX

Device

Type

S

PowerXSpeedXXPackage

X

Process/

Temperature

Range

Package Information

100-Pin Thin Quad Plastic Flatpack (TQFP)
119 Ball Grid Array (BGA)
165 Fine Pitch Ball Grid Array (fBGA)
Information available on the IDT website

Blank
I

PF**
BG
BQ

200*
183
166

S
SA

Blank
Y

71V35761
71V35781

*Commercialtemperature range onl
** JTAG(SA version)is not available with 100 pin TQFP package.

Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)

100-pin Plastic Thin Quad Flatpack (TQFP)
119 Ball Grid Array (BGA)
165 FinePitch Ball Grid Array (fBG A)

Frequency in Megahertz

Standard Power
Standard Power with JTAG interface

First Generation or current stepping
Second Generation die step

128K x 36 Pipelined Burst Synchronous SRAM with 3.3V I/
256K x 18 Pipelined Burst Synchronous SRAM with 3.3V I/

,

5301 drw 13

6.42

21

IDT71V35761, IDT71V35781, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges

Datasheet Document History

12/31/99 Created new datasheet from 71v3576 and 71v3578 datasheet.

Pg. 1, 4, 8, 11, 19 Added industrial temperature range offering from 166MHz and 183MHz

04/04/00 Pg. 18 Added 100 pin TQFP package Diagram Outline

Pg. 4 Add BGA capacitance table; Add industrial tempertaure to table; Insert note to Absolute Max

Rating and Recommended Operating Temperature tables

06/01/00 Add new package diagram outline, 13 x 15mm 165fBGA

Pg. 20 Correct BG119 Package Diagram Outline

07/15/00 Pg. 7 Add note reference to BG119 pinout

Pg. 8 Add DNU reference note to BQ165 pinout
Pg. 20 Update BG119 Package Diagram Outline Dimensions

10/25/00 Remove Preliminary status

Pg. 8 Add reference note to N5 on the BQ165 pinout, reserved for JTAG TRST
04/22/03 Pg.4 Updated 165 BGA table information from TBD to 7
06/30/03 Pg. 1,2,3,5-9 Updated datasheet with JTAG information

Pg. 5-8 Removed note for NC pins (38,39(PF package); L4, U4 (BG package) H2, N7 (BQ package))

requiring NC or connection to Vss.
Pg. 19,20 Added two pages of JTAG Specification, AC Electrical, Definitions and Instructions
Pg. 21-23 Removed old package information from the datasheet
Pg. 24 Updated ordering information with JTAG and Y stepping information. Added information

regarding packages available IDT website.

CORPORATE HEADQUARTERS for SALES: for Tech Support:

2975 Stender Way 800-345-7015 or 408-727-6116 [e-mail]
Santa Clara, CA 95054 fax: [phone], x4033

www.idt.com

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

6.42

22