Datasheet IDT71V321S55PF, IDT71V321L25J, IDT71V321L25PF, IDT71V321L35PF, IDT71V321L55J Datasheet (Integrated Device Technology Inc)

I/O

Control

Address
Decoder

MEMORY

ARRAY

ARBITRATION

and

INTERRUPT

LOGIC

Address
Decoder

I/O

Control

R/

W

L

CE

L

OE

L

BUSY

L

A

10L

A

0L

3026 drw 01

I/O0L- I/O

7L

CE

L

OE

L

R/

W

L

INT

L

BUSY

R

I/O0R-I/O

7R

A

10R

A

0R

INT

R

CE

R

OE

R

(2)

(1,2) (1,2)

(2)

R/

W

R

CE

R

OE

R

R/

W

R

11

11

Integrated Device Technology, Inc.

HIGH-SPEED 3.3V
2K x 8 DUAL-PORT
STATIC RAM WITH INTERRUPT

IDT71V321S/L

FEATURES:

• High-speed access
—Commercial: 25/35/55ns (max.)

• Low-power operation
—IDT71V321S

—Active: 250mW (typ.)
—Standby: 3.3mW (typ.)

—IDT71V321L

—Active: 250mW (typ.)
—Standby: 660µW (typ.)

• Two

INT

flags for port-to-port communications

• On-chip port arbitration logic

•

BUSY

output flag

• Fully asynchronous operation from either port

• Battery backup operation—2V data retention

• TTL-compatible, single 3.3V ±0.3V power supply

• Available in popular plastic packages

FUNCTIONAL BLOCK DIAGRAM

DESCRIPTION:

The IDT71V321 is a high-speed 2K x 8 Dual-Port Static
RAMs with internal interrupt logic for interprocessor com­munications. The IDT71V321 is designed to be used as a
stand-alone 8-bit Dual-Port RAM.

The device provides two independent ports with sepa­rate control, address, and I/O pins that permit independent,
asynchronous access for reads or writes to any location in
memory. An automatic power down feature, controlled by

CE

, permits the on chip circuitry of each port to enter a very

low standby power mode.

Fabricated using IDT's CMOS high-performance technol­ogy, these devices typically operate on only 250mW of
power. Low-power (L) versions offer battery backup data
retention capability, with each Dual-Port typically consum­ing 200µW from a 2V battery.

The IDT71V321 devices are packaged in a 52-pin PLCC
and a 64-pin TQFP (thin plastic quad flatpack).

NOTE:

1.

BUSY

are totem-pole
outputs.

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

and

INT

COMMERCIAL TEMPERATURE RANGE OCTOBER 1996

©1996 Integrated Device Technology, Inc. DSC-3026/2

For latest information contact IDT’s web site at www.idt.com or fax-on-demand at 408-492-8391.

6.34

1

IDT71V321S/L
HIGH-SPEED 3.3V 2K x 8 DUAL-PORT STATIC RAM WITH INTERRUPT COMMERCIAL TEMPERATURE RANGE

PIN CONFIGURATIONS

NDEX

A
A
A
A
A
A
A
A

A
I/O
I/O
I/O
I/O

1L
2L
3L
4L
5L
6L
7L
8L
9L
0L
1L
2L
3L

(1,2)

8
9
10
11
12
13
14
15
16
17
18
19

20

0L

A

4L

I/O

L

OE

5L

I/O

10L

A

6L

I/O

L

L

INT

BUSY

234567474849505152

IDT71V321

TOP VIEW

7L

NC

I/O

L

R/W

CELVCCCE

R

R

R/W

1

J52-1

PLCC

(3)

27262524232221 333231302928

0R1R2R3R4R6R5R

GND

I/O

I/O

I/O

I/O

R

R

INT

BUSY

I/O

I/O

46
45

44
43
42
41
40
39
38
37
36
35

34

10R

A

I/O

OE
A
A
A
A
A
A
A
A
A
A
NC
I/O

R
0R
1R
2R
3R
4R
5R
6R
7R
8R
9R

7R

3026 drw 02

INDEX

OE

L

A

0L

A

1L

A

2L

A

3L

A

4L

A

5L

A

6L

N/C

A

7L

A

8L

A

9L

N/C

I/O

0L

I/O

1L
2L

I/O

10
11
12

13
14
15

16

L

L

INT

W

BUSY

R/

10L

N/C

N/C

A

636261605958575655

64

1
2
3

4
5
6

7
8
9

18

19

17

4L

3L

N/C

I/O5LI/O6LI/O7LI/O

I/O

64-PIN TQFP

TOP VIEW

22

21

20

L

L

CC

CC

V

V

CE

IDT71V321

PN64-1

25

24

23

N/C

GND

GND

R

R

W

R/

54

R

INT

BUSY

52

53

10R

A

51

N/C

50

N/C

49

48

R

CE

47

46
45

44
43

42
41

(3)

40
39

38
37

36
35
34

33

31

30

28

27

26

29

I/O0RI/O1RI/O2RI/O3RI/O4RI/O

N/C

32

5R

OE

0R

A
A

1R

A

2R

A

3R

A

4R

A

5R

A

6R

N/C
A

7R

A

8R

A

9R

N/C
N/C
I/O
I/O

3026 drw 03

R

7R
6R

NOTES:

1. All Vcc pins must be connected to the power supply.

2. All GND pins must be connected to the ground supply.

3. This text does not indicate orientation of the actual part-marking.

6.34 2

IDT71V321S/L
HIGH-SPEED 3.3V 2K x 8 DUAL-PORT STATIC RAM WITH INTERRUPT COMMERCIAL TEMPERATURE RANGE

ABSOLUTE MAXIMUM RATINGS

(1)

Symbol Rating Commercial Unit

(2)

TERM

V

Terminal Voltage –0.5 to +4.6 V

with Respect to

GND

T

A Operating 0 to +70 °C

Temperature

T

BIAS Temperature –55 to +125 °C

Under Bias

T

STG Storage –55 to +125 °C

Temperature

I

OUT DC Output 50 mA

Current

NOTES:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT­INGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of the
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.

2. VTERM must not exceed Vcc + 0.5 for more than 25% of the cycle time
or 10ns maximum, and is limited to
+ 0.5V.

< 20mA for the period of VTERM > Vcc

3026 tbl 01

RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE

Ambient

Grade Temperature GND V

CC

Commercial 0°C to +70°C 0V 3.3V ± 0.3V

3026 tbl 02

RECOMMENDED
DC OPERATING CONDITIONS

Symbol Parameter Min. Typ. Max. Unit

V

CC Supply Voltage 3.0 3.3 3.6 V

GND Supply Voltage 0 0 0 V
V

IH Input High Voltage 2.0 — Vcc+0.3 V

V

IL Input Low Voltage –0.3

NOTES:

IL (min.) = -1.5V for pulse width less than 20ns.

1. V

TERM must not exceed VCC + 0.5V.

2. V

CAPACITANCE

(1)

(TA = +25°C, f = 1.0MHz) TQFP ONLY

Symbol Parameter Conditions

C

IN Input Capacitance VIN = 3dV 9 pF

C

OUT Output Capacitance VIN = 3dV 10 pF

NOTES:

1. This parameter is determined by device characterization but is not
production tested.

2. 3dv references the interpolated capacitance when the input and output

signals switch from 0V to 3V or from 3V to 0V.

(1)

— 0.8 V

(2)

3026 tbl 03

Max. Unit

3026 tbl 04

DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE

Symbol Parameter Test Conditions Min. Max. Min. Max. Unit

Ll| Input Leakage VCC = 3.6V — 10 — 5 µA

|l

|lLO| Output Leakage

VOL Output Low Voltage lOL = 4mA — 0.4 — 0.4 V

V

OH Output High Voltage lOH = -4mA 2.4 — 2.4 — V

NOTE:

1. At Vcc < 2.0V input leakages are undefined. Supply CurrentVIN > VCC -0.2V or < 0.2V

Current

(1)

VIN = 0V to VCCVIN = GND to VCC

CE

Current V

(l/O

0-l/O7) lOL= 16mA

= VIH, VOUT = 0V to VCC —10 — 5µA

CC = 3.6V, VOUT = GND to VCC

(VCC = 3.3V ± 0.3V)

lDT71V321LIDT71V321S

3026 tbl 05

6.34 3

IDT71V321S/L
HIGH-SPEED 3.3V 2K x 8 DUAL-PORT STATIC RAM WITH INTERRUPT COMMERCIAL TEMPERATURE RANGE

DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE

Test

Symbol Parameter Condition Version Typ.

CC Dynamic Operating

I

Current
(Both Ports Active) f = f

ISB1 Standby Current

(Both Ports — TTL
Level Inputs) f = f

ISB2 Standby Current

(One Port — TTL Active Port Outputs Open, L 30 75 30 70 30 60
Level Inputs) f = f

ISB3 Full Standby Current Both Ports

(Both Ports — All
CMOS Level Inputs) V

SB4 Full Standby Current

I

(One Port — All
CMOS Level Inputs)

NOTES: 3026 tbl 06

1. "X" in part numbers indicates power rating (S or L).

CC = 3.3V, TA = +25°C, and are not production tested. ICCDC = 70mA (Typ.)

2. V

3. At f = f

4. f = 0 means no address or control lines change.

5. Port "A" may be either left or right port. Port "B" is the opposite from port "A".

MAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1 / tRC, and using “AC Test Conditions”

of input levels of GND to 3V.

CE

= VIL, Outputs Open COM’L. S 75 150 75 145 75 135 mA

SEM

= V

IH L 75 120 75 115 75 105

(3)

MAX

CE

R = CEL = VIH COM’L. S 20 50 20 50 20 50 mA

SEM

R =

SEM

L = VIH L20 35 20 35 20 35

(3)

MAX

CE

"A" = VIL and CE"B" = VIH

(3)

MAX

SEM

R =

SEM

L = VIH

CE

L and COM’L. S 1.0 5.0 1.0 5.0 1.0 5.0 mA

CE

R > VCC - 0.2V L 0.2 3.0 0.2 3.0 0.2 3.0

IN > VCC - 0.2V or

V

IN < 0.2V, f = 0

SEM

R =

SEM

CE

"A" < 0.2V and COM’L. S 30 90 30 85 30 75 mA

CE

"B" > VCC - 0.2V

R =

SEM

V

SEM

IN > VCC - 0.2V or VIN < 0.2V

(4)

L > VCC - 0.2V

(5)

L > VCC - 0.2V

(5)

COM’L. S 30 105 30 100 30 90 mA

L30 75 30 70 30 60

Active Port Outputs Open

(3)

MAX

f = f

(1)

(VCC = 3.3V ± 0.3V)

71V321X25 71V321X35 71V321X55

(2)

Max. Typ.

(2)

Max. Typ.

(2)

Max. Unit

DATA RETENTION CHARACTERISTICS (L Version Only)

71V321L

(1)

Symbol Parameter Test Conditions Min. Typ.

DR VCC for Data Retention 2.0 — 0 V

V

CCDR Data Retention Current VCC = 2.0V,

I

(3)

t

CDR

Chip Deselect to Data VIN > VCC - 0.2V or VIN< 0.2V 0 — — ns

CE

> VCC - 0.2V COM'L. — 100 1500 µA

Retention Time

(3)

t

R

Operation Recovery tRC

(2)

—— ns

Time

NOTES:

1. VCC = 2V, TA = +25°C, and is not production tested.

RC = Read Cycle Time.

2. t

3. This parameter is guaranteed by device characterization but not production tested.

6.34 4

Max. Unit

3026 tbl 07

IDT71V321S/L

V

CC

CE

3.0V 3.0V

DATA RETENTION MODE

t

CDR

t

R

V

IH

V

IH

V

DR

VDR≥ 2.0V

3026 drw 04

HIGH-SPEED 3.3V 2K x 8 DUAL-PORT STATIC RAM WITH INTERRUPT COMMERCIAL TEMPERATURE RANGE

AC TEST CONDITIONS

Input Pulse Levels GND to 3.0V
Input Rise/Fall Times 5ns
Input Timing Reference Levels 1.5V
Output Reference Levels 1.5V
Output Load Figures 1and 2

3.3V

590Ω

INT

OUT

435Ω

30pF

DATA

BUSY

3026 tbl 08

DATA RETENTION WAVEFORM

3.3V

590Ω

DATA

OUT

435Ω

5pF

3026 drw 05

Figure 1. AC Output Test Load

Figure 2. Output Test Load

HZ, tLZ, tWZ and tOW)

(For t

* Including scope and jig.

AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE

71V321X25 71V321X35 71V321X55

Symbol Parameter Min. Max. Min. Max. Min. Max. Unit
READ CYCLE

RC Read Cycle Time 25 — 35 — 55 — ns

t

AA Address Access Time — 25 — 35 — 55 ns

t

ACE Chip Enable Access Time — 25 — 35 — 55 ns

t
t

AOE Output Enable Access Time — 12 — 20 — 25 ns

t

OH Output Hold from Address Change 3 — 3 — 3 — ns
LZ Output Low-Z Time

t
t

HZ Output High-Z Time

t

PU Chip Enable to Power Up Time
PD Chip Disable to Power Down Time

t

NOTES: 3026 tbl 09

1. Transition is measured ±200mV from Low or High-impedance voltage with Output Test Load (Figure 2).

2. This parameter is guaranteed by device characterization, but is not production tested.

3. "X" in part numbers indicates power rating (S or L).

(1, 2)

(1, 2)

(2)

(2)

0—0— 0—ns

—12—15 —30ns

0—0— 0—ns

—50—50 —50ns

(3)

6.34 5

IDT71V321S/L
HIGH-SPEED 3.3V 2K x 8 DUAL-PORT STATIC RAM WITH INTERRUPT COMMERCIAL TEMPERATURE RANGE

TIMING WAVEFORM OF READ CYCLE NO. 1, EITHER SIDE

t

RC

(1)

ADDRESS

t

t

AA

t

OH

OUT

DATA

BUSY

OUT

NOTES:

1. R/W = V

BDD delay is required only in case where the opposite is port is completing a write operation to same the address location. For simultanious read

2. t
operations

3. Start of valid data depends on which timing becomes effective last t

PREVIOUS DATA VALID

(2,3)

t

BDD

IH,

CE

= VIL, and is OE = VIL. Address is valid prior to the coincidental with CE transition Low.

BUSY

has no relationship to valid output data.

AOE, tACE, tAA, and tBDD.

TIMING WAVEFORM OF READ CYCLE NO. 2, EITHER SIDE

t

ACE

DATA VALID

(3)

OH

CE

t

AOE

(4)

(2)

t

HZ

3026 drw 06

OE

t

OUT

DATA

(1)

t

LZ

t

CC

I

CURRENT

I

NOTES:

1. Timing depends on which signal is asserted last, OE or CE.

2. Timing depends on which signal is deaserted first, OE or CE.

3. R/W = V

4. Start of valid data depends on which timing becomes effective last t

SS

IH, and the address is valid prior to other coincidental with

PU

50%

(1)

LZ

CE

transition Low.

AOE, tACE, tAA, and tBDD.

VALID DATA

t

PD

(2)

t

HZ

(4)

50%

3026 drw 07

6.34 6

IDT71V321S/L
HIGH-SPEED 3.3V 2K x 8 DUAL-PORT STATIC RAM WITH INTERRUPT COMMERCIAL TEMPERATURE RANGE

AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE

Symbol Parameter Min. Max. Min. Max. Min. Max. Unit
WRITE CYCLE

WC Write Cycle Time 25 — 35 — 55 — ns

t

EW Chip Enable to End-of-Write 20 — 30 — 40 — ns

t

AW Address Valid to End-of-Write 20 — 30 — 40 — ns

t

AS Address Set-up Time 0 — 0 — 0 — ns

t

WP Write Pulse Width 20 — 30 — 40 — ns

t

WR Write Recovery Time 0 — 0 — 0 — ns

t
t

DW Data Valid to End-of-Write 12 — 20 — 20 — ns

t

HZ Output High-Z Time
DH Data Hold Time

t
t

WZ Write Enable to Output in High-Z
OW Output Active from End-of-Write

t

NOTES: 3026 tbl 10

1. Transition is measured ±200mV from Low or High-impedance voltage with Output Test Load (Figure 2).

2. This parameter is guaranteed by device characterization, but is not production tested.

3. The specification for t
over voltage and temperature, the actual t

4. "X" in part numbers indicates power rating (S or L).

DH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values will vary

(1, 2)

(3)

(1, 2)

(1, 2)

DH will always be smaller than the actual tOW.

(4)

71V321X25 71V321X35 71V321X55

—12— 15— 30ns

0—0—0—ns

—15 — 15— 30ns

0—0—0—ns

6.34 7

IDT71V321S/L
HIGH-SPEED 3.3V 2K x 8 DUAL-PORT STATIC RAM WITH INTERRUPT COMMERCIAL TEMPERATURE RANGE

TIMING WAVEFORM OF WRITE CYCLE NO. 1,(R/

t

WC

ADDRESS

OE

t

AW

CE

(6)

t

AS

R/

W

(7)

t

WZ

DATA

DATA

OUT

IN

(4) (4)

TIMING WAVEFORM OF WRITE CYCLE NO. 2,

t

t

WP

WC

(2)

CECE

CE

CECE

WW

W

CONTROLLED TIMING)

WW

(3)

t

WR

t

DW

CONTROLLED TIMING

t

DH

t

OW

(1,5)

(1,5,8)

t

HZ

t

3026 drw 08

(7)

HZ

(7)

ADDRESS

t

AW

CE

(6)

t

AS

R/

W

DATA

IN

NOTES:

1. R/W or CE must be High during all address transitions.

2. A write occurs during the overlap (t

3. tWR is measured from the earlier of CE or R/W going High to the end of the write cycle.

4. During this period, the l/O pins are in the output state and input signals must not be applied.

5. If the CE Low transition occurs simultaneously with or after the R/W Low transition, the outputs remain in the High-impedance state.

6. Timing depends on which enable signal (CE or R/W) is asserted last.

7. This parameter is determined be device characterization, but is not production tested. Transition is measured +/- 500mV from steady state
with the Output Test Load (Figure 2).

8. If OE is Low during a R/W controlled write cycle, the write pulse width must be the larger of t
data to be placed on the bus for the required t
write pulse can be as short as the specified t

EW or tWP) of

WP.

CE

= VIL and R/W= VIL.

DW. If

OE

is High during a R/W controlled write cycle, this requirement does not apply and the

t

EW

(2)

t

DW

WP or (tWZ + tDW) to allow the I/O drivers to turn off

t

WR

(3)

t

DH

3026 drw 09

6.34 8

IDT71V321S/L
HIGH-SPEED 3.3V 2K x 8 DUAL-PORT STATIC RAM WITH INTERRUPT COMMERCIAL TEMPERATURE RANGE

AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE

71V321X25 71V321X35 71V321X55

Symbol Parameter Min. Max. Min. Max. Min. Max. Unit
BUSY TIMING (M/

BAA

t

BDA

t

BAC

t

BDC

t

APS Arbitration Priority Set-up Time

t

BDD

t

WDD Write Pulse to Delay Data

t

DDD Write Pulse to Delay Data

t

NOTES:

1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Write with Port-to-Port Read and

2. To ensure that the earlier of the two ports wins.

BDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual), or tDDD – tDW (actual).

3. t

4. To ensure that the write cycle is inhibited on port "B" during contention on port "A".

5. To ensure that a write cycle is completed on port "B" after contention on port "A".

6. "X" in part numbers indicates power rating (S or L).

SS

S

= V

IH)

SS

BUSY

Access Time from Address Match — 20 — 20 — 30 ns

BUSY

Disable Time from Address Not Matched — 20 — 20 — 30 ns

BUSY

Access Time from Chip Enable Low — 20 — 20 — 30 ns

BUSY

Disable Time from Chip Enable High — 20 — 20 — 30 ns

BUSY

Disable to Valid Data

(2)

(3)
(1)
(1)

5— 5— 5—ns
—30 —30 — 45ns
—50 —60 — 80ns
—35 —45 — 65ns

(6)

BUSY

".

3026 tbl 11

TIMING WAVE FORM OF WRITE WITH PORT-TO-PORT READ WITH

t

WC

ADDR

’A’

R/

W

’A’

DATA

IN’A’

(1)

t

APS

ADDR

’B’

BUSY

’B’

DATA

OUT’B’

NOTES:

1. To ensure that the earlier of the two ports wins.

L = CER = VIL

2.

CE

3.OE = VIL for the reading port.

4. All timing is the same for the left and right ports. Port 'A' may be either the left or right port. Port 'B' is opposite from port 'A'.

MATCH

t

WP

t

DW

VALID

MATCH

t

BDA

t

WDD

BUSY BUSY

BUSY

BUSY BUSY

t

DDD

(1,2,3)

t

DH

t

BDD

VALID

3026 drw 10

6.34 9

IDT71V321S/L
HIGH-SPEED 3.3V 2K x 8 DUAL-PORT STATIC RAM WITH INTERRUPT COMMERCIAL TEMPERATURE RANGE

t

WB

(3)

(2)

t

WP

(1)

t

WH

3026 drw 11

CECE

CE

TIMING

CECE

(1)

BUSY

BUSYBUSY

BUSY

BUSYBUSY

'B' goes High.

TIMING WAVEFORM OF WRITE WITH

R/

W

'A'

BUSY

'B'

R/

W

'B'

NOTES:

1. tWH must be met for

2.

BUSY

is asserted on port 'B' blocking R/

3. All timing is the same for the left and right ports. Port 'A' may be either the left or right port. Port 'B' is opposite from port 'A'.

BUSY

.

W

'B', until

TIMING WAVEFORM OF BUSY ARBITRATION CONTROLLED BY

ADDR

'A' AND 'B'

CE

CE

BUSY

'B'

(2)

t

APS

'A'

t

BAC

'A'

ADDRESSES MATCH

t

BDC

3026 drw 12

TIMING WAVEFORM OF BUSY ARBITRATION CONTROLLED BY ADDRESS MATCH TIMING

t

RC OR tWC

ADDR

ADDR

BUSY

'A'

(2)

t

APS

'B'

'B'

ADDRESSES MATCH

t

BAA

ADDRESSES DO NOT MATCH

t

BDA

(1)

NOTES:

1. All timing is the same for left and right ports. Port 'A' may be either left or right port. Port 'B' is the opposite from port 'A'.

2. If t

APS is not satisified, the

asserted.

BUSY

will be asserted on one side or the other, but there is no guarantee on which side

6.34 10

BUSY

3026 drw 13

will be

IDT71V321S/L
HIGH-SPEED 3.3V 2K x 8 DUAL-PORT STATIC RAM WITH INTERRUPT COMMERCIAL TEMPERATURE RANGE

AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE

71V321X25 71V321X35 71V321X55

Symbol Parameter Min. Max. Min. Max. Min. Max. Unit
INTERRUPT TIMING

AS Address Set-up Time 0 — 0 — 0 — ns

t

WR Write Recovery Time 0 — 0 — 0 — ns

t

INS Interrupt Set Time — 25 — 25 — 45 ns

t

INR Interrupt Reset Time — 25 — 25 — 45 ns

t

NOTE:

1. "X" in part numbers indicates power rating (S or L).

(1)

TIMING WAVEFORM OF INTERRUPT MODE

INTINT

INT

SETS

INTINT

t

WC

ADDR

'A'

INTERRUPT ADDRESS

(3)

t

AS

(2)

t

WR

(4)

3026 tbl 12

R/

W

'A'

(3)

t

INS

INT

'B'

INTINT

INT

CLEARS

INTINT

t

RC

ADDR

'B'

OE

'B'

INT

'A'

NOTES:.

1. All timing is the same for left and right ports. Port 'A' may be either left or right port. Port 'B' is the opposite from port 'A'.

2. See Interrupt Truth Table.

3. Timing depends on which enable signal (CE or R/W) is asserted last.

4. Timing depends on which enable signal (CE or R/W) is de-asserted first.

INTERRUPT CLEAR ADDRESS

(3)

t

AS

(3)

t

INR

3026 drw 14

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IDT71V321S/L
HIGH-SPEED 3.3V 2K x 8 DUAL-PORT STATIC RAM WITH INTERRUPT COMMERCIAL TEMPERATURE RANGE

TRUTH TABLES

TABLE I —
NON-CONTENTION READ/WRITE CONTROL

Left or Right Port

WW

CECE

R/

W

CE

WW

CECE

X H X Z Port Disabled and in Power-

XHX Z

L L X DATAIN Data on Port Written Into Memory
H L L DATAOUT Data in Memory Output on Port
H L H Z High-impedance Outputs

NOTES: 3026 tbl 13

1. A0L – A10L ≠ A0R – A10R.

2. If

BUSY

3. If

BUSY

4. 'H' = V

IL, data is not written.

= V

IL, data may not be valid, see tWDD and tDDD timing.

= V

IH, 'L' = VIL, 'X' = DON’T CARE, 'Z' = High-impedance.

TABLE II — INTERRUPT FLAG

WW

R/

LLX 7FF XXXX X L
X X X X X X L L 7FF H
XXX X L
X L L 7FE H

NOTES: 3026 tbl 14

1. Assumes

2. If

3. If

4. 'H' = HIGH, 'L' = LOW, 'X' = DON’T CARE.

CECE

W

CE

L

WW

CECE

BUSY

BUSY

L = VIL, then No Change.
R = VIL, then No Change.

BUSY

(1)

OEOE

OE

OEOE

D0–7 Function

Down Mode, I

CE

R = CEL = VIH, Power-Down

Mode, I

SB1 or ISB3

SB2 or ISB4

(1,4)

Left Port Right Port

OEOE

OE

L

L =

OEOE

BUSY

L A10L – A0L

R = VIH

INTINT

INT

INTINT

L R/

(3)

(2)

WW

W

WW

L L X 7FE X Set Left

X X X X X Reset Left

(4)

(2)

(3)

CECE

CE

R

CECE

OEOE

OE

R

R A10L – A0R

OEOE

INTINT

INT

R Function

INTINT

(2)

(3)

Set Right
Reset Right

INT

INT

INT

R Flag

INT

L Flag

L Flag

R Flag

TABLE III — ADDRESS BUSY ARBITRATION

Inputs Outputs

0L-A10L

A

CECE

CE

NOTES:

1. Pins

2. 'L' if the inputs to the opposite port were stable prior to the address and

CECE

CE

L

CECE

XX
HX
XH

LL

on the IDT71V321 are push-pull, not open-drain outputs.
enable inputs of this port. 'H' if the inputs to the opposite port became

stable after the address and enable inputs of this port. If t
either
can not be low simultaneously.

R A0R-A10R

CECE

BUSY

L and

BUSY

NO MATCH H H Normal

MATCH H H Normal
MATCH H H Normal
MATCH (2) (2) Write Inhibit

BUSY

R are both outputs for IDT71V321.

L or

BUSY

R = Low will result.

BUSYBUSY

BUSY

BUSYBUSY

(1)

L

BUSYBUSY

BUSY

BUSYBUSY

BUSY

(1)

R

L and

Function

3026 tbl 15

BUSY

X outputs

APS is not met,

BUSY

R outputs

(3)

6.34 12

IDT71V321S/L
HIGH-SPEED 3.3V 2K x 8 DUAL-PORT STATIC RAM WITH INTERRUPT COMMERCIAL TEMPERATURE RANGE

FUNCTIONAL DESCRIPTION

The IDT71V321 provides two ports with separate control,
address and I/O pins that permit independent access for
reads or writes to any location in memory. The IDT71V321
has an automatic power down feature controlled by CE. The

CE

controls on-chip power down circuitry that permits the
respective port to go into a standby mode when not selected
(CE = VIH). When a port is enabled, access to the entire
memory array is permitted.

INTERRUPTS

If the user chooses to use the interrupt function, a memory
location (mail box or message center) is assigned to each
port. The left port interrupt flag (
right port writes to memory location 7FE (HEX), where a write
is defined as the CE = R/W = VIL per the Truth Table. The left
port clears the interrupt by access address location 7FE
access when

CE

R = OER = VIL, R/

the right port interrupt flag (
port writes to memory location 7FF (HEX) and to clear the
interrupt flag (

INT

R), the right port must access the memory

location 7FF. The message (8 bits) at 7FE or 7FF is user­defined, since it is an addressable SRAM location. If the

INT

L) is asserted when the

W

is a "don't care". Likewise,

INT

R) is asserted when the left

interrupt function is not used, address locations 7FE and 7FF
are not used as mail boxes, but as part of the random access
memory. Refer to Truth Table for the interrupt operation.

BUSY LOGIC

Busy Logic provides a hardware indication that both ports
of the RAM have accessed the same location at the same
time. It also allows one of the two accesses to proceed and
signals the other side that the RAM is “Busy”. The Busy pin
can then be used to stall the access until the operation on the
other side is completed. If a write operation has been
attempted from the side that receives a busy indication, the
write signal is gated internally to prevent the write from
proceeding.

The use of busy logic is not required or desirable for all
applications. In some cases it may be useful to logically OR
the busy outputs together and use any busy indication as an
interrupt source to flag the event of an illegal or illogical
operation.

The Busy outputs on the IDT71V321 RAM are totem-pole
type outputs and do not require pull-up resistors to operate. If
these RAMs are being expanded in depth, then the Busy
indication for the resulting array does not require the use of an
external AND gate.

ORDERING INFORMATION

XXXXIDT

Device Type

A 999 A A

Power Speed Package

Process/

Temperature

Range

Blank

J
PF

25
35
55

L
S

Commercial (0°C to +70°C)

52-pin PLCC (J52-1)
64-pin TQFP (PN64-1)

Speed in nanoseconds

Low Power
Standard Power

71V321

16K (2K x 8-Bit) MASTER 3.3V
Dual-Port RAM w/ Interrupt

3026 drw 16

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