Datasheet IDT71V256SB12PZ, IDT71V256SB12Y, IDT71V256SB15PZ, IDT71V256SB15Y, IDT71V256SB20PZ Datasheet (Integrated Device Technology Inc)

Integrated Device Technology, Inc.

3.3V CMOS FAST SRAM
WITH 2.5V COMPATIBLE INPUTS
256K (32K x 8-BIT)

IDT71V256SB

FEATURES

• Ideal for high-performance processor secondary cache

• Fast access times:
— 12/15/20ns

• Inputs are 2.5V and LVTTL compatible: VIH = 1.8V

• Outputs are LVTTL compatible

• Low standby current (maximum):
— 2mA full standby

• Small packages for space-efficient layouts:
— 28-pin 300 mil SOJ
— 28-pin TSOP Type I

• Produced with advanced high-performance CMOS
technology

• Single 3.3V(±0.3V) power supply

FUNCTIONAL BLOCK DIAGRAM

DESCRIPTION

The IDT71V256SB is a 262,144-bit high-speed static RAM
organized as 32K x 8. The improved VIH (1.8V) makes the
inputs compatible with 2.5V logic levels. The IDT71V256SB
is otherwise identical to the IDT71V256SA.

The IDT71V256SB has outstanding low power character­istics while at the same time maintaining very high perfor­mance. Address access times of as fast as12 ns are ideal for
tag SRAM in secondary cache designs.

When power management logic puts the IDT71V256SB in
standby mode, its very low power characteristics contribute to
extended battery life. By taking CS HIGH, the SRAM will

automatically go to a low power standby mode and will remain
in standby as long as CS remains HIGH. Furthermore, under
full standby mode (CS at CMOS level, f=0), power consump­tion is guaranteed to always be less than 6.6mW and typically
will be much smaller.

The IDT71V256SB is packaged in 28-pin 300 mil SOJ and
28-pin300 mil TSOP Type I packaging.

A

I/O

I/O

A

14

0

0

7

CS

OE

WE

CONTROL

CIRCUIT

ADDRESS
DECODER

INPUT

DATA

CIRCUIT

262,144 BIT

MEMORY ARRAY

I/O CONTROL

V

CC

GND

3770 drw 01

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

COMMERCIAL TEMPERATURE RANGES JANUARY 1997

1997 Integrated Device Technology, Inc. 3770/1

7.??

1

IDT71V256SB

3.3V CMOS STATIC RAM WITH 2.5V COMPATIBLE INPUTS 256K (32K x 8-BIT) COMMERCIAL TEMPERATURE RANGE

PIN CONFIGURATIONS ABSOLUTE MAXIMUM RATINGS

A
A

A
A
A
A
A
A
A

A
I/O
I/O
I/O

GND

1

14

2

12

3

7

4

6

5

5

6

4
3
2
1
0
0
1
2

7
8
9
10
11
12
13
14

SO28-5

SOJ

28

V

CC

27

WE

26

A

13

25

8

A

24

A

9

23

A

11

22

OE

21

10

A

20

CS

19
18
17
16
15

7

I/O

6

I/O
I/O

5

I/O

4

I/O

3

3770 drw 02

TOP VIEW

22

OE

23

11

A

24

A

9

25

A

8

26

A

13

27

WE

28

V

CC

1

A

14

2

A

12

3

A

7

4

A

6

5

A

5

6

A

4

7

A

3

SO28-8

TSOP

21
20
19
18
17
16
15
14
13
12
11
10

9
8

A

10

CS

7

I/O
I/O

6

I/O

5

I/O

4

I/O

3

GND
I/O

2

I/O

1

I/O

0

A

0

A

1

A

2

3770 drw 03

TOP VIEW

Symbol Rating Com’l. Unit

(2)

V

TERM

Terminal Voltage with –0.5 to +4.6 V
Respect to GND

(3)

V

TERM

Terminal Voltage with –0.5 to VCC+0.5 V
Respect to GND

T

A Operating Temperature 0 to +70 °C

T

BIAS Temperature Under Bias –55 to +125 °C
STG Storage Temperature –55 to +125 °C

T
P

T Power Dissipation 1.0 W

I

OUT DC Output Current 50 mA

NOTES: 3770 tbl 03

1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.

2. Vcc terminals only.

3. Input, Output, and I/O terminals; 4.6V maximum.

CAPACITANCE

(TA = +25°C, f = 1.0MHz, SOJ package)

Symbol Parameter

C

IN Input Capacitance VIN = 3dV 6 pF

C

OUT Output Capacitance VOUT = 3dV 7 pF

NOTE: 3770 tbl 04

1. This parameter is determined by device characterization, but is not

production tested.

(1)

Conditions Max. Unit

(1)

PIN DESCRIPTIONS

Name Description

A

0–A14 Addresses

I/O

0–I/O7 Data Input/Output

CS
WE
OE

GND Ground
V

CC Power

TRUTH TABLE

WE

WE

X H X High-Z Standby (ISB)
XV
H L H High-Z Output Disable
HLLD

LLXD

NOTE: 3770 tbl 02

1. H = VIH, L = VIL, X = Don’t Care

CS

CS

HC X High-Z Standby (ISB1)

Chip Select
Write Enable
Output Enable

(1)

OE

OE

3770 tbl 01

I/O Function

OUT Read

IN Write

RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE

Grade Temperature GND VCC

Commercial 0°C to +70°C 0V 3.3V ± 0.3V

3770 tbl 05

RECOMMENDED DC OPERATING
CONDITIONS

Symbol Parameter Min. Typ. Max. Unit

VCC Supply Voltage 3.0 3.3 3.6 V
GND Supply Voltage 0 0 0 V
VIH Input High Voltage - Inputs 1.8 — 5.0 V
VIH Input High Voltage - I/O 1.8 — Vcc+0.3 V
V

IL Input Low Voltage –0.5

NOTE: 3770 tbl 06

1. VIL (min.) = –1.0V for pulse width less than 5ns, once per cycle.

(1)

— 0.8 V

2

IDT71V256SB

3.3V CMOS STATIC RAM WITH 2.5V COMPATIBLE INPUTS 256K (32K x 8-BIT) COMMERCIAL TEMPERATURE RANGE

DC ELECTRICAL CHARACTERISTICS

(1, 2)

(VCC = 3.3V ± 0.3V, VLC = 0.2V, VHC = VCC - 0.2V)

71V256SB12 71V256SB15 71V256SB20

Symbol Parameter Com’l Com’l. Com’l. Unit

I

CC Dynamic Operating Current

Open, V

CC = Max., f = fMAX

ISB Standby Power Supply Current (TTL Level) 20 20 20 mA

CS

= V

IH, VCC = Max., Outputs Open, f = fMAX

ISB1 Full Standby Power Supply Current (CMOS Level) 2 2 2 mA

CS

≥ V

HC, VCC = Max., Outputs Open, f = 0

V

IN ≤ VLC or VIN ≥ VHC

NOTES: 3770 tbl 07

1. All values are maximum guaranteed values.

MAX = 1/tRC, only address inputs cycling at fmax; f = 0 means that no inputs are cycling.

2. f

CS

≤ VIL, Outputs 90 85 85 mA

(2)

(2)

(2)

,

DC ELECTRICAL CHARACTERISTICS

VCC = 3.3V± 0.3V

IDT71V256SB

Symbol Parameter Test Condition Min. Typ. Max. Unit

|I

LI| Input Leakage Current VCC = Max., VIN = GND to VCC ——2µA

|I

LO| Output Leakage Current VCC = Max., CS = VIH, VOUT = GND to VCC ——2µA

OL Output Low Voltage IOL = 8mA, VCC = Min. — — 0.4 V

V

OH Output High Voltage IOH = –4mA, VCC = Min. 2.4 — — V

V

3770 tbl 08

AC TEST CONDITIONS

Input Pulse Levels GND to 3.0V
Input Rise/Fall Times 3ns

Input Timing Reference Levels 1.5V
Output Reference Levels 1.5V
AC Test Load See Figures 1 and 2

3.3V

320

Ω

DATA

OUT

Ω

350

Figure 1. AC Test Load

30pF*

3770 drw 04

*Includes scope and jig capacitances

3770 tbl 09

DATA

3.3V

OUT

350Ω

Figure 2. AC Test Load

CLZ, tOLZ, tCHZ, tOHZ, tOW, tWHZ)

(for t

320Ω

5pF*

3770 drw 05

3

IDT71V256SB

3.3V CMOS STATIC RAM WITH 2.5V COMPATIBLE INPUTS 256K (32K x 8-BIT) COMMERCIAL TEMPERATURE RANGE

AC ELECTRICAL CHARACTERISTICS (VCC = 3.3V ± 0.3V, Commercial Temperature Range)

71V256SA12 71V256SA15 71V256SA20

Symbol Parameter Min. Max. Min. Max. Min. Max. Unit

Read Cycle

t

RC Read Cycle Time 12 — 15 — 20 — ns

t

AA Address Access Time — 12 — 15 — 20 ns

t

ACS Chip Select Access Time — 12 — 15 — 20 ns

(1)

t

CLZ

t

CHZ

t

OE Output Enable to Output Valid — 6 — 7 — 8 ns

t

OLZ

t

OHZ

t

OH Output Hold from Address Change 3 — 3 — 3 — ns

Write Cycle

t

WC Write Cycle Time 12 — 15 — 20 — ns

t

AW Address Valid to End-of-Write 9 — 10 — 15 — ns

t

CW Chip Select to End-of-Write 9 — 10 — 15 — ns

t

AS Address Set-up Time 0 — 0 — 0 — ns

t

WP Write Pulse Width 9 — 10 — 15 — ns

t

WR Write Recovery Time 0 — 0 — 0 — ns

t

DW Data to Write Time Overlap 6 — 7 — 8 — ns

t

DH Data Hold from Write Time 0 — 0 — 0 — ns

t

OW

t

WHZ

NOTE: 3770 tbl 10

1. This parameter guaranteed with the AC test load (Figure 2) by device characterization, but is not production tested.

Chip Select to Output in Low-Z 5 — 5 — 5 — ns

(1)

Chip Select to Output in High-Z 0 8 0 9 0 10 ns

(1)

Output Enable to Output in Low-Z 3 — 0 — 0 — ns

(1)

Output Disable to Output in High-Z 2 6 0 7 0 8 ns

(1)

Output Active from End-of-Write 4 — 4 — 4 — ns

(1)

Write Enable to Output in High-Z 1 8 1 9 1 10 ns

TIMING WAVEFORM OF READ CYCLE NO. 1

tRC

ADDRESS

tAA tOH

OE

tOE

(2)

tOLZ

CS

tACS

(2)

tCLZ

DATA

OUT

NOTES:

1.WE is HIGH for Read cycle.

2. Transition is measured ±200mV from steady state.

(1)

DATA VALID

tOHZ

tCHZ

(2)

(2)

3770 drw 06

4

IDT71V256SB

3.3V CMOS STATIC RAM WITH 2.5V COMPATIBLE INPUTS 256K (32K x 8-BIT) COMMERCIAL TEMPERATURE RANGE

TIMING WAVEFORM OF READ CYCLE NO. 2

tRC

ADDRESS

tAA

tOH

OUT

DATA

TIMING WAVEFORM OF READ CYCLE NO. 3

CS

t

ACS

(5)

t

CLZ

DATA

OUT

NOTES:

1.WE is HIGH for Read cycle.

2. Device is continuously selected, CS is LOW.

3. Address valid prior to or coincident with CS transition LOW.

4.OE is LOW.

5. Transition is measured ±200mV from steady state.

(1, 2, 4)

(1, 3, 4)

DATA VALIDPREVIOUS DATA VALID

DATA VALID

tOH

t

CHZ

3770 drw 07

(5)

3770 drw 08

TIMING WAVEFORM OF WRITE CYCLE NO. 1 (

t

ADDRESS

OE

t

AW

CS

t

DATA

DATA

WE

OUT

t

AS

(6)

t

WHZ

(4)

IN

WEWE CONTROLLED TIMING)

WC

(7)

WP

t

DW

DATA VALID

t

WR

t

t

DH

(1, 2, 3, 5, 7)

(6)

OW

t

OHZ

(6)

(4)

3770 drw 09

NOTES:

1.WE or CS must be HIGH during all address transitions.

2. A write occurs during the overlap of a LOW CS and a LOW WE.

3. t

WR is measured from the earlier of

4. During this period, I/O pins are in the output state so that the input signals must not be applied.

5. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state.

6. Transition is measured ±200mV from steady state.

7. If OE is LOW during a WE controlled write cycle, the write pulse width must be the larger of t
to be placed on the bus for the required t
be as short as the spectified t

WP.

CS

or WE going HIGH to the end of the write cycle.

DW. If

OE

is HIGH during a

WE

controlled write cycle, this requirement does not apply and the write pulse can

WP or (tWHZ + tDW) to allow the I/O drivers to turn off and data

5

IDT71V256SB

3.3V CMOS STATIC RAM WITH 2.5V COMPATIBLE INPUTS 256K (32K x 8-BIT) COMMERCIAL TEMPERATURE RANGE

TIMING WAVEFORM OF WRITE CYCLE NO. 2 (

CSCS CONTROLLED TIMING)

(1, 2, 3, 4)

tWC

ADDRESS

tAW

CS

(5)

ASt t

tCW

t

WR

WE

tDW

IN

DATA

NOTES:

1.WE or CS must be HIGH during all address transitions.

2. A write occurs during the overlap of a LOW CS and a LOW WE.

3. t

WR is measured from the earlier of

4. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state.

5. If OE is LOW during a WE controlled write cycle, the write pulse width must be the larger of t
to be placed on the bus for the required t
be as short as the spectified t

WP.

CS

or WE going HIGH to the end of the write cycle.

DW. If

OE

is HIGH during a

WE

controlled write cycle, this requirement does not apply and the write pulse can

DATA VALID

WP or (tWHZ + tDW) to allow the I/O drivers to turn off and data

tDH

3770 drw 10

ORDERING INFORMATION

IDT

71V256

Device

Type

SB

Power/

Rev

XX

SpeedYPackage

X

Process/

Temperature

Range

Blank

Y
PZ

12
15
20

SB

Commercial (0

°

C to +70°C)

300 mil SOJ (SO28-5)
TSOP Type I (SO28-8)

Speed in nanoseconds

Standard Power, 2.5V
Compatible Inputs

3770 drw 11

6