Datasheet IDT71V2556S, IDT71V2558S, IDT71V2556SA, IDT71V2558SA Datasheet (IDT)

A0-A17Address Inputs

Input

Synchronous

1

, CE2,

2

Chip Enables

Input

Synchronous

Output E nabl e

Input

Asynchronous

R/WRead / Write Si g nal

Input

Synchronous

Clock Enable

Input

Synchronous

1

,

2

,

3

,

4

Individual Byte Write Selects

Input

Synchronous

CLK

Clock

Input

N/A

ADV/LDAd vanc e b urs t addr e s s / Load ne w ad d re ss

Input

Synchronous

Linear / Interleaved Burst Order

Input

Static

TMS

Test Mode Select

Input

Synchronous

TDI

Tes t D ata In p u t

Input

Synchronous

TCK

Test C lo c k

Input

N/A

TDO

Test D at a O ut p u t

Output

Synchronous

JTAG Reset (Optional)

Input

Asynchronous

ZZ

Sleep Mode

Input

Synchronous

I/O0-I/O31, I/OP1-I/OP4Data In p u t / O utp u t

I/O

Synchronous

VDD, V

DDQ

Core P o we r, I/O P o wer

Supply

Static

VSSGround

Supply

Static

4875 tbl 01

查询IDT71V2556S供应商

128K x 36, 256K x 18

3.3V Synchronous ZBT™ SRAMs

2.5V I/O, Burst Counter
Pipelined Outputs

Features

◆◆

◆

◆◆

128K x 36, 256K x 18 memory configurations

◆◆

◆

◆◆

Supports high performance system speed - 200 MHz
(3.2 ns Clock-to-Data Access)

◆◆

◆

◆◆

ZBTTM Feature - No dead cycles between write and read
cycles

◆◆

◆

◆◆

Internally synchronized output buffer enable eliminates the
need to control

◆◆

◆

◆◆

Single R/

◆◆

◆

◆◆

Positive clock-edge triggered address, data, and control
signal registers for fully pipelined applications

◆◆

◆

◆◆

4-word burst capability (interleaved or linear)

◆◆

◆

◆◆

Individual byte write (

◆◆

◆

◆◆

Three chip enables for simple depth expansion

◆◆

◆

◆◆

3.3V power supply (±5%), 2.5V I/O Supply (VDDQ)

◆◆

◆

◆◆

Optional - Boundary Scan JTAG Interface (IEEE 1149.1
complaint)

◆◆

◆

◆◆

Packaged in a JEDEC standard 100-pin plastic thin quad
flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch
ball grid array (fBGA)

Description

The IDT71V2556/58 are 3.3V high-speed 4,718,592-bit (4.5 Mega­bit) synchronous SRAMS. They are designed to eliminate dead bus cycles
when turning the bus around between reads and writes, or writes and
reads. Thus, they have been given the name ZBTTM, or Zero Bus
Turnaround.

Address and control signals are applied to the SRAM during one clock

Pin Description Summary

OEOE

OE

OEOE

WW

W (READ/WRITE) control pin

WW

BWBW

BWBW

BW1 -

BW4) control (May tie active)

BWBW

BWBW

IDT71V2556S

IDT71V2558S
IDT71V2556SA
IDT71V2558SA

cycle, and two cycles later the associated data cycle occurs, be it read
or write.

The IDT71V2556/58 contain data I/O, address and control signal
registers. Output enable is the only asynchronous signal and can be used
to disable the outputs at any given time.

A Clock Enable (CEN) pin allows operation of the IDT71V2556/58 to
be suspended as long as necessary. All synchronous inputs are ignored
when (CEN) is high and the internal device registers will hold their previous
values.

There are three chip enable pins (CE1, CE2, CE2) that allow the user
to deselect the device when desired. If any one of these three are not
asserted when ADV/LD is low, no new memory operation can be initiated.
However, any pending data transfers (reads or writes) will be completed.
The data bus will tri-state two cycles after chip is deselected or a write is
initiated.

The IDT71V2556/58 has an on-chip burst counter. In the burst mode,
the IDT71V2556/58 can provide four cycles of data for a single address
presented to the SRAM. The order of the burst sequence is defined by the
LBO input pin. The LBO pin selects between linear and interleaved burst
sequence. The ADV/LD signal is used to load a new external address
(ADV/LD = LOW) or increment the internal burst counter (ADV/LD =
HIGH).

The IDT71V2556/58 SRAMs utilize IDT's latest high-performance
CMOS process and are packaged in a JEDEC standard 14mm x 20mm
100-pin thin plastic quad flatpack (TQFP) as well as a 119 ball grid array
(BGA) and a 165 fine pitch ball grid array (fBGA).

CE

CE

OE

CEN

BW

BW

BW

BW

LBO

TRST

©2004 Integrated Device Technology, Inc.

1

OCTOBER 2004

DSC-4875/08

IDT71V2556, IDT71V2558, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs

4875 tbl 02

with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges

Pin Definitions

(1)

Symbol Pin Function I/O Active Description

A0-A

17

Address Inputs I N/A Synchronous Address inputs. The address register is triggered by a combination of the rising edge of

CLK, ADV/LD low, CEN low, and true chip e nables .

ADV/LD Advance / Lo ad I N/A ADV/LD is a s ync hro n o us inp ut that is used to lo ad the i nte rnal reg is te rs with ne w ad d re s s and c o ntro l

when it is sampled low at the rising edge of clock with the chip selected. When ADV/ LD is low with the
chip d e selected, any burst in p rog ress is terminated. When ADV/LD is sampled high then the internal
burst counter is advanced for any burst that was in progress. The external addresses are ignored
when ADV/LD is sample d high.

R/ W Re ad / Wri te I N/ A R/W signal is a synchronous input that identifies whether the current load cyc le initiated is a Read or

Write access to the memory array. The data bus activity for the current cycle takes place two clock
cycles later.

CEN

Clock Enable I LOW Synchro nous Clock Enable Input. When CE N is sam p led high, all other synchronous inputs, including

clock are i g nored and outputs remain unchanged. The e ffect of CE N sampled high on the device
outputs is as if the low to high clock transition did not occur. For normal operation, CEN must be
sampled low at rising edge of clock.

BW

1

-BW

4

Ind iv id ua l By te

Write Enables

I LOW Synchronous byte write enables. Each 9-bit byte has its own active low b yte write enable. On load

wri te c y cl es (Wh e n R/ W and ADV/LD are sampled low) the appropriate byte write signal (BW
must be valid. The byte write signal must also be valid on each cycle of a burst write. Byte Write
signals are ig n ore d whe n R/ W is sampled high. The appropriate byte(s) of data are written into the

CE

1

, CE

device two cycles later. BW

2

Chip Enables I LOW Sy nchronous active low chip enable. CE1 and CE2 are used with CE2 to e n abl e the IDT71V2556 /58.

(CE

or CE2 sampled high or CE2 sample d lo w) and ADV/LD low at the rising edge of c lock, initiates a

1

desele ct cycle. The ZBT

-BW4 can all be tied low if always doing write to the entire 36-bit word.

1

TM

has a two cy cle de se lect, i.e ., the data bus will tri-state two cloc k cy cle s

after des ele ct is initiated.

CE

2

Chip Enable I HIGH Synchronous active high chip enable. CE2 is used with CE1 and CE2 to enable the chip. CE2 has

inverted p olarity but otherwise ide ntical to CE

and CE2.

1

CLK Clock I N/A This is the clock input to the IDT71V2556/58. Exce p t for OE, all timing references for the de vice are

made with respect to the rising edge of CLK.

I/O

-I/O

0

I/OP1-I/O

LBO

Data Input/Output I/O N/A Synchronous data input/output (I/O) pins. Both the data input path and data output path are registered

31

P4

and triggered by the rising edge of CLK.

Linear Burst Order I LOW Burst order selection input. When LBO is high the Interleaved burst sequence is selected. When LBO

is low the Linear burst se quence is selected. LBO i s a s tatic input and it mus t no t ch ang e d uri ng
device operation.

OE

Output Enab l e I LOW As ync hro n ous o utp ut e nab le . OE m ust b e l o w to re ad d ata from the 71V255 6/58 . W he n OE is high the

I/O pins are in a high-impedance state. OE d oes not need to be actively controll ed for read and write
cy c le s . In no rmal o p er atio n, OE can be tied low.

TMS Test Mode Se lect I N/A

TDI Te st Data In pu t I N/ A

TCK Test C l oc k I N/ A

TDO Tes t Data Ou tp ut O N/A

TRST

JTAG Reset

(Op tional)

ILOW

Gives input command for TAP controller. Sampled on rising edge of TDK. This pin has an inte rnal
pullup.

Serial input of registers placed betwee n TDI and TDO. Sampled on rising edge of TCK. This pin has
an inte rnal p ull up .

Clock input of TAP controller. Each TAP event is clocked. Test inputs are captured on rising edge of
TCK, while test outputs are driven from the falling edge of TCK. This pin has an internal pullup.

Serial output of registers placed between TDI and TDO. This output is active depending on the state of
the TAP c ontroller.

Optional Asynchronous JTAG reset. Can be used to re set the TAP controller, but not required. JTAG
re set occurs a utomaticall y at p owe r up and also re sets using TMS and TCK per IE EE 1149.1. If not
used TRST can be l e ft fl o ati ng. Thi s p i n ha s a n i nte r nal p u ll up .

Synchronous s leep mode input. ZZ HIGH will gate the CLK internally and p ower do wn the

ZZ Sleep Mode I HIGH

IDT71V2556/ 2558 to i ts l o we st p o we r c o ns ump ti on le v e l. Data rete n tio n is g uar ante ed i n Sl e e p Mod e .
This p in has an i nte rnal p ull d o wn

V

DD

V

DDQ

V

SS

Power Supply N/A N/A 3.3V core power supply.
Power Supp ly N/A N/A 2.5V I/O Supp ly.

Ground N/A N/A Ground.

-BW4)

1

NOTE:

1. All synchronous inputs must meet specified setup and hold times with respect to CLK.

6.422

IDT71V2556, IDT71V2558, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs
with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges

Functional Block Diagram

LBO

Address A [0:16]

CE

1, CE2,CE2

R/W

CEN

ADV/LD

BWx

Clock

DQ

DQ

egister

Input R

DQ

Clk

Address

Control

Control Logic

Clk

128Kx36 BIT

MEMORY ARRAY

DI DO

Mux

D

Output Register

Q

Sel

OE

TMS

TDI

TCK

TRST

(optional)

JTAG

(SA Version)

TDO

Gate

Data I/O [0:31],

I/O P[1:4]

4875 drw 01a

,

6.42

3

IDT71V2556, IDT71V2558, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs

(2)

(1)

4875 tbl 03

with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges

Functional Block Diagram

Address A [0:17]

CE

1, CE2,CE2

ADV/

Clock

LBO

R/

CEN

LD

BW

W

256x18 BIT

MEMOR YARRAY

DQ

DQ

egister

Address

Control

DI DO

x

Inpu t R

DQ

Clk

Control Logic

Clk

Mux

D

Output Register

Q

Sel

OE

TMS

TDI

TCK

TRST

(optional)

JTAG

(SA Version)

Recommended DC Operating

Conditions

Symbol Parameter Min. Typ. Max. Unit

Core S up p ly Vo ltag e 3.135 3.3 3. 465 V

V

DD

I/O S up p ly Vol tag e 2.3 75 2.5 2. 625 V

V

DDQ

Supply Voltage 0 0 0 V

V

SS

Input High Voltage - Inputs 1.7

V

IH

I nput Hi gh Volta g e - I/O 1. 7

V

IH

Input Lo w Vo ltag e -0.3

V

IL

NOTES:

1. V IL (min.) = –1.0V for pulse width less than tCYC/2, once per cycle.

2. VIH (max.) = +6.0V for pulse width less than tCYC/2, once per cycle.

____

V

+0.3 V

DD

____

V

+0.3

DDQ

____

0.7 V

Gate

4875 drw 01b

Data I/O [0:15],

TDO

V

I/O P[1:2]

6.424

IDT71V2556, IDT71V2558, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs

Grade

Temperature

(1)

VSSVDDV

DDQ

with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges

Recommended Operating

Temperature and Supply Voltage

Comm ercial 0° C to +70°C 0V 3.3V± 5% 2.5V± 5%

Ind us tria l -40°C to + 85°C 0 V 3. 3V±5% 2. 5V ± 5%

NOTES:

4875 tbl 05

1. TA is the "instant on" case temperature.

Pin Configuration  128K x 36

LD

4

3

2

A6A

100 99 98 97 96 95 94 93 92 91 90 87 86 85 84 83 82 8189 88

B

C

C

2

1

7

E

W

E

1

2

D

S

LK

D

W

W

W

B

B

B

S

E
C

C

V

V

W

/
R

/

(2)

(2)

V

N

E

C

D

E

A

N

O

C

9

C

A8A

N

DDQ

V

SS

V

SS

DDQ

V

DD

V

SS

DDQ

V

SS

V

SS

DDQ

1

P3

2

16

3

17

4
5
6

18

7

19

8

20

9

21

10
11
12

22

13

23

(1)

14
15

(1)

16
17
18

24

19

25

20
21
22

26

23

27

24

28

25

29

26
27
28

30

29

31

30

P4

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

O
LB

5

C

A0A1A2A3A4A

N

D

S

C

S

N

V

C

C

D

N

N

V

I/O
I/O
I/O

V

I/O
I/O
I/O
I/O

V

I/O
I/O

V

DD

V

DD

I/O
I/O

V

I/O
I/O
I/O
I/O

V

I/O
I/O
I/O

80

I/O
I/O
I/O
V
V

SS

I/O
I/O
I/O
I/O
V
V

I/O
I/O
V
V

DD

V

DD

V
I/O
I/O
V

DDQ

V

SS

I/O
I/O
I/O
I/O
V
V
I/O
I/O

I/O

4875 drw 02

P2

15

14

DDQ

13
12
11

10
SS
DDQ

9

8
SS

(1)

SS/ZZ

7

6

5

4

3

2
SS
DDQ

1

0

P1

(3)

,

79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

14A13A12A11A10

16

A15A

A

Top View

TQFP

NOTES:

1. Pins 14, 16 and 66 do not have to be connected directly to VDD as long as the input voltage is ≥ VIH.

2. Pins 83 and 84 are reserved for future 8M and 16M respectively.

3. Pin 64 does not have to be connected directly to VSS as long as the input voltage is ≤ VIL; on the latest die revision this
pin supports ZZ (sleep mode).

6.42

5

IDT71V2556, IDT71V2558, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs

Symbol

Ratin g

Commercial &

In dus tri al Va l ues

Uni t

TERM

TERM

DD

TERM

TERM

DDQ

A

Commerical

Industrial

BIAS

STG

T

OUT

Symbol

Parameter

(1)

Conditions

Max.

Unit

CINInp ut Capa ci tanc e

VIN = 3dV

5pFC

I/O

I/O Cap aci tance

V

OUT

= 3dV

7

pF

4875 tbl 07

Symbol

Par a me ter

(1)

Conditions

Max .

Unit

CINInput Cap aci tance

VIN = 3dV

7pFC

I/O

I/O Cap aci tance

V

OUT

= 3dV

7

pF

4875 tbl 07 a

Symbo l

Par a me t e r

(1)

Conditions

Max .

Unit

CINInp ut Cap ac itanc e

VIN = 3dV

TBDpFC

I/O

I/O Cap aci tanc e

V

OUT

= 3dV

TBD

pF

4875 tb l 07b

with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges

Pin Configuration  256K x 18

LD

2

2

1

7

E

E

A6A

C

C

10099989796959493929190 8786858483828189 88

1

NC

2

NC

3

NC

4

DDQ

V

5

SS

V

6

NC

7

NC

8

8

I/O

9

9

I/O

10

SS

V

11

DDQ

V

12

10

I/O

13

11

I/O

(1)

14

DD

V

15

DD

V

(1)

16

DD

V

17

SS

V

18

12

I/O

19

13

I/O

20

DDQ

V

21

SS

V

22

14

I/O

23

15

I/O

24

P2

I/O

25

NC

26

SS

V

27

DDQ

V

28

NC

29

NC

30

NC

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

5

O
LB

1

2

D

S

C

C

W

W
B

N

B

N

C

A0A1A2A3A4A

N

LK

D

S

E

C

V

V

C

D

S

C

C

S

D

N

N

V

V

/

(2)

(2)

V

N

W

E

C

D

C

E

/

C

R

C
N

N

A8A

A

N

O

15A14A13A12A11

A16A

A

9

17

80
79
78
77
76
75
74
73
72

71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

4875 drw 02a

Absolute Maximum Ratings

(2)

V

10

NC
NC

V
NC
I/O
I/O
I/O

I/O
I/O

V
V

V
V
I/O
I/O
NC
NC

A

V

V
V

V

V
I/O
I/O

V
V
NC
NC
NC

DDQ
SS

P1
7

6
SS
DDQ

5

4
SS
DD
DD
SS/ZZ

3

2
DDQ
SS

1

0

SS
DDQ

V

V

V

(1)

(7)

T

(3)

T

T

P

,

I

NOTES:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional

Te rminal Vo ltage with

Respect to GND

(3,6)

Te rminal Vo ltage with
Respect to GND

(4,6)

Te rminal Vo ltage with

-0.5 to VDD +0.5 V

Respect to GND

(5,6)

Te rminal Vo ltage with

-0.5 to V

Respect to GND

Operating Temperature

Operating Temperature
Temperature

Under B ia s
Storage

Temperature
Po we r Di ss i p atio n 2. 0 W
DC Output Current 50 mA

(1)

-0.5 to +4. 6 V

-0.5 to V

+0.5 V

-0 to + 70

-40 to + 85

-55 to + 125

-55 to + 125

4875 tbl 06

operation of the device at these or any other conditions above those indicated

Top View

TQFP

NOTES:

1. Pins 14, 16 and 66 do not have to be connected directly to VDD as long
as the input voltage is ≥ VIH.

2. Pins 83 and 84 are reserved for future 8M and 16M respectively.

3. Pin 64 does not have to be connected directly to VSS as long as the input
voltage is ≤ VIL; on the latest die revision this pin supports ZZ (sleep
mode).

in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.

2. VDD terminals only.

3. VDDQ terminals only.

4. Input terminals only.

5. I/O terminals only.

6. This is a steady-state DC parameter that applies after the power supply has
reached its nominal operating value. Power sequencing is not necessary;
however, the voltage on any input or I/O pin cannot exceed VDDQ during power
supply ramp up.

7. TA is the "instant on" case temperature.

100 TQFP Capacitance

(1)

(TA = +25° C, f = 1.0MHz)

119 BGA Capacitance

(1)

(TA = +25° C, f = 1.0MHz)

V

o

C

o

C

o

C

o

C

165 fBGA Capacitance

(1)

(TA = +25° C, f = 1.0MHz)

NOTE:

1. This parameter is guaranteed by device characterization, but not production tested.

6.426

IDT71V2556, IDT71V2558, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs
with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges

Pin Configuration  128K x 36, 119 BGA

1234567

DDQ

V

A

NC CE

B

NC

C

16

I/O

D

17

I/O

E

DDQ

V

F

20

I/O

G

22

I/O

H

DDQ

V

J

24

I/O

K

25

I/O

L

DDQ

V

M

29

I/O

N

31

I/O

P

NC A

R

NC NC A

T

DDQ

V

U

6

A

2

7

A

P3

I/O

18

I/O

19

I/O

21

I/O

23

I/O

DD

V

26

I/O

27

I/O

28

I/O

30

I/O

P4

I/O

5

NC/TMS

(3)

4

A

3

A

2

A

SS

V

SS

V

SS

V

BW

SS

V

DD(1)

V

SS

V

BW

SS

V

SS

V

SS

V

LBO

10

NC/TDI

3

4

(3)

NC(2)

ADV/LD

DD

V

NC V

1

CE

OE

NC(2)

R/W

DD

V
CLK V

NC

CEN

1

A

0

A

DD

V

11

A

(3)

NC/TCK

8

A

9

A

12

A

SS

SS

V

SS

V

2

BW

SS

V

DD(1)

V

SS

1

BW

SS

V

SS

V

SS

V

V

DD(1)

14

A

NC/TDO

16

A

2

CE

15

A

P2

I/O

13

I/O

12

I/O

11

I/O

9

I/O

DD

V

6

I/O

4

I/O

3

I/O

2

I/O

I/O

P1

13

A

NC NC/ZZ

(3)

TRST

NC/

(3,4)

DDQ

V

NC
NC

15

I/O

14

I/O

DDQ

V

10

I/O

8

I/O

DDQ

V

7

I/O

5

I/O

DDQ

V

1

I/O

0

I/O

NC

DDQ

V

4875 drw 13a

,

(5)

Top View

Pin Configuration  256K x 18, 119 BGA

1234567

DDQ

V

A

NC CE2 A

B

NC

C

8

I/O

D

NC I/O

E

DDQ

V

F

NC I/O

G

11

I/O

H

DDQ

V

J

NC I/O

K

13

I/O

L

DDQ

V

M

15

I/O

N

NC I/O

P

NC A

R

NC A

T

DDQ

V

U

NOTES:

1. J3, J5, and R5 do not have to be directly connected to VDD as long as the input voltage is ≥ VIH.

2. G4 and A4 are reserved for future 8M and 16M respectively.

3. These pins are NC for the "S" version and the JTAG signal listed for the "SA" version.

4. TRST is offered as an optional JTAG reset if required in the application. If not needed, can be left floating and will internally be pulled to VDD.

5. Pin T7 supports ZZ (sleep mode) on the latest die revision.

6

A

7

A

NC V

9

NC V

10

NC V

DD

V

12

NC NC

14

I/O

NC V

P2

5

10

NC/TMS

(3)

4

A

3

2

A

SS

SS

V

SS

BW

SS

DD(1)

V

SS

V

SS

V

SS

V

SS

SS

V

LBO

15

A

NC/TDI

2

(3)

Top View

NC(2)

ADV/LD

DD

V

NC V

1

CE

OE

NC(2)

R/W

DD

V

CLK V

CEN

1

A

0

A

DD

V

NC A

(3)

NC/TCK

8

A

9

A

13

A

SS

SS

V

SS

V

SS

V

SS

V

DD(1)

V

SS

BW

1

SS

V

SS

V

SS

V

V

DD(1)

14

NC/TDO

16

A

CE

17

A

I/O

NC I/O
I/O
NC I/O
I/O

DD

V

NC I/O
I/O
NC V
I/O
NC I/O

12

A

11

A

(3)

NC/

2

P1

6

4

2

1

TRST

(3,4)

DDQ

V

NC
NC
NC

7

DDQ

V

5

NC

DDQ

V

3

NC

DDQ

NC

0

NC
NC/ZZ

DDQ

V

4875 drw 13b

,

(5)

6.42

7

IDT71V2556, IDT71V2558, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs

7

3BW2CE2

8

6CE2BW4BW1

9

DDQVSSVSSVSSVSSVSSVDDQ

P2

16VDDQVDDVSSVSSVSSVDDVDDQ

15

14

18VDDQVDDVSSVSSVSSVDDVDDQ

13

12

20VDDQVDDVSSVSSVSSVDDVDDQ

11

10

22VDDQVDDVSSVSSVSSVDDVDDQ

9

8

DD

DD

DDVSSVSSVSSVDD

24VDDQVDDVSSVSSVSSVDDVDDQ

7

6

26VDDQVDDVSSVSSVSSVDDVDDQ

5

4

28VDDQVDDVSSVSSVSSVDDVDDQ

3

2

30VDDQVDDVSSVSSVSSVDDVDDQ

1

0

DDQVSS

NC/

DD

SSVDDQ

P1

5A2

1

10A13A14

4A3

0

11A12A15A16

4875 tb l 25

7CE1BW2

2

8A10

2

1

9

DDQVSSVSSVSSVSSVSSVDDQ

P1

DDQVDDVSSVSSVSSVDDVDDQ

7

DDQVDDVSSVSSVSSVDDVDDQ

6

DDQVDDVSSVSSVSSVDDVDDQ

5

DDQVDDVSSVSSVSSVDDVDDQ

4

DD

DD

DDVSSVSSVSSVDD

DDQVDDVSSVSSVSSVDDVDDQ

3

DDQVDDVSSVSSVSSVDDVDDQ

2

DDQVDDVSSVSSVSSVDDVDDQ

1

DDQVDDVSSVSSVSSVDDVDDQ

0

P2

DDQVSS

NC/

DD

SSVDDQ

5A2

1

11A14A15

4A3

0

12A13A16A17

4875 tb l 25a

with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges

Pin Configuration  128K x 36, 165 fBGA

1234567891011

ANC

(2)

A
BNC A
CI/OP3NC V
DI/O17I/O
EI/O19I/O

FI/O21I/O
GI/O23I/O
HV

(1)

(1)

V

JI/O25I/O
KI/O27I/O

LI/O29I/O
MI/O31I/O
NI/OP4NC V

NC

(2)

(2)

PNCNC
R

LBO

CE1 BW

NC V

A
A

TRST

NC/TDI

NC/TMS

(3,4)

(3)

(3)

CEN

CLK R/W

NC V

A

NC/TDO

A

NC/TCK

(1)

(3)

(3)

ADV/LD NC

OE

V
A

A

NC

(2)

(2)

A
A

NC

NC I/O
I/O
I/O
I/O

I/O

I/O
I/O
I/O

I/O

NC NC NC/Z Z

I/O
I/O
I/O
I/O

I/O
I/O
I/O
I/O

NC I/O

NC

(2)

(5)

NC

Pin Configuration  256K x 18, 165 fBGA

1234567891011
ANC
BNC A6CE

(2)

A

NC

NC

BW

CE

CEN

CLK R/W

ADV/LD NC

OE

CNC NCV
DNC I/O8V
ENC I/O9V

FNCI/O10V
GNC I/O11V
HV

(1)

(1)

V

NC V

JI/O12NC V
KI/O13NC V

LI/O14NC V
MI/O15NC V

NC/TDO
NC/TCK

(1)

V

(3)

A

(3)

A

NI/O
PNC NC
R

LBO

NC V

(2)

(2)

NC

(3,4)

TRST

A
A

NC/TDI

NC/TMS

(3)

(3)

NC V

A
A

NOTES:

1. H1, H2, and N7 do not have to be directly connected to VDD as long as the input voltage is ≥ VIH.

2. A9, B9, B11, A1, R2 and P2 are reserved for future 9M, 18M, 36M, 72M, 144M, and 288M respectively respectively.

3. These pins are NC for the "S" version and the JTAG signal listed for the "SA" version.

4. TRST is offered as an optional JTAG reset if required in the application. If not needed, can be left floating and will internally be pulled to VDD.

5. Pin H11 supports ZZ (sleep mode) on the latest die revision.

6.428

NC

(2)

(2)

A

A
NC I/O
NC I/O
NC I/O
NC I/O
NC I/O

NC NC NC /ZZ

I/O
I/O
I/O
I/O

NC NC

NC

(2)

(5)

NC
NC
NC
NC

NC

IDT71V2556, IDT71V2558, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs

R/WChip

(5)

Enable

ADV/

x

ADDRESS

USED

PREVIOUS CYCLE

CURRENT CYCLE

I/O

(2 cycles l ater)

OP E RATION

R/

1BW2BW3

(3)

4

(3)

P3

with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges

Synchronous Truth Table

CEN

LD

(1)

BW

D

Q

HiZ

(7)

(7)

(7)

(7)

L L Sele ct L Valid Ex ternal X LOAD WRITE D
L H Sele ct L X External X LOAD READ Q
L X X H Valid Inte rnal LOAD WRITE /

BURS T WRITE

L X X H X Interna l LOA D RE A D /

BURST READ

L X Deselect L X X X DESELECT or STOP

BURS T WRITE

(Advance burst counter)

BURST READ

(Advance burst counter)

(2)

(2)

(3)

L X X H X X DESELECT / NOOP NOOP HiZ
H X X X X X X SUS PEND

NOTES:

1. L = VIL, H = VIH, X = Don’t Care.

2. When ADV/LD signal is sampled high, the internal burst counter is incremented. The R/ W signal is ignored when the counter is advanced. Therefore the nature of
the burst cycle (Read or Write) is determined by the status of the R/W signal when the first address is loaded at the beginning of the burst cycle.

3. Deselect cycle is initiated when either (CE1, or CE2 is sampled high or CE2 is sampled low) and ADV/LD is sampled low at rising edge of clock. The data bus will
tri-state two cycles after deselect is initiated.

4. When CEN is sampled high at the rising edge of clock, that clock edge is blocked from propogating through the part. The state of all the internal registers and the I/
Os remains unchanged.

5. To select the chip requires CE1 = L, CE2 = L, CE2 = H on these chip enables. Chip is deselected if any one of the chip enables is false.

6. Device Outputs are ensured to be in High-Z after the first rising edge of clock upon power-up.

7. Q - Data read from the device, D - data written to the device.

(4)

Previous Value

4875 tbl 08

Partial Truth Table for Writes

(1)

W

BW

BW

READ HXXXX

WRITE ALL BYTES LLLLL
WRITE BYTE 1 (I/O[0:7], I/OP1)
WRITE BYTE 2 (I/O[8:15], I/OP2)
WRITE BYTE 3 (I/O[16:23] , I/O
WRITE BYTE 4 (I/O[24:31] , I/OP4)

(2)

(2)

(2,3)

)

(2,3)

LLHHH
LHLHH
LHHLH
LHHHL

NO WRITE L HHHH

NOTES:

1. L = VIL, H = VIH, X = Don’t Care.

2. Multiple bytes may be selected during the same cycle.

3. N/A for X18 configuration.

4875 tbl 09

6.42

9

IDT71V2556, IDT71V2558, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs

Sequence 1

Sequence 2

Sequence 3

Sequence 4

A1A0A1A0A1A0A1

A0

Sequence 1

Sequence 2

Sequence 3

Sequence 4

A1A0A1A0A1A0A1

A0

with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges

Interleaved Burst Sequence Table (LBO=VDD)

First Address 0 0 0 1 1 0 1 1
Second Address 0 1 0 0 1 1 1 0

Third Address 1 0 1 1 0 0 0 1

Fourth Address

NOTE:

1. Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting.

(1)

11100100

4875 tbl 10

Linear Burst Sequence Table (LBO=VSS)

First Address 0 0 0 1 1 0 1 1
Second Address 0 1 1 0 1 1 0 0

Third Address 1 0 1 1 0 0 0 1

Fourth Address

NOTE:

1. Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting.

(1)

11000110

4875 tbl 11

Functional Timing Diagram

CYCLE

CLOCK

ADDRESS

(A0 - A16)

CONTROL

(R/W, ADV/LD, BWx)

DATA

I/O [0:31], I/O P[1:4]

NOTES:

1. This assumes CEN, CE1, CE2, CE2 are all true.

2. All Address, Control and Data_In are only required to meet set-up and hold time with respect to the rising edge of clock. Data_Out is valid after a clock-to-data
delay from the rising edge of clock.

(2)

(2)

(2)

n+29

A29

C29

D/Q27

n+30

A30

C30

D/Q28

(1)

n+31

A31

C31

D/Q29

n+32

A32

C32

D/Q30

n+33

A33

C33

D/Q31

n+34

A34

C34

D/Q32

n+35

A35

C35

D/Q33

n+36

A36

C36

D/Q34

n+37

A37

C37

D/Q35

4875drw 03

,

6.4210

IDT71V2556, IDT71V2558, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs

Cycl e

Address

R/WADV/

(1)

xOEI/O

Comments

1

0+1

2

2

3

2+1

4

3+1

4

5

6

7

8

7+1

9

Cycl e

Address

R/WADV/

(2)

xOEI/O

Comments

0

with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges

Device Operation - Showint Mixed Load, Burst,

CE

(2)

CEN BW

Deselect and NOOP Cycles

LD

nA0H L L L X X X Load re ad

n+1 X X H X L X X X Burst re ad
n+2 A
n+3 X X L H L X L Q
n+4 X X H XLXLQ1NOOP
n+5 A
n+6 X X H X L X X Z Burst read
n+7 X X L H L X L Q
n+8 A
n+9 X X H X L L X Z Burst write

n+10 A

n+11 X X L H L X X D
n+12 X X H X L X X D
n+13 A
n+14 A

HL LLXLQ0Load read

H L L L X X Z Load read

L L LLLLQ

L L LLLXD3Load write

L L LLLXZLoad write

H L L L X X Z Load read

Deselect or STOP

Deselect or STOP
Load write

Deselect or STOP
NOOP

n+15 A

L L LLLXD5Load write
n+16 X X H XLLLQ6Burst write
n+17 A
n+18 X X H X L X X D
n+19 A

NOTES:

1. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.

2. H = High; L = Low; X = Don’t Care; Z = High Impedance.

Read Operation

HL LLXXD7Load read

Burst re ad

L L LLLLQ8Load write

(1)

LD

CE

CEN BW

nA0H L L L X X X Address and Control meet setup

n+1 X X X X L X X X Clock Setup Valid

n+2 X X X XXXLQ

NOTES:

1. H = High; L = Low; X = Don’t Care; Z = High Impedance.

2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.

Contents of Address A0 Re ad Out

4875 tbl 12

4875 tbl 13

6.42

11

IDT71V2556, IDT71V2558, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs

Cycl e

Address

R/WADV/

(2)

xOEI/O

Comments

0+1

0+1

0+2

0+2

1

0+3

0+3

1

2

1+1

1+1

2

Cycl e

Address

R/WADV/

(2)

xOEI/O

Comments

0

0

Cycl e

Address

R/WADV/

(2)

xOEI/O

Comments

0+1

0+1

0+2

0+2

0+3

0+3

1

2

1+1

1+1

2

with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges

LD

(1)

CE

CEN BW

Burst Read Operation

nA0H L L L X X X Address and Control meet setup

n+1 X X H X L X X X Clock Setup Valid, Advance Counter
n+2 X X H XLXLQ0Address A0 Re ad Out, Inc . Co unt
n+3 X X H XLXLQ
n+4 X X H XLXLQ
n+5 A

HL LLXLQ

Address A
Address A
Address A

Re ad Out, Inc . Co unt
Re ad Out, Inc . Co unt

Read Out, Load A
n+6 X X H XLXLQ0Address A0 Re ad Out, Inc . Co unt
n+7 X X H XLXLQ1Address A1 Re ad Out, Inc . Co unt
n+8 A

NOTES:

1. H = High; L = Low; X = Don’t Care; Z = High Impedance..

2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.

Write Operation

HL LLXLQ

Address A

(1)

LD

CE

CEN BW

Read Out, Load A

nA0L L L L L X X Address and Control meet setup

n+1 X X X X L X X X Clock Setup Valid

n+2 X X X X L X X D

NOTES:

1. H = High; L = Low; X = Don’t Care; Z = High Impedance.

2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.

Write to Address A

4875 tbl 14

4875 tbl 15

LD

(1)

CE

CEN BW

Burst Write Operation

nA0L L L L L X X Address and Control meet setup

n+1 X X H X L L X X Clock Se tup Valid , Inc. Count
n+2 X X H X L L X D0Address A0 Write, Inc. Co unt
n+3 X X H X L L X D
n+4 X X H X L L X D
n+5A1LLLLLXD

Address A
Address A
Address A

Write, Inc. Co unt
Write, Inc. Co unt

Write, Lo ad A
n+6 X X H X L L X D0Address A0 Write, Inc. Count
n+7 X X H X L L X D1Address A1 Write, Inc. Count
n+8 A

NOTES:

1. H = High; L = Low; X = Don’t Care; ? = Don’t Know; Z = High Impedance.

2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.

L L LLLXD

Address A

Write, Lo ad A

6.4212

4875 tbl 16

IDT71V2556, IDT71V2558, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs

Cycl e

Address

R/WADV/

(2)

xOEI/O

Comments

1

0

0

2

3

4

Cycl e

Address

R/WADV/

(2)

xOEI/O

Comments

1

2

0

3

1

4

2

with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges

Read Operation with Clock Enable Used

LD

CE

CEN BW

(1)

nA0H L L L X X X Address and Control meet setup

n+1 X X X X H X X X Clock n+1 Igno re d
n+2 A
n+3 X X X X H X L Q
n+4 X X X X H X L Q
n+5 A
n+6 A
n+7 A

NOTES:

1. H = High; L = Low; X = Don’t Care; Z = High Impedance.

2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.

H L L L XXXClock Valid

Clock Ignored. Data Q0 is on the bus.

Clock Ignored. Data Q0 is on the bus.
HL LLXLQ0Address A0 Read out (bus trans.)
HL LLXLQ1Address A1 Read out (bus trans.)
HL LLXLQ2Address A2 Read out (bus trans.)

4875 tbl 17

Write Operation with Clock Enable Used

LD

CE

CEN BW

(1)

nA0L L L L L X X Address and Control meet setup.

n+1 X X X X H X X X Clock n+1 Igno re d.

n+2 A

L L L L L X X Clock Valid.
n+3 X X X X H X X X Clock Ignored.
n+4 X X X X H X X X Clock Ignored.
n+5 A
n+6 A
n+7 A

NOTES:

1. H = High; L = Low; X = Don’t Care; Z = High Impedance.

2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.

L L LLLXD0Write Data D

L L LLLXD1Write Data D

L L LLLXD2Write Data D

4875 tbl 18

6.42

13

IDT71V2556, IDT71V2558, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs

Cycl e

Address

R/WADV/

(2)

xOEI/O

(3)

Comments

0

1

1

2

Cycl e

Address

R/WADV/

(2)

xOEI/O

(3)

Comments

0

1

1

2

with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges

Read Operation with Chip Enable Used

LD

CE

CEN BW

(1)

n X X L H L X X ? Deselected.

n+1 X X L H L X X ? Deselected.

n+2 A

H L L L X X Z Address and Control meet setup
n+3 X X L H L X X Z Deselected or STOP.
n+4 A

HL LLXLQ0Address A0 Read o ut. Load A1.
n+5 X X L H L X X Z Deselected or STOP.
n+6 X X L H L X L Q
n+7 A

H L L L X X Z Address and control meet setup.

Address A1 Read out. Deselected.

n+8 X X L H L X X Z Deselected or STOP.
n+9 X X L H L X L Q2Address A2 Read out. Deselected.

NOTES:

1. H = High; L = Low; X = Don’t Care; ? = Don’t Know; Z = High Impedance.

2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.

3. Device Outputs are ensured to be in High-Z after the first rising edge of clock upon power-up.

Write Operation with Chip Enable Used

LD

CE

CEN BW

(1)

n X X L H L X X ? Deselected.

4875 tbl 19

n+1 X X L H L X X ? Deselected.

n+2 A

L L L L L X Z Address and Control meet setup
n+3 X X L H L X X Z Deselected or STOP.
n+4 A

L L LLLXD0Address D0 Write in. Load A1.
n+5 X X L H L X X Z Deselected or STOP.
n+6 X X L H L X X D
n+7 A

L L L L L X Z Address and control meet setup.

Address D1 Write in. Des ele c ted .

n+8 X X L H L X X Z Deselected or STOP.
n+9 X X L H L X X D2Address D2 Write in. Des ele c ted .

NOTES:

1. H = High; L = Low; X = Don’t Care; ? = Don’t Know; Z = High Impedance.

2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.

4875 tbl 20

6.4214

IDT71V2556, IDT71V2558, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs

Symbol

Parameter

Test Conditions

Min.

Max.

Unit

L

I

DD

LI

DD

OUT

DDQ

OL

OH

4875 tbl 21

Symbol

Parameter

Test Conditi ons

200MHz

166MHz

133MHz

100MHz

Unit

Com' l Onl y

Com'l

Ind

Com'l

Ind

Com'l

Ind

IDDOp erating Po we r

Sup p ly Curre nt

Device Selected, Outputs Open,

ADV/LD = X, V

DD

= Max.,

VIN > VIH or < VIL, f = f

MAX

(2)

400

350

360

300

310

250

260mAI

SB1

CMOS S tandb y

Po we r Sup ply Curre nt

Device Deselected, Outputs

Ope n, V

DD

= Max., V

IN

> VHD or< VLD, f = 0

(2,3)

40404540454045mAI

SB2

Clo ck Runni ng P o we r

Sup p ly Curre nt

Device Deselected, Outputs

Ope n, V

DD

= Max., V

IN

> VHD or

< VLD,

f = f

MAX

(2.3)

130

120

130

110

120

100

110mAI

SB3

Idl e P owe r

Sup p ly Curre nt

Device Selected, Outputs Open,

> VIH, VDD = Max.,

VIN > VHD or < VLD, f = f

MAX

(2,3)

40404540454045

mA

4875 tb l 22

with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges

DC Electrical Characteristics Over the Operating

Temperature and Supply Voltage Range

(VDD = 3.3V±5%)

|I

| Input Leakage Current VDD = Max., VIN = 0V to V

|I

LBO, JTA G and ZZ Input Le akage Current

|
|ILO| Output Leakage Current V
V
V

NOTE:

1. The LBO, TMS, TDI, TCK & TRST pins will be internally pulled to VDD and ZZ will be internally pulled to VSS if it is not actively driven in the application.

Output Low Voltage IOL = +6mA, VDD = Min.
Outp ut Hig h Vol tag e IOH = -6mA, VDD = Min. 2.0

(1)

VDD = Max., VIN = 0V to V

= 0V to V

, De v i ce De s e l e c te d

___

___

___

___

5µA

30 µA

5µA

0.4 V

___

DC Electrical Characteristics Over the Operating

(1)

Temperature Supply Voltage Range

(VDD = 3.3V±5%)

V

CEN

NOTES:

1. All values are maximum guaranteed values.

2. At f = fMAX, inputs are cycling at the maximum frequency of read cycles of 1/tCYC; f=0 means no input lines are changing.

3. For I/Os VHD = VDDQ – 0.2V, VLD = 0.2V. For other inputs VHD = VDD – 0.2V, VLD = 0.2V.

DDQ

V

AC Test Loads

6
5
4

∆tCD

(Typical, ns)

3
2

I/O

Figure 1. AC Test Load

Z

0

=50Ω

/2

50Ω

4875 drw04

AC Test Conditions

(VDDQ = 2.5V)

Input Pulse Levels

,

Inp ut Ris e / Fa ll Tim e s
Inp ut Timi ng Re fe re nc e Le v e ls
Outp ut Tim ing R efe r e nc e Le vel s

AC Test Load

1

2030 50 100 200

Figure 2. Lumped Capacitive Load, Typical Derating

80

Capacitance (pF)

4875drw 05

,

0 to 2.5V

2ns

(V

/2)

DDQ

(V

/2)

DDQ

See Figure 1

4875 tbl 23

6.42

15

IDT71V2556, IDT71V2558, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs

200MHz

166MHz

133MHz

100MHz

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Uni t

CYC

F

CH

CL

Output Parameters

CD

CDC

CLZ

CHZ

OE

OLZ

OHZ

Set Up Times

SE

SA

SD

SW

SADV

SC

SB

Hol d T im es

HE

HA

HD

HW

HADV

HC

HB

4875 tbl 24

with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges

AC Electrical Characteristics

(VDD = 3.3V±5%, Commercial and Industrial Temperature Ranges)

t

(1)

t

(2)

t

(2)

t

t
t

(3,4 ,5)

t

(3,4 ,5)

t
t

(3,4)

t

(3,4)

t

t
t
t
t

Clo c k Cyc l e Time 5
Clock Frequence

____

Clock High Pulse Width 1.8
Clock Low Pulse Width 1.8

Clo c k Hig h to Vali d Data

____

Cloc k Hig h to Data Cha ng e 1
Cloc k Hig h to Outp ut A c tiv e 1
Cl o ck Hig h to Da ta Hig h- Z 1 3 1 3 1 3 1 3 ns
Output Enable Acces s Time

____

Outp ut En ab le Lo w to Data A c tiv e 0
Outp ut En ab le Hig h to Da ta Hig h-Z

____

Clock Enable Setup Time 1.5

Address Setup Time 1.5
Data In S e tu p Ti m e 1 .5
Re ad/ Write (R/W) Se tup Time 1.5

____

200

____

____

3.2

____

____

3.2

____

3.5

____

____

____

____

6

____

1.8

1.8

____

1
1

____

0

____

1.5

1.5

1.5

1.5

____

166

____

____

3.5

____

____

3.5

____

3.5

____

____

____

____

7.5

____

2.2

2.2

____

____

____

1.7

1.7

1.7

1.7

____

133

____

____

4.2

1
1

____

____

4.2

0

____

4.2

____

____

____

____

10

____

3.2

3.2

____

1
1

____

0

____

2.0

2.0

2.0

2.0

____

ns

100 MHz

____

____

ns
ns

5ns

____

____

ns
ns

5ns

____

ns

5ns

____

____

____

____

ns
ns
ns
ns

t

t

t

t
t
t
t
t
t
t

Adv ance /Lo ad (ADV /LD) Se tup

Tim e

1.5

Chip Enable/Select Setup Time 1.5
Byte Write Enable (BWx) Setup

Time

1.5

Clock Enab le Hold Time 0.5

Address Hold Time 0.5
Data In Ho ld Ti me 0.5
Re ad/ Write (R/W) Hol d Time 0.5

Adv ance /Lo ad (ADV /LD) Hol d Time 0.5
Chip E nable /S el ec t Hold Time 0.5
Byte Write Enable (BWx) Hold Time 0.5

____

____

____

____

____

____

____

____

____

____

1.5

1.5

1.5

0.5

0.5

0.5

0.5

0.5

0.5

0.5

____

____

____

____

____

____

____

____

____

____

1.7

1.7

1.7

0.5

0.5

0.5

0.5

0.5

0.5

0.5

____

____

____

____

____

____

____

____

____

____

2.0

2.0

2.0

0.5

0.5

0.5

0.5

0.5

0.5

0.5

____

____

____

____

____

____

____

____

____

____

ns

ns

ns

ns
ns
ns
ns
ns
ns
ns

NOTES:

1. tF = 1/tCYC.

2. Measured as HIGH above 0.6VDDQ and LOW below 0.4VDDQ.

3. Transition is measured ±200mV from steady-state.

4. These parameters are guaranteed with the AC load (Figure 1) by device characterization. They are not production tested.

5. To avoid bus contention, the output buffers are designed such that tCHZ (device turn-off) is about 1ns faster than tCLZ (device turn-on) at a given temperature and voltage.
The specs as shown do not imply bus contention because tCLZ is a Min. parameter that is worse case at totally different test conditions (0 deg. C, 3.465V) than tCHZ,
which is a Max. parameter (worse case at 70 deg. C, 3.135V).

6.4216

IDT71V2556, IDT71V2558, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs
with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges

Timing Waveform of Read Cycle

(1,2,3,4)

C
D
C

t

around
raps

urst W
(B

inates

high, elim

N
E
C

(

Z
H
C

t

)

2

(A
Q

)

3
2+

initialstate)

(A

to

Q

)

2
+
2

(A
Q

edge)
clock

)

2
2+

(A
Q

current L-H

D
C

t

)

2)

1
2+

2(A

(A

O

Q

6
0

drw
4875

ead
R

ipeline

urst P
B

C
D

L
C

t

C
Y
C

t

H

LK
C

C

t

E
H

t

E
S

t

V
D
A
H

t

W
H

t

W
S

t

V
D
A
S

t

N
E
C

/LD
V
D
A

A
H

t

2
A

A
S

t

1
A

W

/
R

S
S
E
R
D
D
A

C
H

t

C
S

t

(2)

2

E
C

,

1

E
C

4

W
B

-

1

W
B

C

)

t

2)

2

(A

1(A

Q

O

D
C

t

)

1

(A
Q

Z
L
C

t

E
O

T
U
O

A
T
A
D

ipeline
P

ead

ipeline

R

P

,

ead
R

of the base address A2, etc. where address bits A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input.

NOTES:

1. Q (A1) represents the first output from the external address A1. Q (A2) represents the first output from the external address A2; Q (A2+1) represents the next output data in the burst sequence

loaded into the SRAM.

2. CE2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH.

3. Burst ends when new address and control are loaded into the SRAM by sampling ADV/LD LOW.

4. R/W is don't care when the SRAM is bursting (ADV/LD sampled HIGH). The nature of the burst access (Read or Write) is fixed by the state of the R/W signal when new address and control are

6.42

17

IDT71V2556, IDT71V2558, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs
with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges

Timing Waveform of Write Cycles

(1,2,3,4,5)

around
raps

urst W
(B

inates

high, elim

N
E
C

(

)

2

(A
D

)

3
2+

A

(
D

initial state)
to

)

+2

D

2

H

A

t

(
D

D
S

t

edge)
clock

)

1

current L-H

2+

(A
D

07
drw

4875

rite
W

ipeline

urstP
B

L
C

t

C
Y
C

t

H
C

t

E
H

t

E
S

t

K
L
C

V
D
A
H

t

W
H

t

W
S

t

V
D
A
S

t

N
E
C

D

/L
V
D
A

A
H

t

2

A

A
S

t

1

A

/W

R

S
S
E
R
D
D
A

C
H

t

C
S

t

)
(2

2

E
C

1,

E
C

B
H

t

B
S

t

4

W
B

­1

W
B

E
O

)

2

(A
D

,

D
H

t

)

1

D

(A

S

t

D

ipeline
P

IN

A
T
A
D

rite

ipeline

W

P

rite
W

loaded into the SRAM.

the base address A2, etc. where address bits A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input.

NOTES:

1. D (A1) represents the first input to the external address A1. D (A2) represents the first input to the external address A2; D (A2+1) represents the next input data in the burst sequence of

2. CE2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH.

3. Burst ends when new address and control are loaded into the SRAM by sampling ADV/LD LOW.

the actual data is presented to the SRAM.

4. R/W is don't care when the SRAM is bursting (ADV/LD sampled HIGH). The nature of the burst access (Read or Write) is fixed by the state of the R/W signal when new address and control are

5. Individual Byte Write signals (BWx) must be valid on all write and burst-write cycles. A write cycle is initiated when R/W signal is sampled LOW. The byte write information comes in two cycles before

6.4218

IDT71V2556, IDT71V2558, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs
with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges

Timing Waveform of Combined Read and Write Cycles

9

A

8

A

)

7

A

6

A

5

(A
D

)

4

(A
D

(1,2,3)

)

7

(A
Q

)

6

(A
Q

08
drw

4875

,

,

ead
R

C
D
C

t

5

A

L
C

t

C
Y
C

t

H
C

t

E
H

t

E
S

t

V
D
A
H

t

W
H

t

W
S

t

V
D
A
S

t

4

A

3

A

A
H

t

A
S

t

C
H

t

2

A

C
S

t

1

A

B
H

t

B
S

t

D
H

t

D
S

t

rite
W

)

2

(A
D

rite
W

)

3

(A
Q

LZ
C

t

ead
R

Z
H
C

t

)

1

(A
Q

D
C

t

ead
R

LK
C

(2)

N
E
C

/LD
V
D
A

/W
R

S
S
E
R
D
D
A

2

E

, C

1

E
C

6.42

19

4

W

- B

1

W
B

E
O

IN

A
T
A
D

T
U
O

A
T
A
D

NOTES:

cycles before the actual data is presented to the SRAM.

1. Q (A1) represents the first output from the external address A1. D (A2) represents the input data to the SRAM corresponding to address A2.

2. CE2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH.

3. Individual Byte Write signals (BWx) must be valid on all write and burst-write cycles. A write cycle is initiated when R/W signal is sampled LOW. The byte write information comes in two

IDT71V2556, IDT71V2558, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs
with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges

Timing Waveform of CEN Operation

5

A

4

A

3

A

(1,2,3,4)

09

)

drw

3

(A

4875

Q

D

)

H

2

t

(A

D

D

S

t

Z

C

H

D

C

t

C

t

)

1

(A
Q

,

L
C

t

V
D
A

H
C
Y
C

t

H
C

t

E
H

t

E
S

t

K
L

C

t

W
H

t

W
S

t

V
D
A

tS

N
E
C

D

/L
V
D
A

A
H

t

A
S

t

/W
R

C
H

t

2

A

C
S

t

1

A

S
S
E
R
D
D
A

B

)

H

2

t

(A

B

B

S

t

(2)

2

E
C

,

1

E
C

4

W
B

­1

W
B

E

IN

O

A
T
A
D

)

1

(A
Q

D
C

t

LZ
C

t

T
U
O

A
T
A
D

NOTES:

internal registers in the SRAM will retain their previous state.

1. Q (A1) represents the first output from the external address A1. D (A2) represents the input data to the SRAM corresponding to address A2.

2. CE2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH.

the actual data is presented to the SRAM.

3. CEN when sampled high on the rising edge of clock will block that L-H transition of the clock from propogating into the SRAM. The part will behave as if the L-H clock transition did not occur. All

4. Individual Byte Write signals (BWx) must be valid on all write and burst-write cycles. A write cycle is initiated when R/W signal is sampled LOW. The byte write information comes in two cycles before

6.4220

IDT71V2556, IDT71V2558, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs
with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges

Timing Waveform of CS Operation

5

A

4

A

(1,2,3,4)

0
1

drw
75

48

,

)

4

(A
Q

D

)

H

3

t

(A

D

D

S

t

Z
H

C

C

D
L
C

t

C
Y
C

t

H
C

t

E
H

t

E
S

t

K
L
C

V
D
A
H

t

W
H

t

W
S

t

V
D
A
S

t

N
E
C

LD

/
V
D
A

W

/
R

3

A

A
H

t

A
S

t

C
H

t

2

A

C
S

t

1
A

S
S
E
R
D
D
A

(2)

B
H

t

B
S

t

E2
C

E1,
C

W4
B

-

W1
B

E
O

t

IN

A
T
A
D

)

2

C

t

(A
Q

)

1

(A
Q

D

Z

C

L

t

C

t

T
U
O

A
T
A
D

NOTES:

internal registers in the SRAM will retain their previous state.

1. Q (A1) represents the first output from the external address A1. D (A3) represents the input data to the SRAM corresponding to address A3.

2. CE2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH.

the actual data is presented to the SRAM.

3. CEN when sampled high on the rising edge of clock will block that L-H transition of the clock from propogating into the SRAM. The part will behave as if the L-H clock transition did not occur. All

4. Individual Byte Write signals (BWx) must be valid on all write and burst-write cycles. A write cycle is initiated when R/W signal is sampled LOW. The byte write information comes in two cycles before

6.42

21

IDT71V2556, IDT71V2558, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs

3

)

x

Symbol

Parameter

Min.

Max .

Units

JCYC

JCH

JCL

JR

JF

JRST

JRSR

JCD

JDC

JS

JH

Register Name

Bit S ize

with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges

JTAG Interface Specification (SA Version only)

JCYC

t

t

JCL

t

JR

JCH

t

TCK

JF

t

Device Inputs

(1)

/

TDI/TMS

JDC

JStJH

t

Device Outputs

NOTES:

1. Device inputs = All device inputs except TDI, TMS and TRST.

2. Device outputs = All device outputs except TDO.

3. During power up, TRST could be driven low or not be used since the JTAG circuit resets automatically. TRST is an optional JTAG reset.

(2)

TDO

TRST

/

JRSR

t

(

JRST

t

t

JCD

t

JTAG AC Electrical

Characteristics

t

t
t

t
t

t

t

t
t

t
t

NOTES:

1. Guaranteed by design.

2. AC Test Load (Fig. 1) on external output signals.

3. Refer to AC Test Conditions stated earlier in this document.

4. JTAG operations occur at one speed (10MHz). The base device may run at any speed specified in this datasheet.

JTAG Clock Input Period 100

JTAG Clock HIGH 40

JTAG Clock Low 40

JTAG Clock Rise Time

JTAG Clock Fall Time

JTAG Reset Recovery 50

JTAG Data Output

JTAG Data Output Ho ld 0

(1,2,3,4)

____

____

JTAG Reset 50

____

JTAG Setup 25

JTAG Hold 25

____

____

____

(1)

5

(1)

5

____

____

20 ns

____

____

____

I4875 tbl 01

Scan Register Sizes

ns
ns
ns
ns
ns
ns
ns

ns
ns
ns

Instruc tion (IR) 4
Bypass (BYR) 1
JTAG Id e nti fic ati o n (J IDR) 32
Bound ary Sc an (BSR) No te (1)

NOTE:

1. The Boundary Scan Descriptive Language (BSDL) file for this device is available
by contacting your local IDT sales representative.

M4875 drw 01

I4875 tbl 03

6.4222

IDT71V2556, IDT71V2558, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs

Instruction Field

Value

Description

Instru ction

Description

OPCODE

EX T EST

Forces contents of the bound ary scan cells onto the device

o

utputs

(1)

.

Places the boundary scan register (BSR) between TDI and TDO.

0000

SAMPLE/PRELOAD

Places the boundary scan register (BSR) between TDI and TDO.

SAMPLE allows data from device inputs

(2)

and outputs

(1)

to be captured

in the b o undary sc an ce lls and s hifted se riall y thro ugh TDO. PRE LOAD

allows d ata to be input serially into the bo undary scan cells via the TDI.

0001

DEVICE_ID

Load s the J TAG ID re g is te r (JIDR) with the v e ndor ID co d e and pl ac es

the register between TDI

and TDO.

0010

HIGHZ

Places the bypass register (BYR) b etween TDI and TDO. Forces all

device output drivers to a High-Z state.

0011

RESERVED

Se v er al c om b inati ons are re s e rv ed . Do no t use c od e s o the r than tho se

id e ntifie d for EXTEST, SA MPLE / PRELOA D, DEVICE_ID, HIGHZ, CLAM P,

VALIDATE and B YPAS S ins tructio ns.

0100

RESERVED

0101

RESERVED

0110

RESERVED

0111

CLAMP

Uses BYR. Forces contents of the bound ary scan cells onto the device

outp uts. Places the bypass registe r (BYR) between TDI and TDO.

1000

RESERVED

Same as ab o ve .

1001

RESERVED

1010

RESERVED

1011

RESERVED

1100

VALIDAT E

Automatically loaded into the instruction register whenever the TAP

co ntrol le r pass es throug h the CAP TURE-IR state. The lo wer two b its '01'

are mand ate d b y the IEE E std . 1149.1 s pe c ifi cati on.

1101

RESERVED

Same as ab o ve .

1110

BYP ASS

The BYPASS instruction is used to truncate the boundary scan register

as a sing le bit in le ng th.

1111

I4875 tbl 04

with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges

JTAG Identification Register Definitions (SA Version only)

Revision Number (31:28) 0x2 Reserved for version number.
IDT Devi ce ID (27:12) 0x210, 0x212 Defines IDT part numbe r 71V2556SA and 71V2558SA, res p ec tive ly.
IDT JEDEC ID (11:1) 0x33 Allows unique identification of device vendor as IDT.
ID Register Indicator Bit (Bit 0) 1 Indicates the presence of an ID register.

I4875 tbl 02

Available JTAG Instructions

NOTES:

1. Device outputs = All device outputs except TDO.

2. Device inputs = All device inputs except TDI, TMS, and TRST.

6.42

23

IDT71V2556, IDT71V2558, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs
with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges

100 Pin Plastic Thin Quad Flatpack (TQFP) Package Diagram Outline

6.4224

IDT71V2556, IDT71V2558, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs
with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges

119 Ball Grid Array (BGA) Package Diagram Outline

6.42

25

IDT71V2556, IDT71V2558, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs
with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges

165 Fine Pitch Ball Grid Array (fBGA) Package Diagram Outline

6.4226

IDT71V2556, IDT71V2558, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs
with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges

Timing Waveform of OE Operation

(1)

OE

OE

t

OHZ

DATA

t

OUT

OLZ

t

Valid

NOTE:

1. A read operation is assumed to be in progress.

Ordering Information

IDT XXXX

Device

Type

XX

Power

XX

SpeedXXPackage

X

Process/

Temperature

Range

Blank
I

PF**
BG
BQ

200*
166
133
100

S
SA

Commercial (0°C to +70°C)
Industrial (-40°Cto +85°C)

100-pin Plastic Thin Quad Flatpack (TQFP)
119 Ball Grid Array (BGA)
165 Fine Pitch Ball Grid Array (fBGA)

ClockFrequencyin Megahertz

Standard Power
Standard Power with JTAG Interface

4875 drw 11

,

,

6.42

27

IDT71V2556
IDT71V2558

*Available for commercial temperature range only.
** JTAG (SA version) is not available with 100-pin TQFP package

128Kx36 Pipelined ZBT SRAM with 2.5V I/O
256Kx18 Pipelined ZBT SRAM with 2.5V I/O

4875 drw 12

IDT71V2556, IDT71V2558, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs
with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges

Datasheet Document History

6/30/99 Updated to new format
8/23/99 Added Smart ZBT functionality

Pp. 4, 5 Added Note 4 and changed Pins 38, 42, and 43 to DNU
Pg. 6 Changed U2–U6 to DNU
Pg. 14 Added Smart ZBT AC Electrical Characteristics
Pg. 15 Improved tCD and tOE(MAX) at 166MHz

Revised tCHZ(MIN) for f ≤ 133 MHz
Revised tOHZ (MAX) for f ≤ 133 MHz
Improved tCH, tCL for f ≤ 166 MHz

Improved setup times for 100–200 MHz
Pg. 22 Added BGA package diagrams
Pg. 24 Added Datasheet Document History

10/4/99 Pg. 14 Revised AC Electrical Characteristics table

Pg. 15 Revised tCHZ to match tCLZ and tCDC at 133MHz and 100MHz

12/31/99 Removed Smart functionality

Added Industrial Temperature range offerings at the 100 to 166MHz speed grades.

04/30/00 Pg. 5,6 Add clarification note to Recommended Temperature Ratings and Absolute Max Ratings

table; Add note to TQFP Pin Configurations
Pg. 6 Add BGA Capacitance table
Pg. 7 Add note to BGA Pin Configurations
Pg. 21 Insert TQFP Package Diagram Outline

05/26/00 Add new package offering, 13 x 15mm 165fBGA

Pg. 23 Correct 119 BGA Package Diagram Outline

07/26/00 Pg. 5,6,7 Add zz, sleep mode reference note to TQFP, BG119 and BQ165 pinouts

Pg. 8 Update BQ165 pinout
Pg. 23 Update BG119 package diagram outlines

10/25/00 Remove Preliminary Status

Pg. 8 Add note to pin N5, BQ165 pinout reserved for JTAG TRST

5/20/02 Pg. 1-8,15,22,23,27 Added JTAG "SA" version functionality & updated ZZ pin descriptions and notes.
10/15/04 Pg.7 Updated pin configuration for the 119 BGA - reordered I/O signals on P6, P7 (128K x 36)

and P7, N6, L6, K7, H6, G7, F6, E7, D6 (256K x 18).

CORPORATE HEADQUARTERS for SALES: for Tech Support:

2975 Stender Way 800-345-7015 or 408-727-6116 [e-mail]
Santa Clara, CA 95054 fax: [phone]

www.idt.com

ZBT and ZeroBus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola Inc.

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

6.4228