Datasheet IDT71P72104 Datasheet (IDT)

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Features

◆ 18Mb Density (2Mx8, 2Mx9, 1Mx18, 512kx36)

◆ Separate, Independent Read and Write Data Ports

- Supports concurrent transactions

◆ Dual Echo Clock Output

◆ 2-Word Burst on all SRAM accesses

◆ DDR (Double Data Rate) Multiplexed Address Bus

- One Read and One Write request per clock cycle

◆ DDR (Double Data Rate) Data Buses

- Two word burst data per clock on each port

- Four word transfers per clock cycle (2 word
bursts on 2 ports)

◆ Depth expansion through Control Logic

◆ HSTL (1.5V) inputs that can be scaled to receive signals

from 1.4V to 1.9V.

◆ Scalable output drivers

- Can drive HSTL, 1.8V TTL or any voltage level
from 1.4V to 1.9V.

- Output Impedance adjustable from 35 ohms to 70
ohms

◆ 1.8V Core Voltage (VDD)

◆ 165-ball, 1.0mm pitch, 13mm x 15mm fBGA Package

◆ JTAG Interface

18Mb Pipelined
QDR™II SRAM
Burst of 2

Description

The IDT QDRIITM Burst of two SRAMs are high-speed synchronous
memories with independent, double-data-rate (DDR), read and write
data ports. This scheme allows simultaneous read and write access for
the maximum device throughput, with two data items passed with each
read or write. Four data word transfers occur per clock cycle, providing
quad-data-rate (QDR) performance. Comparing this with standard SRAM
common I/O (CIO), single data rate (SDR) devices, a four to one in­crease in data access is achieved at equivalent clock speeds. Consider­ing that QDRII allows clock speeds in excess of standard SRAM de­vices, the throughput can be increased well beyond four to one in most
applications.

Using independent ports for read and write data access, simplifies
system design by eliminating the need for bi-directional buses. All buses
associated with the QDRII are unidirectional and can be optimized for
signal integrity at very high bus speeds. The QDRII has scalable output
impedance on its data output bus and echo clocks, allowing the user to
tune the bus for low noise and high performance.

The QDRII has a single DDR address bus with multiplexed read and
write addresses. All read addresses are received on the first half of the
clock cycle and all write addresses are received on the second half of the
clock cycle. The read and write enables are received on the first half of
the clock cycle. The byte and nibble write signals are received on both
halves of the clock cycle simultaneously with the data they are controlling
on the data input bus.

The QDRII has echo clocks, which provide the user with a clock

Advance

Information
IDT71P72204
IDT71P72104
IDT71P72804
IDT71P72604

Functional Block Diagram

(Note1)

BW

(Note1)

D

(Note2 )

SA

R

W

(Note3)

x

K

K

C

C

DATA

REG

ADD
REG

CTRL

LOGIC

CLK
GEN

Notes

1) Represents 8 data signal lines for x8, 9 signal lines for x9, 18 signal lines for x18, and 36 signal lines for x36

2) Represents 20 address signal lines for x8 and x9, 19 address signal lines for x18, and 18 address signal lines for x36.

3) Represents 1 signal line for x9, 2 signal lines for x18, and four signal lines for x36. On x8 parts, the BW is a “nibble write” and there are 2
signal lines.

4) Represents 16 data signal lines for x8, 18 signal lines for x9, 36 signal lines for x18, and 72 signal lines for x36.

©2003 Integrated Device Technology, Inc. “QDR SRAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress Semiconductor, IDT, and Micron Technology, Inc. “

DATA

REG

WRITE DRIVER

(Note2)

E
D
O
C
E
D

D
A
E

/R
E

IT
R

W

SELECT OUTPUT CONTROL

(Note1)

18M

MEMORY

ARRAY

1

S
P

M
A

E
S
N
E
S

(Note4)

G
E
R

T
U
P
T
U
O

(Note4)

6109 drw 16

T
C
E
L
E
S

T
U
P
T
U
O

(Note1)

Q

CQ

CQ

MAY 2004

DSC-6109/0C

IDT71P72204 (2M x 8-Bit), 71P72104 (2M x 9-Bit), 71P72804 (1M x 18-Bit) 71P72604 (512K x 36-Bit)
18 Mb QDR II SRAM Burst of 2 Commercial Temperature Range

Advance Information

that is precisely timed to the data output, and tuned with matching imped­ance and signal quality. The user can use the echo clock for down­stream clocking of the data. Echo clocks eliminate the need for the user
to produce alternate clocks with precise timing, positioning, and signal
qualities to guarantee data capture. Since the echo clocks are generated
by the same source that drives the data output, the relationship to the data
is not significantly affected by voltage, temperature and process, as would
be the case if the clock were generated by an outside source.
All interfaces of the QDRII SRAM are HSTL, allowing speeds beyond
SRAM devices that use any form of TTL interface. The interface can be
scaled to higher voltages (up to 1.9V) to interface with 1.8V systems if
necessary. The device has a VDDQ and a separate Vref, allowing the
user to designate the interface operational voltage, independent of the
device core voltage of 1.8V VDD. The output impedance control allows
the user to adjust the drive strength to adapt to a wide range of loads and
transmission lines.

The device is capable of sustaining full bandwidth on both the input
and output ports simultaneously. All data is in two word bursts, with
addressing capability to the burst level.

Clocking

The QDRII SRAM has two sets of input clocks, namely the K, K clocks
and the C, C clocks. In addition, the QDRII has an output “echo” clock,

CQ, CQ.

The K and K clocks are the primary device input clocks. The K clock
is, used to clock in the control signals (R, W and BWx or NWx), the read
address, and the first word of the data burst during a write operation.
The K clock is used to clock in the control signals (BWx or NWx), write
address and the second word of the data burst during a write operation.
The K and K clocks are also used internally by the SRAM. In the event
that the user disables the C and C clocks, the K and K clocks will also be
used to clock the data out of the output register and generate the echo
clocks.
The C and C clocks may be used to clock the data out of the output
register during read operations and to generate the echo clocks. C and
C must be presented to the SRAM within the timing tolerances. The
output data from the QDRII will be closely aligned to the C and C input,
through the use of an internal DLL. When C is presented to the QDRII
SRAM, the DLL will have already internally clocked the first data word to
arrive at the device output simultaneously with the arrival of the C clock.

The C and second data word of the burst will also correspond.

Single Clock Mode

The QDRII SRAM may be operated with a single clock pair. C and C
may be disabled by tying both signals high, forcing the outputs and echo

clocks to be controlled instead by the K and K clocks.

DLL Operation

The DLL in the output structure of the QDRII SRAM can be used to
closely align the incoming clocks C and C with the output of the data,
generating very tight tolerances between the two. The user may disable
the DLL by holding Doff low. With the DLL of f, the C and C (or K and K
if C and C are not used) will directly clock the output register of the SRAM.
With the DLL off, there will be a propagation delay from the time the clock
enters the device until the data appears at the output.

Echo Clock

The echo clocks, CQ and CQ, are generated by the C and C clocks
(or K, K if C, C are disabled). The rising edge of C generates the rising
edge of CQ, and the falling edge of CQ. The rising edge of C generates
the rising edge of CQ and the falling edge of CQ. This scheme improves
the correlation of the rising and falling edges of the echo clock and will

improve the duty cycle of the individual signals.
The echo clock is very closely aligned with the data, guaranteeing that
the echo clock will remain closely correlated with the data, within the
tolerances designated.

Read and Write Operations

QDRII devices internally store the two words of the burst as a single,
wide word and will retain their order in the burst. There is no ability to
address to the single word level or reverse the burst order; however, the
byte and nibble write signals can be used to prevent writing any indi-

vidual bytes, or combined to prevent writing one word of the burst.

Read operations are initiated by holding the read port select (R) low ,

and presenting the read address to the address port during the rising
edge of K which will latch the address. The data will then be read and will
appear at the device output at the designated time in correspondence

with the C and C clocks.
Write operations are initiated by holding the write port select (W) low
and designating with the Byte Write inputs (BWx) which bytes are to be
written (or NWx on x8 devices). The first word of the data must also be
present on the data input bus D[X:0]. Upon the rising edge of K the first
word of the burst will be latched into the input register. After K has risen,
and the designated hold times observed, the second half of the clock
cycle is initiated by presenting the write address to the address bus
SA[X:0], the BWx (or NWx) inputs for the second data word of the burst,
and the second data item of the burst to the data bus D[X:0]. Upon the
rising edge of K, the second word of the burst will be latched, along with
the designated address. Both the first and second words of the burst will
then be written into memory as designated by the address and byte write
enables.

Output Enables

The QDRII SRAM automatically enables and disables the Q[X:0]
outputs. When a valid read is in progress, and data is present at the
output, the output will be enabled. If no valid data is present at the output
(read not active), the output will be disabled (high impedance). The
echo clocks will remain valid at all times and cannot be disabled or turned
off. During power-up the Q outputs will come up in a high impedance

state.

Programmable Impedance

An external resistor, RQ, must be connected between the ZQ pin on
the SRAM and Vss to allow the SRAM to adjust its output drive imped­ance. The value of RQ must be 5X the value of the intended drive
impedance of the SRAM. The allowable range of RQ to guarantee
impedance matching with a tolerance of +/- 10% is between 175 ohms
and 350 ohms, with VDDQ = 1.5V. The output impedance is adjusted

every 1024 clock cycles to correct for drifts in supply voltage and tem­perature. If the user wishes to drive the output impedance of the SRAM

to it’s lowest value, the ZQ pin may be tied to VDDQ.

6.422

IDT71P72204 (2M x 8-Bit), 71P72104 (2M x 9-Bit), 71P72804 (1M x 18-Bit) 71P72604 (512K x 36-Bit)

0

1BW2

3

0

0

0

DDQ

Advance Information

18 Mb QDR II SRAM Burst of 2 Commercial Temperature Range

Pin Definitions

Symbol Pin Function Description

Data input signals, sampled on the rising edge of K and K clocks during valid write operations

2M x 8 -- D[7: 0]
2M x 9 -- D[8: 0]

1M x 18 -- D[17:0]

512 K x 36 -- D[35:0]

Byte Write Select 0, 1, 2, and 3 are active LOW. Sampled on the rising edge of the K and again on the rising
edge of K clocks d uring write ope rations. Used to select which byte is written into the device during the
curre nt p o rtion of the wri te operat io n s. By te s no t writ ten remain unalte re d . Al l the by te write s are s amp l ed o n

the same edg e as the data. Desele cting a Byte Write Sele ct will cause the corresp ond ing by te of data to be

ig n o re d an d no t wri tte n in to th e d e v ice .

2M x 9 -- BW

1M x 18 -- BW

512K x 36 -- BW

co ntro ls D[ 8: 0]

co ntro ls D[ 8: 0] a nd BW1 controls D[17:9]

controls D[8:0], BW1 controls D[17:9], BW2 co ntro ls D[ 26: 18] and BW3 co ntro ls D[ 35: 27]

Nibble Write Select 0 and 1 are active LOW. Available only on x8 bit parts instead of Byte Write Selects.
Sampled on the rising edge of the K and K clocks during write operations. Used to select which nibble is

written into the device during the current portion of the write operations. Nibbles not written remain unaltered.
All the nibble writes are sampled on the same edge as the data. Deselecting a Nibble Write Select will cause
the corresponding nibble of data to be ignored and not written in to the device.

D[X:0]

BW

BW

,
, BW

NW0, NW 1

Input

Sy nchronous

Input

Synchro nous

Input

Synchronous

SA

Q[X: 0]

W

R

C

C

Input

Synchro nous

Output

Synchro nous

Input

Synchronous

Input

Synchronous

Inp ut Cl o c k

Inp ut Cl o c k

K Input Clock

Address Inputs. Read addresses are sampled on the rising edge of K clock during active read operations.

Write addresses are sampled on the rising edge of K cl ock during active write op erations. These address
inputs are multiplxed, so that both a read and write operation can occur on the same clock cycle. These
inputs are ignored when the appropriate port is deselected.

Data Output signals. These pins drive out the requested d ata during a Read operation. Valid data is driven out
on the rising edge of both the C and C clocks during Read operations or K and K when operating in single
clock mode. When the Read port is deselected, Q[X:0] are automatically three-state d.

Write Control Logic active Low. Sampled on the rising edge of the p ositive input clock (K). When asserted
active, a write ope ration in initiated. Deasse rting will des ele ct the Write port. Desele cting the Write port will cause
D[X:0] to be ignored.

Read Control Logic, active LOW. Sampled on the rising edge o f Positiv e Input Clock (K). When active, a
Read operation is initiated. Deasserting will cause the Read p ort to be d eselected. When deselected, the
pending access is allowed to complete and the output drivers are automaticall y three-stated following the next
rising edg e of the C clock. Each read access consists of a burst of two sequential transfer.

Positive Output Clock Input. C is used in conjunction with C to clock out the Rea d data fr o m the devi ce . C
and C can be used together to de skew the flight time s of various devices on the board back to the controller.
See applic ation example for further d etails.

Negative Output Clock Input. C is used in conjunction with C to clock out the Read data from the device. C
and C can be used together to deskew the flight times of various de vices on the bo ard back to the controller.
See applic ation example for further d etails.

Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the device and to
drive out data through Q[X:0] whe n in single clock mode. All accesses are initiated on the rising edge of K.

K Inp ut Cl o c k

CQ

CQ,

Output Cl o ck

ZQ Inp u t

Negati ve Input Clock Input. K is used to capture synchronous inputs being presented to the device and to
drive out data through Q[X:0] when in single clock mode.

Synchro nous Echo clock outputs. The rising edges of these outputs are tightly matched to the synchronous
data outputs and can be use d as a d ata valid ind ication. Thes e signals are free running and do not stop when

the o utput d ata is tr i-s ta te d .

Outp ut I mp e danc e M atc hi ng Inp u t. This input i s us e d to tu ne th e d e v ic e o u tp uts to the s y s te m d ata b u s
imp e d anc e . Q[X: 0] ou tput i mp e d anc e is se t to 0 .2 x RQ, whe re RQ i s a re si s tor c o nne c te d b e twee n ZQ and
ground. Alternate ly, this pin can be connected directly to V

, which enables the minimum impedance mode.

This pin cannot be connec ted directly to GND or left unconnected.

6.42

3

6109 tbl 02a

IDT71P72204 (2M x 8-Bit), 71P72104 (2M x 9-Bit), 71P72804 (1M x 18-Bit) 71P72604 (512K x 36-Bit)

DD

DD

Advance Information

18 Mb QDR II SRAM Burst of 2 Commercial Temperature Range

Pin Definitions continued

Symbol Pin Function Description

DLL Tur n Off. Whe n l o w th is i np u t wi ll tur n off t he DLL in s id e the d e v i c e . The A C ti mi n g s w ith

Doff

Input

TDO Output TDO pin for JTAG

TCK Inp ut TCK pi n fo r J TAG.

the DLL turned off will be different from those listed in this data sheet. There will be an
increased propagation delay from the incidence of C and C to Q, o r K and K to Q as
configured. The propagation delay is not a tested paramete r, but will be similar to the
propagation delay of othe r SRAM devices in this speed grade.

TDI Input TDI pin fo r JTAG. An internal resis tor will pull TDI to V

TMS Input TMS p in for JTA G. An internal re sis tor will pull TMS to V

when the pin is unc onnecte d .

when the pi n is unc onnected.

NC No Connect No connec ts inside the package. Can be tied to any voltage level

V

REF

V

DD

V

SS

V

DDQ

Input

Reference

Power

Supply

Gro und Ground fo r the device. Should be co nnected to ground of the system.

Power

Supply

Re fe re n ce Vo lta g e i np ut . Sta tic i np u t us e d to s e t the refe re nc e l e v el for HSTL inputs an d
Outputs as wel l as A C me as ure me nt p o i nts.

Power supply inputs to the c ore of the device. Should be connected to a 1.8V power
supply.

Power supply for the outputs of the device. Should be connected to a 1.5V power supply

for HSTL or scaled to the desired output voltage.

6109 tbl 02b

6.424

IDT71P72204 (2M x 8-Bit), 71P72104 (2M x 9-Bit), 71P72804 (1M x 18-Bit) 71P72604 (512K x 36-Bit)

SS/

SS/

SS

SS

SSVSSVSSVSSVSS

DDQVSSVSSVSSVDDQ

DDQVDDVSSVDDVDDQ

DDQVDDVSSVDDVDDQ

REFVDDQVDDQVDDVSSVDDVDDQVDDQVREF

DDQVDDVSSVDDVDDQ

DDQVDDVSSVDDVDDQ

DDQVSSVSSVSSVDDQ

SSVSSVSSVSSVSS

SS

SS

18 Mb QDR II SRAM Burst of 2 Commercial Temperature Range

Advance Information

Pin Configuration 2M x 8

1234567891011

A

CQ

V
SA

B

C

D

E

F

G

H

J

K

L

NC NC NC SA NC K

NC NC NC V

NC D

NC NC Q

NC NC NC V

NC D

Doff

V

NC NC NC V

NC NC NC V

NC Q

(2)

4

5

6

SA

NC V

4

Q

5

D

6

WNW1K

SA SA SA V

V

V

V

NW

NC

R

SA NC NC Q

0

SA V

NC NC D

NC NC NC

NC D

NC NC NC

NC NC NC

NC Q

NC NC NC

NC NC Q

SA

CQ

(1)

3

3

Q

2

2

ZQ

D

1

1

0

M

N

P

R

NC NC NC V

NC D

NC NC Q

7

NC V

7

TDO TCK SA SA SA

NOTES:

1. A10 is reserved for the 36Mb expansion address.

2. A2 is reserved for the 72Mb expansion address.

NC NC D

SA SA SA V

NC NC NC

SA SA C SA SA NC NC NC

C

SA SA SA TMS TDI

6109 tbl 12

165-ball FBGA Pinout

TOP VIEW

0

6.42

5

IDT71P72204 (2M x 8-Bit), 71P72104 (2M x 9-Bit), 71P72804 (1M x 18-Bit) 71P72604 (512K x 36-Bit)

SS/

SS/

SS

SS

SSVSSVSSVSSVSS

DDQVSSVSSVSSVDDQ

DDQVDDVSSVDDVDDQ

DDQVDDVSSVDDVDDQ

REFVDDQVDDQVDDVSSVDDVDDQVDDQVREF

DDQVDDVSSVDDVDDQ

DDQVDDVSSVDDVDDQ

DDQVSSVSSVSSVDDQ

SSVSSVSSVSSVSS

SS

SS

18 Mb QDR II SRAM Burst of 2 Commercial Temperature Range

Advance Information

Pin Configuration 2M x 9

1234567891011

A

CQ

V

SA

B

C

D

E

F

G

H

J

K

L

NC NC NC SA NC K

NC NC NC V

NC D

NC NC Q

NC NC NC V

NC D

Doff

V

NC NC NC V

NC NC NC V

NC Q

4

5

6

(2)

SA

NC V

4

Q

5

D

6

W

NC

K

SA SA SA V

NC

BW

R

SA V

SA

(1)

SA NC NC Q

NC NC D

CQ

3

3

NC NC NC

V

NC D

Q

2

2

NC NC NC

V

NC NC NC

ZQ

NC Q

D

1

1

NC NC NC

V

NC NC Q

0

M

N

P

R

NC NC NC V

NC D

7

NC NC Q

TDO TCK SA SA SA

NOTES:

1. A10 is reserved for the 36Mb expansion address.

2. A2 is reserved for the 72Mb expansion address.

NC V

7

SA SA C SA SA NC D

SA SA SA V

C

165-ball FBGA Pinout

TOP VIEW

6.426

NC NC D

NC NC NC

Q

8

SA SA SA TMS TDI

6109 tbl 12a

0

8

IDT71P72204 (2M x 8-Bit), 71P72104 (2M x 9-Bit), 71P72804 (1M x 18-Bit) 71P72604 (512K x 36-Bit)

9D9

0

8

10

7D8

11Q10

7

11

6Q6

12D12

DDVSS

5

13Q13

5

14

4D4

14

SS

3Q3

15D15

SSVSS

2

16

1D2

17Q16

1

17

0Q0

Advance Information

18 Mb QDR II SRAM Burst of 2 Commercial Temperature Range

Pin Configuration 1M x 18

1234567891011

SS/

A

CQ

V

SA

B

NC Q

NC/

(3)

SA

WBW1K

(1)

SA NC K

NC

BW

R

SA VSS/

SA

(2)

SA NC NC Q

CQ

SS

C

D

E

F

G

H

J

K

L

M

N

NC NC D

NC D

NC NC Q

NC Q

NC D

REF

Doff

V

NC NC D

NC NC Q

NC Q

NC NC D

NC D

DDQ

V

V

SS

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

SS

V

SS

V

SA SA SA V

SS

V

SS

V

V

DD

V

DD

V

DD

V

DD

V

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

V

SS

V

SS

V

SS

V

DD

V

DD

V

DD

V

DD

V

DD

V

SS

V

SS

V

SA SA SA V

SS

SS

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

SS

V

SS

NC Q

NC NC D

NC D

NC NC Q

NC NC D

DDQ

V

REF

V

NC Q

NC D

NC NC Q

NC Q

NC NC D

ZQ

P

R

NC NC Q

TDO TCK SA SA SA

SA SA C SA SA NC D

C

SA SA SA TMS TDI

6109 tbl 12b

165-ball FBGA Pinout

TOP VIEW

NOTES:

1. A3 is reserved for the 36Mb expansion address.

2. A10 is reserved for the 72Mb expansion address. This must be tied or driven to VSS on the 1M x 18 QDRII Burst of 2 (71P72804) devices.

3. A2 is reserved for the 144Mb expansion address. This must be tied or driven to VSS on the 1M x 18 QDRII Burst of 2 (71P72804) devices.

6.42

7

IDT71P72204 (2M x 8-Bit), 71P72104 (2M x 9-Bit), 71P72804 (1M x 18-Bit) 71P72604 (512K x 36-Bit)

27Q18D18

17Q17Q8

27Q28D19

16Q7D8

28D20Q19

16D15D7

29D29Q20

15D6Q6

30Q21D21

DDQD14Q14Q5

30D22Q22

DD

13D13D5

REFVDDQ

DD

DDQVREF

31Q31D23

DD

12Q4D4

32D32Q23

DD

12D3Q3

24D24

11Q11Q2

33Q34D25

10Q1D2

34D26Q25

SSQ10D9D1

35D35Q26

9D0Q0

Advance Information

18 Mb QDR II SRAM Burst of 2 Commercial Temperature Range

Pin Configuration 512K x 36

1234567891011

SS/

A

CQ

V

SA

B

C

D

E

F

G

H

J

K

L

Q

D

D

Q

Q

D

Doff

D

Q

Q

V

33

Q

NC/

(4)

SA

WBW2KBW1R

(2)

SA

V

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

BW

SS

SA SA SA V

SS

SS

V

SS

V

DD

V

V

V

V

V

SS

V

K

3

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

BW

V

V

V

V

V

V

V

V

SS

SS

DD

DD

DD

DD

DD

SS

0

SA D

V

DDQ

V

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

NC/

SA

SS

D

SS

Q

Q

Q

V

D

Q

D

SS/

V

(1)

SA

CQ

(3)

ZQ

SS

M

N

P

R

D

D

Q

TDO TCK SA SA SA

V

SS

V

SA SA C SA SA Q

SS

V

SS

V

SS

V

SA SA SA V

C

SA SA SA TMS TDI

SS

V

D

6109 tbl 12c

165-ball FBGA Pinout

TOP VIEW

NOTES:

1. A9 is reserved for the 36Mb expansion address.

2. A3 is reserved for the 72Mb expansion address.

3. A10 is reserved for the 144Mb expansion address. This must be tied or driven to VSS on the 512K x 36 QDRII Burst of 2 (71P72604) devices.

4. A2 is reserved for the 288Mb expansion address. This must be tied or driven to VSS on the 512K x 36 QDRII Burst of 2 (71P72604) devices.

6.428

IDT71P72204 (2M x 8-Bit), 71P72104 (2M x 9-Bit), 71P72804 (1M x 18-Bit) 71P72604 (512K x 36-Bit)

Symbol

Parameter

Conditions

Max.

Uni t

IN

DD

DDQ

CLK

O

Symbol

Rating

Value

Unit

TER M

TER M

DDQ

DD

TER M

DD

TER M

DDQ

BIAS

STG

OUT

6109 tb l 05

Signal

Symbol

Paramet er

Min.

Typ.

Max.

Unit

c

Advance Information

18 Mb QDR II SRAM Burst of 2 Commercial Temperature Range

Absolute Maximum Ratings

V

V

V

V

T
T

I

Supply Voltage on VDD with
Re s p e c t to G ND

Supply Voltage on V
Re s p e c t to G ND

Voltage on Input terminals with
re s p e ct to G N D.

Voltage on Output and I/O
te rm i na ls wi th re s p e c t to GN D.

Temperature Under Bias –55 to +125 °C
Storage Temperature –65 to +150 °C
Continuous Current into Outputs + 20 mA

with

–0.5 to + 2.9 V

–0.5 to V

–0.5 to V

-0. 5 to V

(1) (2)

+0.3 V

+0.3 V

+0.3 V

NOTES:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect
reliability.

2. VDDQ must not exceed VDD during normal operation.

Write Descriptions

(1,2)

Capacitance (TA = +25°C, f = 1.0MHz)

C

Inp ut Cap ac ita nc e

= 1.8V

V

= 1.5V

V

NOTE:

C

Clock Input Capacitance 6 pF

C

Output Capacitance 7 pF

(1)

5pF

6109 tbl 06

1. Tested at characterization and retested after any design or process change that
may affect these parameters.

Recommended DC Operating and

Temperature Conditions

Power Supp ly

DD

V

Voltage

DDQ

V

I/O Su p p ly Vol tage 1.4 1.5 1. 9 V

SS

V

Ground 0 0 0 V
Inp u t Re fe re n c e

REF

V

Vo lta ge
Ambie nt

A

T

Temperature

(1)

NOTE:

1. During production testing, the case temperature equals the ambient

temperature.

1.7 1.8 1.9 V

0.68 V

DDQ

/2 0. 95 V

025+70

61 09 tbl 04

o

BW0BW1BW2BW3NW0NW

1

Write Byte 0 L XXXXX
Write Byte 1 X L X X X X
Write Byte 2 X X L X X X
Write Byte 3 XXX LXX
Write Nibble 0 X X X X L X
Write Nibble 1 XXXXXL

NOTES:

6109 tbl 09

1) All byte write (BWx) and nibble write (NWx) signals are sampled on the
rising edge of K and again on K. The data that is present on the data bus in the
designated byte/nibble will be latched into the input if the corresponding BWx or
NWx is held low. The rising edge of K will sample the first byte/nibble of the
two word burst and the rising edge of K will sample the second byte/nibble of
the two word burst.

2) The availability of the BWx or NWx on designated devices is described in
the pin description table.

3) The QDRII Burst of two SRAM has data forwarding. A read request that is
initiated on the same cycle as a write request to the same address will produce

the newly written data in response to the read request.

6.42

9

IDT71P72204 (2M x 8-Bit), 71P72104 (2M x 9-Bit), 71P72804 (1M x 18-Bit) 71P72604 (512K x 36-Bit)

W

18 Mb QDR II SRAM Burst of 2 Commercial Temperature Range

Advance Information

Application Example

Data In

Data Out

Address

BWx/NW

MEMORY
CONTROLLER

Return CLK

Source CLK

Return

Source

CLK

CLK

R

W

x

T

V

R

T

V

V

R

R=50Ω

T

R

D

SA

VT=V

SRAM#1

WBW0BW

R

REF

SRAM #4

ZQ

Q

1

K

K

C

C

250

Ω

D

SA

WBW0BW

R

1

ZQ

Q

K

K

C

C

6109drw 20

250

Ω

R
R
R

T

V

R
R

6.4210

IDT71P72204 (2M x 8-Bit), 71P72104 (2M x 9-Bit), 71P72804 (1M x 18-Bit) 71P72604 (512K x 36-Bit)

Parameter

Symbol

Test Conditions

Min

Max

Unit

Note

Input Le akag e Curre nt

IILVDD = Max V

IN

= VSS to V

DDQ

-10

+10µA

Output Le ak age Curre nt

IOLOutput Disabled

-10

+10µA

Operating Current

(x36,x 18, x9, x 8): DDR

IDDVDD = Max,

I

OUT

= 0mA (outputs open),

Cycle Time

>

t

KHKH

Min

250MHZ-

TBDmA1

200MHZ-

TBD

167MHZ-

TBD

Standby Current: NOP

I

SB1

Device Deselected (in NOP state),

Iout = 0mA (outputs open),

f=Max,

All Inp uts

<

0.2V o r

>

VDD -0.2V

250MHZ-

TBDmA2

200MHZ-

TBD

167MHZ-

TBD

Output Hig h Vo ltag e

V

OH1

RQ = 250

IOH = -15mA

V

DDQ

/2-0.12

V

DDQ

/2+0.12V3,7

Output Low Voltag e

V

OL1

RQ = 250

IOL = 15mA

V

DDQ

/2-0.12

V

DDQ

/2+0.12V4,7

Output Hig h Vo ltag e

V

OH2IOH

= -0.1mA

V

DDQ

-0.2

V

DDQ

V5Output Low Voltag e

V

OL2IOL

= 0. 1mA

VSS0.2V6

6109 tbl 10c

Advance Information

18 Mb QDR II SRAM Burst of 2 Commercial Temperature Range

DC Electrical Characteristics Over the Operating Temperature and

Supply Voltage Range

NOTES:

1. Operating Current is measured at 100% bus utilization.

2. Standby Current is only after all pending read and write burst operations are completed.

3. Outputs are impedance-controlled. IOH = -(VDDQ/2)/(RQ/5) and is guaranteed by device characterization for 175Ω < RQ < 350 Ω. This
parameter is tested at RQ = 250Ω, which gives a nominal 50Ω output impedance.

4. Outputs are impedance-controlled. IOL = (VDDQ/2)/(RQ/5) and is guaranteed by device characterization for 175Ω < RQ < 350Ω. This
parameter is tested at RQ = 250Ω, which gives a nominal 50Ω output impedance.

5. This measurement is taken to ensure that the output has the capability of pulling to the VDDQ rail, and is not intended to be used as an
impedance measurement point.

6. This measurement is taken to ensure that the output has the capability of pulling to Vss, and is not intended to be used as an impedance
measurement point.

7. Programmable Impedance Mode.

(VDD = 1.8 ± 100mV, V DDQ = 1.4V to 1.9V)

Ω,

Ω,

6.42

11

IDT71P72204 (2M x 8-Bit), 71P72104 (2M x 9-Bit), 71P72804 (1M x 18-Bit) 71P72604 (512K x 36-Bit)

Parameter

Symbol

Value

Unit

V

I

LVD

DVD

D

D

D

1

Advance Information

18 Mb QDR II SRAM Burst of 2 Commercial Temperature Range

Input Electrical Characteristics Over the Operating Temperature and

Supply Voltage Range

PARAMETER SYMBOL MIN MAX UNIT NOTES

(VDD = 1.8 ± 100mV, VDDQ = 1.4V to 1.9V)

Input High Voltage, DC V
Input Low Voltage, DC V
Input High Voltage, AC V
Input Low Voltage, AC V

NOTES:

)V

IH (DC

IL (DC)

IH (AC)

IL ( AC )

+0.1 V

REF

-0.3 V

V

+0.2 - V 4,5

REF

-V

+0.3 V 1,2

DDQ

-0.1 V 1,3

REF

-0.2 V 4,5

REF

6109 tb l 10d

1. These are DC test criteria. DC design criteria is VREF + 50mV. The AC VIH/VIL levels are defined separately for measuring timing parameters.

2. VIH (Max) DC = VDDQ+0.3, VIH (Max) AC = VDD +0.5V (pulse width <20% tKHKH (min))

3. VIL (Min) DC = -0.3V, VIL (Min) AC = -0.5V (pulse width <20% tKHKH (min))

4. This conditon is for AC function test only, not for AC parameter test.

5. To maintain a valid level, the transitioning edge of the input must:
a) Sustain a constant slew rate from the current AC level through the target AC level, VIL(AC) or VIH (AC)
b) Reach at least the target AC level.
c) After the AC target level is reached, continue to maintain at least the target DC level, VIL(DC) or VIH(DC)

Overshoot Timing

20%tKHKH (MIN)

+0.5

V

+0.25

Undershoot Timing

IH

V

SS

VSS-0.25V

V

AC Test Load

DDQ

V

REF

OUTPUT
Device

Under
Test

ZQ

V

Z

0

Q

R

/2

=50

=250

-0.5V

V

SS

6109drw22

6109drw 2

20% tKHKH (MIN)

AC Test Conditions

Co re P ower S upp ly Vo l tag e V
Outp ut Power Supply Voltage V
Input High/Low Level VIH/V
Inpu t Re fe rence L e v e l VREF V

Ω

Ω

DDQ

V

R

/2

=50

L

Ω

Input Rise/ Fall Time TR/TF 0.6/0.6 ns
Output Timing Referenc e Leve l V

NOTE:

1. Parameters are tested with RQ=250Ω

6109 drw 04

1.25V

0.75V

0.25V

DD

DDQ

1.7-1.9 V

1.4-1.9 V

IL

1.25 /0.25 V

DDQ

/2 V

DDQ

/2 V

6109tbl 11a

6109 drw 06

6.4212

IDT71P72204 (2M x 8-Bit), 71P72104 (2M x 9-Bit), 71P72804 (1M x 18-Bit) 71P72604 (512K x 36-Bit)

Symbol

Parameter

250MHz

200MHz

167MHz

Unit

Notes

Min.

Max

Min.

Max

Min.

Max

Clock Pa ram eters

t

KHKH

Averag e clock cycle time (K

,K,C,C)

4.00

6.30

5.00

7.88

6.00

8.40

ns

t

KC var

Cycle to Cycle Period Jitter (K,

,C,C)-0.20-0.20-0.20ns1,5

t

KHKL

Clock High Tim e (K,

,C,C)

1.60-2.00-2.40-ns9t

KLKH

Clock LOW Tim e (K,

,C,C)

1.60-2.00-2.40-ns9t

KHKH

Clock to

(K

,C

)

1.80-2.20-2.70-ns10t

HKH

to cl o ck (

K,

C)

1.80-2.20-2.70-ns10t

KHCH

Clock to data clock (K

C,

)

0.00

1.80

0.00

2.30

0.00

2.80

ns

t

KC lock

DLL lock time (K, C)

1024-1024-1024-cycle s

2

t

KC reset

K static to DLL rese t

30-30-30-ns

Output Parameters

t

CHQV

C,C HIGH to output valid

-

0.45-0.45-0.50ns3

t

CHQX

C,C HIGH to output hold

-0.45--0.45--0.50-ns3t

CHCQV

C,C HIG H to echo clock v alid

-

0.45-0.45-0.50ns3

t

CHCQX

C,C HIG H to echo clock hold

-0.45--0.45--0.50-ns3t

CQ HQV

CQ,CQ HIG H to o utpu t va lid

-

0.30-0.35-0.40

ns

t

CQHQ X

CQ,CQ HIGH to output hold

-0.30--0.35--0.40-ns

t

CHQZ

HIGH to output High-Z

-

0.45-0.45-0.50ns3,4,5

t

CHQX1

HIGH to output Low-Z

-0.45--0.45--0.50-ns

3,4,5

Set-Up Times

t

AVKH

Address valid to K,

rising edge

0.35-0.40-0.50-ns6t

IV KH

Co ntro l in pu ts va lid to K,

rising edge

0.35-0.40-0.50-ns7t

DVK H

Date -in valid to K ,

rising edge

0.35-0.40-0.50-ns

Hold Ti mes

t

KHAX

K,K rising edge to address hold

0.35-0.40-0.50-ns6t

KHIX

K,K rising edge to control inputs hold

0.35-0.40-0.50-ns7t

KHDX

K, K rising edge to data-in hold

0.35-0.40-0.50-ns

6109 tbl 11

Advance Information

18 Mb QDR II SRAM Burst of 2 Commercial Temperature Range

AC Electrical Characteristics (VDD = 1.8 ± 100mV, VDDQ = 1.4V to 1.9V, TA =0 to 70°C)

K

K

K

clock

→

K

→

C

K

Clock

K

→

C

→

→

K→C

(3,8)

C

C

K

K

K

NOTES:

1. Cycle to cycle period jitter is the variance from clock rising edge to the next expected clock rising edge, as defined per JEDEC Standard No.65 (EIA/JESD65) pg.10

2. Vdd slew rate must be less than 0.1V DC per 50 ns for DLL lock retention. DLL lock time begins once Vdd and input clock are stable.

3. If C,C are tied High, K,K become the references for C,C timing parameters.

4. To avoid bus contention, at a given voltage and temperature tCHQX1 is bigger than tCHQZ.
The specs as shown do not imply bus contention because tCHQX1 is a MIN parameter that is worse case at totally different test conditions
(0°C, 1.9V) than tCHQZ, which is a MAX parameter (worst case at 70°C, 1.7V)
It is not possible for two SRAMs on the same board to be at such different voltage and temperature.

5. This parameter is guaranteed by device characterization, but not production tested.

6. All address inputs must meet the specified setup and hold times for all latching clock edges.

7. Control signals are R, W,BW0,BW1 and (NW0,NW1, for x8) and (BW2,BW3 also for x36)

8. During production testing, the case temperature equals TA.

9. Clock High Time (tKHKL) and Clock Low Time (tKLKH) should be within 40% to 60% of the cycle time (tKHKH).

10. Clock to Clock time (tKHKH) and Clock to Clock time (tKHKH) should be within 45% to 55% of the cycle time (tKHKH).

6.42

13

IDT71P72204 (2M x 8-Bit), 71P72104 (2M x 9-Bit), 71P72804 (1M x 18-Bit) 71P72604 (512K x 36-Bit)

Advance Information

18 Mb QDR II SRAM Burst of 2 Commercial Temperature Range

Timing Waveform of Combined Read and Write Cycles

Read A0 Write A1 Read A2 Read A4

1

2

3

4

5

K

tKHKL

tKLKH

tKHKH

K

R

tIVKH

tKHIX

W

SA

D

A0

D10

A1

D11

A3A2

tKHAXtAVKH

tAVKH

tKHAX

D30 D31

A4

D50

tKHKH

6

A5

D51

NOP

7

D60

8

A6

D61

NOP NOPWrite A3 Write A5 Write A6

9

10

Q

C

C

CQ

CQ

tKHCH

tKHKL

tKHCH

tKLKH

tDVKH

tCHQX1

tKHKH

tCHCQX

tCHQV

tCHCQV

tKHDX

tCHCQX

Q00

tCHQX

tCHCQV

Q01 Q20 Q21

tCHQX

tCHQV

tKHKH

tKHDXtDVKH

tCQHQV

tCQHQX

Q40

Q41

tCHQZ

6109 drw 09a

6.4214

IDT71P72204 (2M x 8-Bit), 71P72104 (2M x 9-Bit), 71P72804 (1M x 18-Bit) 71P72604 (512K x 36-Bit)

IR2

IR1

IR0

Instruction

TDO Output

Notes

.

s

6109drw18

Advance Information

18 Mb QDR II SRAM Burst of 2 Commercial Temperature Range

IEEE 1149.1 TEST ACCESS PORT AND BOUNDARY SCAN-JTAG

This part contains an IEEE standard 1 149.1 Compatible T est Access Port (T AP). The package pads are monitored by the Serial Scan circuitry
when in test mode. This is to support connectivity testing during manufacturing and system diagnostics. In conformance with IEEE 1149.1, the
SRAM contains a TAP controller , Instruction register , Bypass Register and ID register . The T AP controller has a standard 16-st ate machine that
resets internally upon power-up; therefore, the TRST signal is not required. It is possible to use this device without utilizing the T A P . To disable
the T AP controller without interfacing with normal operation of the SRAM, TCK must be tied to VSS to preclude a mid level input. TMS and TDI
are designed so an undriven input will produce a response identical to the application of a logic 1, and may be left unconnected, but they may
also be tied to VDD through a resistor. TDO should be left unconnected.

JTAG Block Diagram

S

A,D
K,

K

C,C

Q
CQ

SRAM
CORE

CQ

TDI

BYPASS Reg.
Identification Reg.
Instruction Reg

Control Signal

TMS
TCK

TAP Controller

TAP Controller State Diagram

TDO

JTAG Instruction Coding

0 0 0 EXTEST Boundary Scan Register
0 0 1 IDCODE Identification register 2
0 1 0 SAMPLE-Z Boundary Scan Re gister 1
0 1 1 RESERVED Do Not Use 5

1 0 0 SAMPLE/PRELOAD Boundary Scan re gister 4
1 0 1 RESERVED Do Not Use 5
1 1 0 RESERVED Do Not Use 5
1 1 1 BYPASS Bypass Register 3

NOTES:

1. Places Qs in Hi-Z in order to sample all input data regardless of other
SRAM inputs.

2. TDI is sampled as an input to the first ID register to allow for the serial shift
of the external TDI data.

3. Bypass register is initialized to Vss when BYPASS instruction is invoked.
The Bypass Register also holds serially loaded TDI when exiting the Shift DR
states.

4. SAMPLE instruction does not place output pins in Hi-Z.

5. This instruction is reserved for future use.

6109tbl 13

Test Logic Reset

1

0

Run Test Idle Select DR

0

1

1

1

1

0

CaptureDR

0

Shift DR

1

Exit 1 DR

0

Pause DR

1

Exit 2 DR

1

UpdateDR

0

1

1

CaptureIR

0

1

0

0

SelectIR

0

0

Shift IR

1

Exit 1 IR

Pause IR

Exit 2 IR

1

UpdateIR

0

1

1

6109 drw 17

1

0

0

0

0

6.42

15

IDT71P72204 (2M x 8-Bit), 71P72104 (2M x 9-Bit), 71P72804 (1M x 18-Bit) 71P72604 (512K x 36-Bit)

Part

Instruction Register

Bypass Register

ID Register

Boundary Scan

INSTRUCTION FIELD

ALL DEVICES

DESCRIPTION

PART NUM BER

18 Mb QDR II SRAM Burst of 2 Commercial Temperature Range

Advance Information

Scan Register Definition

512Kx36 3 bits 1 bit 32 bits 107 b its

1Mx18 3 bits 1 bit 32 bits 107 b its

2Mx8/x 9 3 bits 1 b it 32 bits 107 bi ts

6109 tbl 14

Identification Register Definitions

Rev i si on Numb e r (31:29) 000 Re vi si o n Numbe r
Dev ic e ID (28:12) 0 0000 0010 0100 0100

0 0000 0010 0100 0101
0 0000 0010 0100 0110
0 0000 0010 0100 0111

512K x36 QDRII Burst o f 2

1Mx 18

2Mx 9
2Mx 8

IDT JE DEC ID CODE (11:1) 000 0011 0011 All ows uniq ue i d entific atio n o f SRAM

vendor.

ID Register Presence

1 Indicates the presence of an ID register.

Ind ic ato r (0)

71P72604S
71P72804S
71P72104S
71P72204S

6109 tbl 15

6.4216

IDT71P72204 (2M x 8-Bit), 71P72104 (2M x 9-Bit), 71P72804 (1M x 18-Bit) 71P72604 (512K x 36-Bit)

Advance Information

18 Mb QDR II SRAM Burst of 2 Commercial Temperature Range

Boundary Scan Exit Order (2M x 8-Bit, 2M x 9-Bit)

ORDER PIN ID

16R
26P
36N
47P
57N
67R
78R
88P
99R

10 11P

11 10P

12 10N
13 9P
14 10M
15 11N
16 9M
17 9N
18 11L
19 11M
20 9L
21 1 0L
22 11K
23 10K
24 9J
25 9K
26 1 0J
27 11J
28 11H
29 1 0G
30 9G
31 11F
32 11G
33 9F
34 10F
35 11E
36 10E

6109 tb l 16 a

ORDER PIN ID

37 10D
38 9E
39 10C
40 11D

41 9C
42 9D
43 11B
44 11C
45 9B
46 10B
47 11A
48 Internal
49 9A
50 8B

51 7C
52 6C
53 8A
54 7A
55 7B
56 6B
57 6A
58 5B
59 5A
60 4A

61 5C
62 4B
63 3A
64 2A
65 1A
66 2B
67 3B
68 1C
69 1B
70 3D

71 3C
72 2D

ORDER PIN ID

73 3E
74 2C
75 1D
76 2E
77 1E
78 2F
79 3F
80 2G

81 3G
82 1F
83 1G
84 1J
85 2J
86 3K
87 3J
88 3L
89 2L
90 1K

91 2K
92 1M
93 1L
94 3N
95 3M
96 2N
97 3P
98 2M
99 1N

100 2P
101 1P
102 3R
103 4R
104 4P
105 5P
106 5N
107 5R

6109 tb l 18a

6109 tb l 17a

6.42

17

IDT71P72204 (2M x 8-Bit), 71P72104 (2M x 9-Bit), 71P72804 (1M x 18-Bit) 71P72604 (512K x 36-Bit)

Advance Information

18 Mb QDR II SRAM Burst of 2 Commercial Temperature Range

Boundary Scan Exit Order (1M x 18-Bit, 512K x 36 -Bit)

ORDER PIN ID

16R
26P
36N
47P
57N
67R
78R
88P
99R

10 11P
11 10P
12 10N
13 9P
14 10M
15 11N
16 9M
17 9N
18 11L
19 11M
20 9L
21 10L
22 11K
23 10K
24 9J
25 9K
26 10J
27 11J
28 11H
29 10G
30 9G
31 11F
32 11G
33 9F
34 10F
35 11E
36 10E

6109 tbl 16

ORDER PIN ID

37 10D
38 9E
39 10C
40 11D
41 9C
42 9D
43 11B
44 11C
45 9B
46 10B
47 11A
48 Internal
49 9A
50 8B
51 7C
52 6C
53 8A
54 7A
55 7B
56 6B
57 6A
58 5B
59 5A
60 4A
61 5C
62 4B
63 3A
64 1H
65 1A
66 2B
67 3B
68 1C
69 1B
70 3D
71 3C
72 1D

ORDE R PI N ID

73 2C
74 3E
75 2D
76 2E
77 1E
78 2F
79 3F
80 1G
81 1F
82 3G
83 2G
84 1J
85 2J
86 3K
87 3J
88 2K
89 1K
90 2L
91 3L
92 1M
93 1L
94 3N
95 3M
96 1N
97 2M
98 3P

99 2N
100 2P
101 1P
102 3R
103 4R
104 4P
105 5P
106 5N
107 5R

6109 tb l 18

6109 tb l 17

6.4218

IDT71P72204 (2M x 8-Bit), 71P72104 (2M x 9-Bit), 71P72804 (1M x 18-Bit) 71P72604 (512K x 36-Bit)

DD Q

DD

IH

IL

OH

OHVDDQ -

DD Q

OL

OLVSS

6109 tbl 19

IH/VIL

DDQ

TCKTM

S

t

TDI/SRAMIn putsTD

O

t

t

t

t

t

t

t

t

t

SRAM

Outputs

Advance Information

18 Mb QDR II SRAM Burst of 2 Commercial Temperature Range

JTAG DC Operating Conditions

Parameter Symbol Min Typ Max Unit Note
Output Power Supply V
Power Supply Voltage V
Input High Level V
Input Low Lev el V
Output High Voltage (I
Output Low Vo ltag e (I

= -1mA) V
= 1mA) V

1.4 - 1. 9 V

1.7 1.8 1.9 V

1.3 - VDD+0.3 V

-0.3 - 0.5 V

0.2 - V

-0.2V1

V1

NOTE:

1. The output impedance of TDO is set to 50 ohms (nominal process) and does not vary with the external resistor connected to ZQ.

JTAG AC Test Conditions

Parameter Symbol Min Unit Not e

Input High/Low Level V

1.3/0.5 V
Input Rise/Fall Time TR/TF 1.0/1.0 ns
Inp ut and Outp ut Timing Re fere nc e L ev e l V

NOTE:

/2 V 1

6109 tbl 20

1. See AC test load on page 12.

JTAG AC Characteristics

Parameter Symbol Min Max Unit Note
TCK Cyc l e Ti m e t
TCK High Pulse Width t
TCK Low Pulse Width t
TMS Input Setup Time t
TMS I nput Hold Ti m e t
TDI Inp u t S etup Tim e t
TDI Inp ut Hol d Tim e t
SRAM Input Setup Time t
SRAM Input Hold Time t
Clo ck Lo w to Outp ut Vali d t

JTAG Timing Diagram

CHCH

CHCH
CHCL
CLCH
MVCH
CHMX
DV CH
CHDX
SVCH
CHSX
CLQV

MVCH

DVCH

50 - ns
20 - ns
20 - ns

5-ns
5-ns
5-ns
5-ns
5-ns
5-ns
010ns

6109 tbl.21

CHCL

CHMX

CHDX

CLCH

SVCH

CLQV

6.42

CHSX

6109 drw 19

19

IDT71P72204 (2M x 8-Bit), 71P72104 (2M x 9-Bit), 71P72804 (1M x 18-Bit) 71P72604 (512K x 36-Bit)
18 Mb QDR II SRAM Burst of 2 Commercial Temperature Range

Advance Information

Package Diagram Outline for 165-Ball Fine Pitch Grid Array

6.4220

IDT71P72204 (2M x 8-Bit), 71P72104 (2M x 9-Bit), 71P72804 (1M x 18-Bit) 71P72604 (512K x 36-Bit)
18 Mb QDR II SRAM Burst of 2 Commercial Temperature Range

Advance Information

Ordering Information

S

IDT 71P72XXX

Device

Type

Power

XXX

SpeedBQPackage

X

Process

Temperature

Range

Blank

BQ

250
200
167

IDT71P72204 2M x 8 Q DRII SRAMBurst of 2
IDT71P72104 2M x 9 Q DRII SRAMBurst of 2
IDT71P72804 1M x 18 QDR II SRAM Burst of 2
IDT71P72604 512K x 36 QDR II SRAM Burst of 2

Commerc ial (0oCto+70oC)

165FinePitch Ball GridArray (fB GA)

Clock Frequency in MegaHertz

6109 drw 15

CORPORA TE HEADQUARTERS for SALES: for T ech Support:

2975 Stender Way 800-345-7015 or 408-727-6116 [e-mail]
Santa Clara, CA 95054 fax: [phone]

www .idt.com

“QDR SRAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress Semiconductor, IDT, and Micron Technology, Inc. “

6.42

21

IDT71P72204 (2M x 8-Bit), 71P72104 (2M x 9-Bit), 71P72804 (1M x 18 x -Bit) 71P72604 (512K x 36-Bit)
18 Mb QDR II SRAM Burst of 2 Commercial Temperature Range

Advance Information

Revision History

REVISION DATE PAGES DESCRIPTION
0 8/01/03 1-21 Initial Advance Information Data Sheet Release
A 11/14/03 11,12,19 Updated tKHKH (max) for 167-250 MHz and set-up & hold times for

250MHz. Incorporated 133 MHz speed grade in S167 speed bin.

15 Changed number of Boundary Scan bits from 109 to 107. Specified ID bits [28:24] and

IDT JEDEC ID bits [11:1] in binary.

16 Updated Boundary Scan Pin IDs for order #48, #64 and #84 through 107.

B 3/30/04 1,3,5-8,14-15 Renamed address inputs from A to SA.

5-8 Identified 36Mb to 288Mb address expansion pins and requirements.

9 Updated absolute maximum VTERM on input terminals, added VDDQ requirement note 2

and VREF min/max specifications

9,11,12 Consolidated DC and AC input specifications by adding new pg.12, including new Input

Electrical Characteristics table, notes 1-5 and overshoot/undershoot timing diagrams.
10 Updated application example showing HSTL terminations (R and VT) on control inputs.
11 Clarified VOH, VOL, IDD and ISB1 test conditions and notes.
13 Clarified tKHKL,tKLKH,tKHKH, tKHKH as a percentage of the cycle time; updated tKC var

cycle to cycle period jitter and notes for AC Electrical Characteristics.
14 Added tCQHQX to timing diagram.

17,18 Modified Boundary Scan order for x8 and x9 options, adding new page 17 with new pin

IDs for order#64, #72-75, #80-83, #88-91 and #96-99; changed order #48 from 10A to

Internal for x8/9 and x18/36 options.
19 Updated JTAG DC Operating Conditions note 1 and VOH (max) specification from VDD to

VDDQ. Added tCLQV to JTAG Timing Diagram.

C 5/18/04 1 Corrected package size to 13mm x 17mm fBGA.

2 Clarified data word order.
12 Updated AC Test Load and T est Conditions to VREF = VDDQ/2.
15 Clarified pull up resistor to VDD for the unused JTAG inputs.