Datasheet IDT71B74S12TP, IDT71B74S12Y, IDT71B74S15TP, IDT71B74S15Y, IDT71B74S20TP Datasheet (Integrated Device Technology Inc)
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Integrated Device Technology, Inc.
BiCMOS STATIC RAM
64K (8K x 8-BIT)
CACHE-TAG RAM
IDT71B74
FEATURES:
• High-speed address to MATCH comparison time
— Commercial: 8/10/12/15/20ns (max.)
• High-speed address access time
— Commercial: 8/10/12/15/20ns (max.)
• High-speed chip select access time
— Commercial: 6/7/8/10ns (max.)
• Power-ON Reset Capability
• Low power consumption
— 830mW (typ.) for 12ns parts
— 880mW (typ.) for 10ns parts
— 920mW (typ.) for 8ns parts
• Produced with advanced BiCMOS high-performance
technology
• Input and output directly TTL-compatible
• Standard 28-pin plastic DIP and 28-pin SOJ (300 mil)
DESCRIPTION:
The IDT71B74 is a high-speed cache address comparator
subsystem consisting of a 65,536-bit static RAM organized as
8K x 8 and an 8-bit comparator. A single IDT71B74 can map
8K cache words into a 2 megabyte address space by using the
21 bits of address organized with the 13 LSBs for the cache
address bits and the 8 higher bits for cache data bits. Two
IDT71B74s can be combined to provide 29 bits of address
comparison, etc. The IDT71B74 also provides a single RAM
clear control, which clears all words in the internal RAM to zero
when activated. This allows the tag bits for all locations to be
cleared at power-on or system-reset, a requirement for cache
comparator systems. The IDT71B74 can also be used as a
resettable 8K x 8 high-speed static RAM.
The IDT71B74 is fabricated using IDT’s high-performance,
high-reliability BiCMOS technology. Address access times as
fast as 8ns, chip select times of 6ns and address-to-match
times of 8ns are available.
The MATCH pin of several IDT71B74s can be wired-ORed
together to provide enabling or acknowledging signals to the
data cache or processor, thus eliminating logic delays and
increasing system throughput.
FUNCTIONAL BLOCK DIAGRAM
A0
ADDRESS
DECODER
A12
RESET
I/O0 - 7
WE
OE
CS
8
CONTROL
LOGIC
EQUAL
MATCH (OPEN DRAIN)
65,536-BIT
MEMORY ARRAY
I/O CONTROL
VCC
GND
3013 drw 01
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE AUGUST 1996
1996 Integrated Device Technology, Inc. DSC-3013/4
14.1
1
IDT71B74
BiCMOS STATIC RAM 64K (8K x 8-BIT) CACHE-TAG RAM COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATION
RESET
A
A
A
A
A
A
A
A
A
I/O
I/O
I/O
GND
1
2
12
3
7
4
6
5
5
4
3
2
1
0
0
1
2
6
7
8
9
10
11
12
13
14
P28-2
SO28-5
DIP/SOJ
V
CC
28
WE
27
MATCH
26
A
8
25
24
A
9
A
23
11
22
OE
A
10
21
20
CS
I/O
I/O
I/O
I/O
I/O
7
6
5
4
3
3013 drw 02
19
18
17
16
15
TOP VIEW
TRUTH TABLE
WEWECSCSOEOERESET
(1, 2)
RESET
MATCH I/O Function
X X X L HIGH — Reset all bits to LOW
X H X H HIGH Hi-Z Deselect chip
H L H H LOW DIN No MATCH
H L H H HIGH DIN MATCH
H L L H HIGH DOUT Read
L L X H HIGH D
NOTES: 3013 tbl 01
1. H = VIH, L = VIL, X = DON'T CARE
2. HIGH = High-Z (pulled up by an external resistor), and LOW = V
IN Write
OL.
PIN DESCRIPTIONS
Pin Names Description
A0–12 Address
I/O0-7 Data Input/Output
CS
RESET
MATCH Data/Memory Match (Open Drain)
WE
OE
GND Ground
V
CC Power
Chip Select
Memory Reset
Write Enable
Output Enable
3013 tbl 02
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol Rating Com’l. Unit
(2)
V
TERM
Terminal Voltage with –0.5 to +7.0 V
Respect to GND
TA Operating Temperature 0 to +70 °C
TBIAS Temperature Under Bias –55 to +125 ° C
TSTG Storage Temperature –55 to +125 °C
PT Power Dissipation 1.0 W
OUT DC Output Current 50 mA
I
NOTES: 3013 tbl 03
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
TERM must not exceed VCC + 0.5V.
2. V
CAPACITANCE
(TA = +25°C, f = 1.0MHz, SOJ Package)
Symbol Parameter
CIN Input Capacitance VIN = 3dV 6 pF
OUT Output Capacitance VOUT = 3dV 7 pF
C
NOTE: 3013 tbl 04
1. This parameter is determined by device characterization, but is not
production tested.
(1)
Conditions Max. Unit
14.1 2
IDT71B74
BiCMOS STATIC RAM 64K (8K x 8-BIT) CACHE-TAG RAM COMMERCIAL TEMPERATURE RANGE
RECOMMENDED DC OPERATING
CONDITIONS
Symbol Parameter Min. Typ. Max. Unit
VCC Supply Voltage 4.5 5.0 5.5 V
GND Supply Voltage 0 0 0 V
VIH Input HIGH Voltage
VIHR
V
IL Input LOW Voltage –0.5
NOTES: 3013 tbl 05
1. All inputs except
2. When using bipolar devices to drive the
1kΩ–10kΩ is usually required to assure this voltage.
3. V
IL (min.) = –1.5V for pulse width less than 10ns, once per cycle.
TERM must not exceed VCC + 0.5V.
4. V
RESET
Input Voltage 2.5
RESET
.
(1)
2.2 — 6.0
(2)
(3)
RESET
— 6.0 V
— 0.8 V
input, a pullup resistor of
DC ELECTRICAL CHARACTERISTICS
(4)
(1)
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Grade Ambient Temperature GND VCC
Commercial 0°C to +70°C 0V 5V ± 10%
3013 tbl 06
V
(VCC = 5.0V ± 10%, VLC = 0.2V, VHC = VCC – 0.2V)
Symbol Parameter 71B74S8 71B74S10 71B74S12 71B74S15 71B74S20 Unit
CC Dynamic Operating Current
I
Outputs Open, VCC = Max., f = fMAX
NOTES: 3013 tbl 07
1. All values are maximum guaranteed values.
MAX = 1/tRC, only input addresses are cycling at fMAX.
2. f
WE
= VLC 230 210 200 190 180 mA
(2)
WE
= VHC 210 200 170 160 150 mA
DC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE
AND SUPPLY VOLTAGE
Symbol Parameter Test Condition Min. Max. Unit
|I
LI| Input Leakage Current VCC = Max., VIN = GND to VCC —5µA
LO| Output Leakage Current VCC = Max.,
|I
VOL Output LOW Voltage IOL = 22mA MATCH — 0.5 V
OH Output HIGH Voltage IOH = –4mA, VCC = Min. (Except MATCH) 2.4 — V
V
AC TEST CONDITIONS
Input Pulse Levels GND to 3.0V
Input Rise/Fall Times 3ns
Input Timing Reference Levels 1.5V
Output Reference Levels 1.5V
AC Test Load See Figures 1, 2, and 3
(VCC = 5.0V ± 10%)
VOUT = GND to VCC
OL = 18mA MATCH — 0.4
I
OL = 10mA, VCC = Min. (Except MATCH) — 0.5
I
IOL = 8mA, VCC = Min. (Except MATCH) — 0.4
IDT71B74S
CS
= VIH,—5µA
3013 tbl 08
1.5V
50
Ω
DATA
OUT
3013 drw 03
3013 tbl 09
Figure 1. AC Test Load
14.1 3
IDT71B74
BiCMOS STATIC RAM 64K (8K x 8-BIT) CACHE-TAG RAM COMMERCIAL TEMPERATURE RANGE
∆TADM
(Typical, ns)
MATCH
7
6
5
4
3
2
1
•
8
•
•
•
20 40 60 80 100 120 140 160
•
•
CAPACITANCE (pF)
Figure 1A. Lumped Capacitive Load
Typical Derating Curve
5V
R
L
= 200Ω (COM’L.)
Ω
(MIL.)
= 270
•
480Ω
5V
DATA
OUT
180
3013 drw 04
200
255Ω
*Includes scope and jig.
Figure 2. AC Test Load
(for t
CLZ, tOLZ, tCHZ, tOHZ, tOW, tWHZ)
5pF*
3013 drw 05
7
•
∆TAA
(Typical, ns)
6
5
4
R
L
3013 drw 06
3
2
1
•
8
•
•
•
20 40 60 80 100 120 140 160
•
•
180
200
Figure 3. AC Test Load for MATCH
Figure 3A. Lumped Capacitive Load
Typical Derating Curve
32
DATA
ADDR
80486
5V
(2)
L
R
32-BIT
MICROPROCESSOR
A4-A16
CLEAR
RDY
NOTES:
1. For more information refer to IDT Application Notes AN-07 and AN-78 and Technical Notes TN-11 and TN-13.
L = 200Ω.
2. R
32
8713
D0-D31
A0-A31
LOGIC 1
A17-A24
IDT71B74
CACHE-
TAG
RAM
MATCH
A25-A31
IDT71B74
CACHE-
TAG
RAM
MATCH
MEMORY READ/WRITE
CONTROL LOGIC
8 9
8 98 8
IDT71256
256 256256
CACHE-
DATA
RAM
CACHE READ/WRITE
MAIN MEMORY READ/WRITE
CAPACITANCE (pF)
3013 drw 07
DATA
ADDR
MAIN
MEMORY
3013 drw 08
Figure 4. Example of Cache Memory System Block Diagram
14.1 4
IDT71B74
BiCMOS STATIC RAM 64K (8K x 8-BIT) CACHE-TAG RAM COMMERCIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS (VCC = 5.0V ± 10%)
71B74S8 71B74S10 71B74S12 71B74S15 71B74S20
Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
Read Cycle
tRC Read Cycle Time 8 — 10 — 12 — 15 — 20 — ns
tAA Address Access Time — 8 — 10 — 12 — 15 — 20 ns
tACS Chip Select Access Time — 6 — 7 — 8 — 8 — 10 ns
(1)
tCLZ
tOE Output Enable to Output Valid — 5 — 6 — 6 — 8 — 9 ns
tOLZ
tCHZ
tOHZ
OH Output Hold from Address Change 3 — 3 — 3 — 3 — 3 — ns
t
NOTE: 3013 tbl 10
1. This parameter is guaranteed with the AC Load (Figure 2) by device characterization, but is not production tested.
Chip Select to Output in Low-Z 2 — 2 — 2 — 3 — 3 — ns
(1)
Output Enable to Output in Low-Z 2 — 2 — 2 — 2 — 2 — ns
(1)
Chip Select to Output in High-Z — 4 — 5 — 5 — 7 — 8 ns
(1)
Output Disable to Output in High-Z — 4 — 4 — 5 — 5 — 8 ns
TIMING WAVEFORM OF READ CYCLE NO. 1
tRC
ADDRESS
tAA
OE
tOE
(5)
tOLZ
CS
(3)
tACS
(5)
tCLZ
DATAOUT
TIMING WAVEFORM OF READ CYCLE NO. 2
t
RC
(1)
(1, 2, 4)
DATAOUT VALID
t
OH
t
tOHZ
CHZ
(5)
(5)
3013 drw 09
ADDRESS
t
AA
t
OH
DATA
OUT
NOTES:
1.WE is HIGH for Read cycle.
2. Device is continuously selected, CS is LOW.
3. Address valid prior to or coincident with CS transition LOW; otherwise t
4.OE is continuously active, OE is LOW.
5. Transition is measured ±200mV from steady state.
t
OH
DATA
OUT
VALID
3013 drw 10
AA is the limiting parameter.
14.1 5
IDT71B74
BiCMOS STATIC RAM 64K (8K x 8-BIT) CACHE-TAG RAM COMMERCIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS (VCC = 5.0V ± 10%)
71B74S8 71B74S10 71B74S12 71B74S15 71B74S20
Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
Write Cycle
tWC Write Cycle Time 8 — 10 — 12 — 15 — 20 — ns
tCW Chip Select to End of Write 7 — 8 — 9 — 10 — 15 — ns
tAW Address Valid to End of Write 7 — 8 — 9 — 10 — 15 — ns
tAS Address Set-up Time 0 — 0 — 0 — 0 — 0 — ns
tWP Write Pulse Width 7 — 8 — 9 — 10 — 15 — ns
tWR Write Recovery Time (CS, WE) 0—0—0—0—0—ns
(1)
tWHZ
tDW Data Valid to End of Write 5 — 5 — 6 — 8 — 10 — ns
tDH Data Hold from Write Time 0 — 0 — 0 — 0 — 0 — ns
(1)
OW
t
NOTE: 3013 tbl 11
1. This parameter is guaranteed with the AC Load (Figure 2) by device characterization, but is not production tested.
Write Enable to Output in High-Z — 5 — 5 — 5 — 5 — 5 ns
Output Active from End of Write 2 — 2 — 2 — 2 — 2 — ns
TIMING WAVEFORM OF WRITE CYCLE NO. 1 (
WEWE Controlled Timing,
OEOE HIGH During Write)
tWC
ADDRESS
OE
CS
tAS
tAW
tWR
(3)
WE
(2)
tWHZ
(8,9)
tWP
tOW
(9)
DATAOUT
(4,9)
tOHZ
DATAIN
NOTES:
1.WE, CS must be inactive during all address transitions.
2. A write occurs during the overlap of a LOW WE and a LOW CS.
3. t
WR is measured from the earlier of
4. During this period, I/O pins are in the output state and input signals must not be applied.
5. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state.
6.OE is continuously HIGH, OE ≥ V
drivers to turn off and the data to be placed on the bus for the required t
apply and the minimum write pulse is the specified t
7. DATA
8. t
9. Transition is measured ±200mV from steady state.
OUT is never enabled, therefore the output is in High-Z state during the entire write cycle.
WHZ is not included if
OE
remains HIGH during the write cycle. If OE is LOW during the Write Enabled write cycle then tWHZ must be added to tWP and tCW.
CS
or WE going HIGH to the end of the write cycle.
IH. If during the
WE
controlled write cycle the OE is LOW, tWP must be greater or equal to tWHZ + tDW to allow the I/O
WP. For a
DW. If
CS
controlled write cycle, OE may be LOW with no degradation to tCW timing.
OE
is HIGH during the WE controlled write cycle, this requirement does not
DATA VALID
tDHtDW
(1, 6)
3013 drw 11
14.1 6
IDT71B74
BiCMOS STATIC RAM 64K (8K x 8-BIT) CACHE-TAG RAM COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OF WRITE CYCLE NO. 2 (
CSCS Controlled Timing)
t
WC
(1, 6)
ADDRESS
OE
(3)
tWR
CS
(2)
t
(5)
t
t
AS
CW
AW
WE
tOW
(9)
DATAOUT
(7)
tWHZ
(8,9)
t DHt DW
DATA
IN
NOTES:
1.WE, CS must be inactive during all address transitions.
2. A write occurs during the overlap of a LOW WE and a LOW CS.
3. t
WR is measured from the earlier of
4. During this period, I/O pins are in the output state and input signals must not be applied.
5. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state.
6.OE is continuously HIGH, OE ≥ V
drivers to turn off and the data to be placed on the bus for the required t
apply and the minimum write pulse is the specified t
7. DATA
8. t
9. Transition is measured ±200mV from steady state.
OUT is never enabled, therefore the output is in High-Z state during the entire write cycle.
WHZ is not included if
OE
remains HIGH during the write cycle. If OE is LOW during the Write Enabled write cycle then tWHZ must be added to tWP and tCW.
CS
or WE going HIGH to the end of the write cycle.
IH. If during the
WE
controlled write cycle the OE is LOW, tWP must be greater or equal to tWHZ + tDW to allow the I/O
WP. For a
DW. If
CS
controlled write cycle, OE may be LOW with no degradation to tCW timing.
OE
is HIGH during the WE controlled write cycle, this requirement does not
DATA VALID
3013 drw 12
AC ELECTRICAL CHARACTERISTICS (VCC = 5.0V ± 10%)
71B74S8 71B74S10 71B74S12 71B74S15 71B74S20
Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
Match Cycle
tADM Address to MATCH Valid — 8 — 10 — 12 — 15 — 20 ns
tCSM Chip Select to MATCH Valid — 7 — 7 — 8 — 10 — 10 ns
(1)
tCSMHI
tDAM Data Input to MATCH Valid — 7 — 8 — 10 — 12 — 12 ns
tOEMHI
tWEMHI
tRSMHI
tMHA MATCH Valid Hold From Address 2 — 2 — 2 — 2 — 2 — ns
MHD MATCH Valid Hold From Data 2 — 2 — 2 — 2 — 2 — ns
t
NOTE: 3013 tbl 12
1. This parameter is guaranteed with the AC Load (Figure 3) by device characterization, but is not production tested.
Chip Select to MATCH HIGH — 7 — 8 — 8 — 8 — 8 ns
(1)
OE
LOW to MATCH HIGH — 7 — 8 — 10 — 10 — 10 ns
(1)
WE
LOW to MATCH HIGH — 7 — 8 — 10 — 10 — 10 ns
(1)
RESET
LOW to MATCH HIGH — 8 — 10 — 10 — 12 — 15 ns
14.1 7
IDT71B74
BiCMOS STATIC RAM 64K (8K x 8-BIT) CACHE-TAG RAM COMMERCIAL TEMPERATURE RANGE
MATCH TIMING
(1)
ADDRESS
tADM
tCSM
CS
OE
WE
RESET
DATA
VALID READ DATA
VALID MATCH
DATA
tDAM
MATCH
MATCH
NO MATCH
NOTES:
1. It is not recommended to float data and address input pins while the MATCH pin is active.
2. Transition is measured at ±200mV from steady state.
tMHA
tWEMHI
tMHD
MATCH VALID
tCSMHI
tOEMHI
(2)
(2)
(2)
(2)
tRSMHI
3013 drw 13
AC ELECTRICAL CHARACTERISTICS (VCC = 5.0V ± 10%)
71B74S8 71B74S10 71B74S12 71B74S15 71B74S20
Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
Reset Cycle
(1)
tRSPW
tWERS
Reset Pulse Width 30 — 35 — 35 — 40 — 45 — ns
WE
HIGH to Reset HIGH 5 — 5 — 5 — 5 — 5 — ns
tRSRC Reset HIGH to WE LOW 25 — 25 — 25 — 30 — 30 — ns
(2)
tPORS
NOTES: 3013 tbl 13
1. Recommended duty cycle = 10% maximum.
2. This parameter is guaranteed with the AC Load (Figure 1) by device characterization, but is not production tested.
Power On Reset 100 — 100 — 100 — 120 — 120 — ns
RESET TIMING
t
RSPW
RESET
t
RSRC
WE
t
WERS
3013 drw 14
14.1 8
IDT71B74
BiCMOS STATIC RAM 64K (8K x 8-BIT) CACHE-TAG RAM COMMERCIAL TEMPERATURE RANGE
POWER ON RESET TIMING
tPORS
VCC
RESET
tRSRC
WE
CMOS GATE
Driving the
tWERS
IDT71B74
RESET
3013 drw 16
RESET
pin with CMOS logic. Driving the
RESET
Figure 5.
BIPOLAR GATE
1KΩ – 10KΩ
RESET
RESET
3013 drw 15
5V
IDT71B74
RESET
3013 drw 17
pin with bipolar logic.
ORDERING INFORMATION
IDT
71B74
Device
Type
S
PowerXXSpeedXPackage
X
Process/
Temperature
Range
Blank
TP
Y
8
10
12
15
20
Commercial (0
°C to +70°C)
Plastic DIP (300 mil) (P28–2)
SOJ (Small Outline IC, J-bend) (SO28–5)
Commercial Only, SOJ Only
Commercial Only
Commercial Only
Speed in ns
Commercial Only
Commercial Only
3013 drw 18
14.1 9
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