Datasheet IDT7188S25DB, IDT7188S35DB, IDT7188S45DB, IDT7188S55DB, IDT7188S70DB Datasheet (Integrated Device Technology Inc)

Integrated Device Technology, Inc.

W

CMOS STATIC RAM
64K (16K x 4-BIT)

IDT7188S
IDT7188L

FEATURES:

• High-speed (equal access and cycle times)
— Military: 25/35/45/55/70/85ns (max.)

• Low power consumption

• Battery backup operation — 2V data retention (L version
only)

• Available in high-density industry standard 22-pin, 300
mil ceramic DIP

• Produced with advanced CMOS technology

• Inputs/outputs TTL-compatible

• Military product compliant to MIL-STD-883, Class B

DESCRIPTION:

The IDT7188 is a 65,536-bit high-speed static RAM
organized as 16K x 4. It is fabricated using IDT’s high­performance, high-reliability technology — CMOS. This state­of-the-art technology, combined with innovative circuit design

FUNCTIONAL BLOCK DIAGRAM

A0

techniques, provides a cost effective approach for memory
intensive applications.

Access times as fast as 25ns are available. The IDT7188

offers a reduced power standby mode, I

SB1, which is activated

when CS goes HIGH. This capability significantly decreases

power while enhancing system reliability. The low-power
version (L) version also offers a battery backup data retention
capability where the circuit typically consumes only 30µW
operating from a 2V battery.

All inputs and outputs are TTL-compatible and operate
from a single 5V supply. The IDT7188 is packaged in 22-pin,
300 mil ceramic DIP providing excellent board-level packing
densities.

Military grade product is manufactured in compliance with
the latest revision of MIL-STD-883, Class B, making it ideally
suited to military temperature applications demanding the
highest level of performance and reliability.

VCC

CS

E

I/O0

I/O1

I/O2

I/O3

A13

DECODER

INPUT

DATA

CONTROL

GND

65,536-BIT

MEMORY ARRAY

COLUMN I/O

2989 drw 01

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

MILITARY TEMPERATURE RANGE AUGUST 1996

1996 Integrated Device Technology, Inc. DSC-2989/7
For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.

6.3

1

IDT7188S/L
CMOS STATIC RAM 64K (16K x 4-BIT) MILITARY TEMPERATURE RANGE

PIN CONFIGURATIONS

1

A0

2

A1

3

A2

4

A3

5

A4

6

A

5

A6
A7
A8

CS

GND

D22-1

7
8
9
10
11

DIP

TOP VIEW

PIN DESCRIPTIONS

Name Description

A0–A13 Address Inputs

CS
WE

I/O0-3 Data Input/Output
VCC Power
GND Ground

Chip Select
Write Enable

22
21

20
19

18
17
16
15
14
13
12

2989 drw 02

VCC
A13
A12
A11
A10

A9
I/O3
I/O
I/O1
I/O0
WE

ABSOLUTE MAXIMUM RATINGS

(1)

Symbol Rating Com’l. Mil. Unit

TERM Terminal Voltage –0.5 to +7.0 –0.5 to +7.0 V

V

with Respect
to GND

T

A Operating 0 to +70 –55 to +125 °C

Temperature

BIAS Temperature –55 to +125 –65 to +135 °C

T

Under Bias

STG Storage –55 to +125 –65 to +150 °C

T

Temperature

2

PT Power Dissipation 1.0 1.0 W

OUT DC Output 50 50 mA

I

Current

NOTE: 2989 tbl 03

1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.

CAPACITANCE

Symbol Parameter

(TA = +25°C, f = 1.0MHz, VCC = 0v))

(1)

Conditions Max. Unit

CIN Input Capacitance VIN = 0V 6 pF
C

I/O I/O Capacitance VOUT = 0V 6 pF

NOTE: 2989 tbl 04

1. This parameter is determined by device characterization, but is not

production tested.

RECOMMENDED DC OPERATING
CONDITIONS

Symbol Parameter Min. Typ. Max. Unit

VCC Supply Voltage 4.5 5.0 5.5 V
GND Supply Voltage 0 0 0 V

2989 tbl 01

VIH Input High Voltage 2.2 — 6.0 V
V

IL Input Low Voltage –0.5

NOTE: 2989 tbl 05

1. VIL (min.) = –3.0V for pulse width less than 20ns,once per cycle.

(1)

— 0.8 V

CS

CS

(1)

WE

WE

I/O Power

TRUTH TABLE

Mode

Standby H X High Z Standby
Read L H DOUT Active
Write L L D

NOTE: 2989 tbl 02

1. H = VIH, L = VIL, X = don't care.

IN Active

RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE

Grade Temperature GND VCC

Military –55°C to +125°C 0V 5V ± 10%
Commercial 0°C to +70°C 0V 5V ± 10%

2989 tbl 06

6.3 2

IDT7188S/L
CMOS STATIC RAM 64K (16K x 4-BIT) MILITARY TEMPERATURE RANGE

DC ELECTRICAL CHARACTERISTICS

VCC = 5.0V ± 10%

IDT7188S IDT7188L

Symbol Parameter Test Condition Min. Max. Min. Max. Unit

|I

LI| Input Leakage Current VCC = Max., MIL. — 10 — 5 µA

VIN = GND to VCC COM’L. — 5 — 2

LO| Output Leakage Current VCC = Max., CS = VIH, MIL. — 10 — 5 µA

|I

VOUT = GND to VCC COM’L. — 5 — 2

OL Output Low Voltage IOL = 10mA, VCC = Min. 0.5 — 0.5 V

V

IOL = 8mA, VCC = Min. — 0.4 — 0.4

OH Output High Voltage IOH = –4mA, VCC = Min. 2.4 — 2.4 — V

V

2989 tbl 07

DC ELECTRICAL CHARACTERISTICS

(1)

(VCC = 5V ± 10%, VLC = 0.2V, VHC = VCC - 0.2V)

7188S25 7188S35 7188S45 7188S55/70 7188S85
7188L25 7188L35 7188L45 7188L55/70 7188L85

Symbol Parameter Power Com’l. Mil. Com’l. Mil. Com’l. Mil. Com’l. Mil. Com’l. Mil. Unit

I

CC1 Operating Power S — 105 — 105 — 105 — 105 — 105 mA

Supply Current

CS

= V

IL, Outputs Open L — 80 — 80 — 80 — 80 — 80

VCC = Max., f = 0

ICC2 Dynamic Operating S — 155 — 140 — 140 — 140 — 140 mA

Current

CS

= V

IL, Outputs Open L — 120 — 115 — 110 — 110 — 105

VCC = Max., f = fMAX

ISB Standby Power Supply S — 60 — 50 — 50 — 50 — 50 mA

Current (TTL Level)

CS

≥ V

IH, VCC = Max., L — 40 — 40 — 35 — 35 — 35

Outputs Open, f = fMAX

ISB1 Full Standby Power S — 20 — 20 — 20 — 20 — 20 mA

Supply Current (CMOS
Level) CS ≥ V
V

CC=Max., VIN ≥ VHC or L — 1.5 — 1.5 — 1.5 — 1.5 — 1.5

V

IN ≤ VLC, f = 0

NOTES: 2989 tbl 08

1. All values are maximum guaranteed values.

2. At f = f

MAX address and data inputs are cycling at the maximum frequency of read cycles of 1/tRC. f = 0 means no input lines change.

(2)

(2)

(2)

HC,

(2)

6.3 3

IDT7188S/L
CMOS STATIC RAM 64K (16K x 4-BIT) MILITARY TEMPERATURE RANGE

DATA RETENTION CHARACTERISTICS OVER ALL TEMPERATURE RANGES

(L Version Only) VHC = VCC - 0.2V

(1)

Typ.

V

CC @VCC @

Symbol Parameter Test Condition Min. 2.0v 3.0V 2.0V 3.0V Unit

DR VCC for Data Retention — 2.0 — — — — V

V

CCDR Data Retention Current MIL. — 10 15 600 900 µA

I

COM’L. — 10 15 150 225

(3)

CDR

t

(3)

tR

(3)

LI|

|I

NOTES: 2989 tbl 09

1. TA = +25°C.

RC = Read Cycle Time.

2. t

3. This parameter is guaranteed by device characterization but is not production tested.

Chip Deselect to Data
Retention Time V

Operation Recovery Time tRC

CS

≥ VHC 0————ns

IN ≥ VHC or ≤ VLC

(2)

————ns

Input Leakage Current — — — 2 2 µA

Max.

LOW VCC DATA RETENTION WAVEFORM

DATA

RETENTION

VCC

4.5V 4.5V

MODE

V

CS

IH VIH

AC TEST CONDITIONS

Input Pulse Levels GND to 3.0V
Input Rise/Fall Times 5ns
Input Timing Reference Levels 1.5V
Output Reference Levels 1.5V
AC Test Load See Figures 1 and 2

5V

480Ω

OUT

DATA

255Ω

30pF*

2989 drw 04

2989 tbl 10

V

DR≥2V

VDR

DATA

OUT

255

tRtCDR

2989 drw 03

5V

480

Ω

Ω

5pF*

2989 drw 05

Figure 1. AC Test Load Figure 2. AC Test Load

*Includes scope and jig capacitances

6.3 4

HZ, tLZ, tWZ, tOHZ and tOW)

(for t

IDT7188S/L
CMOS STATIC RAM 64K (16K x 4-BIT) MILITARY TEMPERATURE RANGE

AC ELECTRICAL CHARACTERISTICS (VCC = 5.0V ± 10%, All Temperature Ranges)

7188S25 7188S35/45 7188S55/70 7188S85
7188L25 7188L35/45 7188L55/70 7188L85

Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Unit

Read Cycle

tRC Read Cycle Time 25 — 35/45 — 55/70 — 85 — ns
tAA Address Access Time — 25 — 35/45 — 55/70 — 85 ns
tACS Chip Select Access Time — 25 — 35/45 — 55/70 — 85 ns
tOH Output Hold from Address Change 5 — 5 — 5 — 5 — ns

(1)

tLZ
tHZ
tPU

PD

t

NOTES: 2989 tbl 11

1. This parameter is guaranteed by device characterization but is not production tested.

Output Selection to Output in Low-Z 5 — 5 — 5 — 5 — ns

(1)

Chip Deselect to Output in High-Z — 10 — 14 — 20/25 — 30 ns

(1)

Chip Select to Power Up Time 0 — 0 — 0 — 0 — ns

(1)

Chip Deselect to Power Down Time — 25 — 35/45 — 55/70 — 85 ns

TIMING WAVEFORM OF READ CYCLE NO. 1

(1, 2)

tRC

(5)

ADDRESS

tAA

tOH

OUT

DATA

TIMING WAVEFORM OF READ CYCLE NO. 2

PREVIOUS DATA VALID DATA VALID

(1, 3)

(5)

tRC

CS

tACS

(4)

tLZ

DATAOUT

tPU

CC

VCC SUPPLY

CURRENT

NOTES:

1.WE is HIGH for Read cycle.

2.CS is LOW for Read cycle.

3. Address valid prior to or coincident with CS transition LOW.

4. Transition is measured ±200mV from steady state voltage.

5. All Read cycle timings are referenced from the last valid address to the first transitioning address.

I
ISB

DATA VALID

tHZ

2989 drw 06

(4)

HIGH IMPEDANCE

tPD

2989 drw 07

6.3 5

IDT7188S/L
CMOS STATIC RAM 64K (16K x 4-BIT) MILITARY TEMPERATURE RANGE

AC ELECTRICAL CHARACTERISTICS (VCC = 5.0V ± 10%, All Temperature Ranges)

7188S25 7188S35/45 7188S55/70 7188S85
7188L25 7188L35/45 7188L55/70 7188L85

Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Unit
Write Cycle

tWC Write Cycle Time 20 — 30/40 — 50/60 — 75 — ns
tCW Chip Select to End-of-Write 20 — 25/35 — 50/60 — 75 — ns
tAW Address Valid to End-of-Write 20 — 25/35 — 50/60 — 75 — ns
tAS Address Set-up Time 0 — 0 — 0 — 0 — ns
tWP Write Pulse Width 20 — 25/35 — 50/60 — 75 — ns
tWR Write Recovery Time 0 — 0 — 0 — 0 — ns
tDW Data Valid to End-of-Write 13 — 15/20 — 25/30 — 35 — ns
tDH Data Hold Time 0 — 0 — 0 — 0 — ns

(1)

tWZ

OW

t

NOTES: 2989 tbl 12

1. This parameter is guaranteed by device characterization.

Write Enable to Output in High-Z — 7 — 10/15 — 25/30 — 40 ns

(1)

Output Active from End-of-Write 5 — 5 — 5 — 5 — ns

TIMING WAVEFORM OF WRITE CYCLE NO. 1 (

WEWE CONTROLLED TIMING)

(1, 2 ,3)

tWC

ADDRESS

tAW

CS1, CS

2

(7)

tAS

tWP

tWR

WE

(6)

tWZ

OUT

DATA

DATAIN

NOTES:

1.WE or CS must be HIGH during all address transitions.

2. A write occurs during the overlap (t

WR is measured from the earlier of

3. t

4. During this period, I/O pins are in the output state so that the input signals should not be applied.

5. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in the high-impedance state.

6. Transition is measured ±200mV from steady state.

WP) of a LOW

CS

(4)

tDW

CS

or WE going HIGH to the end of the write cycle.

and a LOW WE.

tDH

DATA VALID

tOW

(6)

(4)

2989 drw 08

6.3 6

IDT7188S/L
CMOS STATIC RAM 64K (16K x 4-BIT) MILITARY TEMPERATURE RANGE

TIMING WAVEFORM OF WRITE CYCLE NO. 2 (

CSCS CONTROLLED TIMING)

(1,2,3,5)

tWC

ADDRESS

tAW

CS

t

tAS

tCW

tWR

WE

tDW

IN

DATA

NOTES:

1.WE or CS must be HIGH during all address transitions.

2. A write occurs during the overlap (t

WR is measured from the earlier of

3. t

4. During this period, I/O pins are in the output state so that the input signals should not be applied.

5. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in the high-impedance state.

6. Transition is measured ±200mV from steady state.

WP) of a LOW

CS

or WE going HIGH to the end of the write cycle.

CS

and a LOW WE.

DATA VALID

tDH

2989 drw 09

ORDERING INFORMATION

IDT7188
Device

Type

X

PowerXXSpeedXPackage

X

Process/

Temperature

Range

B

Military (–55°C to +125°C)
Compliant to MIL-STD-883, Class B

D 300 mil Ceramic DIP (D22-1)

25
35
45
55

Speed in nanoseconds

70
85

S
L

Standard Power
Low Power

2989 drw 10

6.3 7