Datasheet IDT7164L20D, IDT7164L20DB, IDT7164L20P, IDT7164L20PB, IDT7164L20TD Datasheet (Integrated Device Technology Inc)

Integrated Device Technology, Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES MAY 1996

1996 Integrated Device Technology, Inc. 2967/8
For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

FEATURES:

• High-speed address/chip select access time
— Military: 20/25/30/35/45/55/70/85ns (max.)
— Commercial: 15/20/25/35/70ns (max.)

• Low power consumption

• Battery backup operation — 2V data retention voltage
(L Version only)

• Produced with advanced CMOS high-performance
technology

• Inputs and outputs directly TTL-compatible

• Three-state outputs

• Available in:
— 28-pin DIP and SOJ

• Military product compliant to MIL-STD-883, Class B

DESCRIPTION:

The IDT7164 is a 65,536 bit high-speed static RAM orga­nized as 8K x 8. It is fabricated using IDT’s high-performance,
high-reliability CMOS technology.

Address access times as fast as 15ns are available and the
circuit offers a reduced power standby mode. When

CS

1 goes

HIGH or CS2 goes LOW, the circuit will automatically go to,
and remain in, a low-power stand by mode. The low-power (L)
version also offers a battery backup data retention capability
at power supply levels as low as 2V.

All inputs and outputs of the IDT7164 are TTL-compatible
and operation is from a single 5V supply, simplifying system
designs. Fully static asynchronous circuitry is used, requiring
no clocks or refreshing for operation.

The IDT7164 is packaged in a 28-pin 300 mil DIP and SOJ;
and 28-pin 600 mil DIP.

Military grade product is manufactured in compliance with
the latest revision of MIL-STD-883, Class B, making it ideally
suited to military temperature applications demanding the
highest level of performance and reliability.

FUNCTIONAL BLOCK DIAGRAM

ADDRESS

DECODER

65,536 BIT

MEMORY ARRAY

I/O CONTROL

2967 drw 01

WE

CS

V

CC

GND

I/O

0

I/O7

CONTROL

LOGIC

OE

2

CS

1

A

0

A

12

0

7

6.1

1

IDT7164S
IDT7164L

CMOS STATIC RAM
64K (8K x 8-BIT)

6.1 2

IDT7164S/L
CMOS STATIC RAM 64K (8K x 8-BIT) MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN CONFIGURATIONS

PIN DESCRIPTIONS

Name Description

A

0–A12 Address

I/O

0–I/O7 Data Input/Output

CS

1 Chip Select

CS

2 Chip Select

WE

Write Enable

OE

Output Enable
GND Ground
VCC Power

2967 tbl 01

ABSOLUTE MAXIMUM RATINGS

(1)

Symbol Rating Com’l. Mil. Unit

V

TERM

(2)

Terminal Voltage –0.5 to +7.0 –0.5 to +7.0 V

with Respect

to GND

T

A Operating 0 to +70 –55 to +125 °C

Temperature

T

BIAS Temperature –55 to +125 –65 to +135 °C

Under Bias

T

STG Storage –55 to +125 –65 to +150 °C

Temperature

P

T Power Dissipation 1.0 1.0 W

I

OUT DC Output 50 50 mA

Current

NOTES: 2967 tbl 03

1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.

2. V

TERM must not exceed VCC + 0.5V.

DIP/SOJ

TOP VIEW

TRUTH TABLE

(1,2,3)

WEWECS

CS

1 CS2

OEOEI/O Function

X H X X High-Z Deselected – Standby (I

SB)

X X L X High-Z Deselected – Standby (I

SB)

XV

HC VHC or X High-Z Deselected –Standby (ISB1)

V

LC

XXVLC X High-Z Deselected –Standby (ISB1)
H L H H High-Z Output Disabled
H L H L Data

OUT Read Data

L L H X Data

IN Write Data

NOTES: 2967 tbl 02

1. CS2 will power-down

CS

1, but CS1 will not power-down CS2.

2. H = V

IH, L = VIL, X = don't care.

3. V

LC = 0.2V, VHC = VCC - 0.2V

RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE

Grade Temperature GND VCC

Military –55°C to +125°C 0V 5V ± 10%

Commercial 0°C to +70°C 0V 5V ± 10%

2967 tbl 04

RECOMMENDED DC OPERATING
CONDITIONS

Symbol Parameter Min. Typ. Max. Unit

V

CC Supply Voltage 4.5 5.0 5.5 V

GND Supply Voltage 0 0 0 V

V

IH Input HIGH Voltage 2.2 — VCC + 0.5 V

V

IL Input LOW Voltage –0.5

(1)

— 0.8 V

NOTE: 2967 tbl 05

1. VIL (min.) = –1.5V for pulse width less than 10ns, once per cycle.

2967 drw 02

5
6
7
8
9
10
11
12

A12

1
2
3
4

24
23

22
21

20
19

18
17

D28-1
D28-3
P28-1
P28-2

SO28-5

13
14

28
27
26
25

A7
A6
A5
A4
A3
A2
A1

A0
I/O0
I/O1

VCC

WE

A

8

A9
A11

OE

A

10

CS

1

I/O7

16
15

I/O2

GND

I/O

6

I/O5
I/O4
I/O3

NC

CS

2

6.1 3

IDT7164S/L
CMOS STATIC RAM 64K (8K x 8-BIT) MILITARY AND COMMERCIAL TEMPERATURE RANGES

DC ELECTRICAL CHARACTERISTICS

(1)

(VCC = 5.0V ± 10%, VLC = 0.2V, VHC = VCC - 0.2V)

7164S15 7164S20 7164S25 7164S30
7164L15 7164L20 7164L25 7164L30

Symbol Parameter Power Com’l. Mil. Com’l. Mil. Com’l. Mil. Com’l. Mil. Unit

I

CC1 Operating Power Supply S 110 — 100 110 90 110 — 100 mA

Current,

CS

1 = VIL, CS2 = VIH,

Outputs Open, V

CC = Max., f = 0

(3)

L 100 — 90 100 80 100 — 90

I

CC2 Dynamic Operating Current S 180 — 170 180 170 180 — 170 mA

CS

1 = VIL, CS2 = VIH,

Outputs Open, V

CC = Max., f = fMAX

(3)

L 150 — 150 160 150 160 — 150

I

SB Standby Power Supply Current S 20 — 20 20 20 20 — 20 mA

(TTL Level),

CS

1 ≥ VIH or CS2 ≤ VIL

VCC = Max., Outputs Open, f = fMAX

(3)

L 3—353 5—5

I

SB1 Full Standby Power Supply Current S 15 — 15 20 15 20 — 20 mA

(CMOS Level), f = 0

(3)

, VCC = Max.

1. CS1 ≥ V

HC and CS2 ≥ VHC, or L 0.2 — 0.2 1 0.2 1 — 1

2. CS

2 ≤ VLC

CAPACITANCE (TA = +25°C, f = 1.0MHz)

Symbol Parameter

(1)

Conditions Max. Unit

C

IN Input Capacitance VIN = 0V 8 pF

C

I/O I/O Capacitance VOUT = 0V 8 pF

NOTE: 2967 tbl 06

1. This parameter is determined by device characterization, but is not
production tested.

DC ELECTRICAL CHARACTERISTICS

(1)

(Continued)

(VCC = 5.0V ± 10%, VLC = 0.2V, VHC = VCC - 0.2V)

7164S35 7164S45 7164S55 7164S70

(2)

/85

(4)

7164L35 7164L45 7164L55 7164L70

(2)

/85

(4)

Symbol Parameter Power Com’l. Mil. Com’l. Mil. Com’l. Mil. Com’l. Mil. Unit

I

CC1 Operating Power Supply S 90 100 — 100 — 100 90 100 mA

Current,

CS

1 = VIL, CS2 = VIH,

Outputs Open, VCC = Max., f = 0

(3)

L 8090—90—90 8090

I

CC2 Dynamic Operating Current S 150 160 — 160 — 160 150 160 mA

CS

1 = VIL, CS2 = VIH,

Outputs Open, VCC = Max., f = fMAX

(3)

L 130 140 — 130 — 125 130 120

I

SB Standby Power Supply Current S 20 20 — 20 — 20 20 20 mA

(TTL Level),

CS

1 ≥ VIH, or CS2 ≤ VIL

VCC = Max., Outputs Open, f = fMAX

(3)

L35—5—5 35

I

SB1 Full Standby Power Supply Current S 15 20 — 20 — 20 15 20 mA

(CMOS Level), f = 0

(3)

, VCC = Max.

1.

CS

1 ≥ VHC and CS2 ≥ VHC, or L 0.2 1 — 1 — 1 0.2 1

2. CS

2 ≤ VLC

NOTES: 2967 tbl 07

1. All values are maximum guaranteed values.

2. 70 ns available in both military and commercial devices.

3. f

MAX = 1/tRC (all address inputs are cycling at fMAX); f = 0 means no address input lines are changing.

4. Also available: 100ns military devices.

6.1 4

IDT7164S/L
CMOS STATIC RAM 64K (8K x 8-BIT) MILITARY AND COMMERCIAL TEMPERATURE RANGES

DC ELECTRICAL CHARACTERISTICS

(VCC = 5.0V ± 10%)

IDT7164S IDT7164L

Symbol Parameter Test Condition Min. Max. Min. Max. Unit

|I

LI| Input Leakage Current VCC = Max., MIL. — 10 — 5 µA

VIN = GND to VCC COM’L. — 5 — 2

|I

LO| Output Leakage Current V CC = Max., CS1 = VIH, MIL. — 10 — 5 µA

VOUT = GND to VCC COM’L. — 5 — 2

V

OL Output Low Voltage IOL = 8mA, VCC = Min. 0.4 — 0.4 V

IOL = 10mA, VCC = Min. — 0.5 — 0.5

V

OH Output High Voltage IOH = –4mA, VCC = Min. 2.4 — 2.4 — V

AC TEST CONDITIONS

Input Pulse Levels GND to 3.0V
Input Rise/Fall Times 5ns
Input Timing Reference Levels 1.5V
Output Reference Levels 1.5V
AC Test Load See Figures 1 and 2

2967 tbl 10

*Includes scope and jig capacitances

Figure 2. AC Test Load

(for t

CLZ1, tCLZ2, tOLZ, tCHZ1, tCHZ2, tOHZ, tOW, and tWHZ)

Figure 1. AC Test Load

DATA RETENTION CHARACTERISTICS OVER ALL TEMPERATURE RANGES

(L Version Only) (VLC = 0.2V, VHC = VCC - 0.2V)

Typ.

(1)

Max.

V

CC @VCC @

Symbol Parameter Test Condition Min. 2.0v 3.0V 2.0V 3.0V Unit

V

DR VCC for Data Retention — 2.0 — — — — V

I

CCDR Data Retention Current MIL. — 10 15 200 300 µA

COM’L. — 10 15 60 90

t

CDR

(3)

Chip Deselect to Data 1.

CS

1 ≥ VHC 0————ns

Retention Time CS

2 ≥ VHC, or

t

R

(3)

Operation Recovery Time 2. CS2 ≤ VLC tRC

(2)

————ns

|I

LI|

(3)

Input Leakage Current — — — 2 2 µA

NOTES: 2967 tbl 09

1. TA = +25°C.

2. t

RC = Read Cycle Time.

3. This parameter is guaranteed by device characterization, but is not production tested.

2967 drw 03

480Ω

30pF*

255Ω

DATA

OUT

5V

2967 drw 04

480Ω

5pF*

255Ω

DATA

OUT

5V

2967 tbl 08

6.1 5

IDT7164S/L
CMOS STATIC RAM 64K (8K x 8-BIT) MILITARY AND COMMERCIAL TEMPERATURE RANGES

AC ELECTRICAL CHARACTERISTICS (VCC = 5.0V ± 10%, All Temperature Ranges)

7164S15

(1)

7164S20 7164S25 7164S30

(2)

7164L15

(1)

7164L20 7164L25 7164L30

Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Unit

Read Cycle

tRC Read Cycle Time 15 — 20 — 25 — 30 — ns
tAA Address Access Time — 15 — 19 — 25 — 29 ns
tACS1

(3)

Chip Select-1 Access Tim — 15 — 20 — 25 — 30 ns

tACS2

(3)

Chip Select-2 Access Time — 20 — 25 — 30 — 35 ns

tCLZ1,2

(4)

Chip Select-1, 2 to Output in Low-Z 5 — 5 — 5 — 5 — ns
tOE Output Enable to Output Valid — 7 — 8 — 12 — 15 ns
tOLZ

(4)

Output Enable to Output in Low-Z 0 — 0 — 0 — 0 — ns
tCHZ1,2

(4)

Chip Select-1, 2 to Output in High-Z — 8 — 9 — 13 — 13 ns
tOHZ

(4)

Output Disable to Output in High-Z — 7 — 8 — 10 — 12 ns
tOH Output Hold from Address Change 5 — 5 — 5 — 5 — ns
tPU

(4)

Chip Select to Power Up Time 0 — 0 — 0 — 0 — ns
tPD

(4)

Chip Deselect to Power Down Time — 15 — 20 — 25 — 30 ns

Write Cycle

tWC Write Cycle Time 15 — 20 — 25 — 30 — ns
tCW1, 2 Chip Select to End-of-Write 14 — 15 — 18 — 22 — ns
tAW Address Valid to End-of-Write 14 — 15 — 18 — 22 — ns
tAS Address Set-up Time 0 — 0 — 0 — 0 — ns
tWP Write Pulse Width 14 — 15 — 21 — 23 — ns
tWR1 Write Recovery Time (

CS

1,

WE

) 0—0—0— 0—ns
tWR2 Write Recovery Time (CS2) 5—5—5— 5—ns
tWHZ

(4)

Write Enable to Output in High-Z — 6 — 8 — 10 — 12 ns
tDW Data to Write Time Overlap 8 — 10 — 13 — 13 — ns
tDH1 Data Hold from Write Time (

CS

1,

WE

) 0—0—0— 0—ns
tDH2 Data Hold from Write Time (CS2) 5—5—5— 5—ns
t

OW

(4)

Output Active from End-of-Write 4 — 4 — 4 — 4 — ns

NOTES: 2967 tbl 11

1. 0° to +70°C temperature range only.

2. –55°C to +125°C temperature range only. Also available: 100ns military devices.

3. Both chip selects must be active for the device to be selected.

4. This parameter is guaranteed by device characterization, but is not production tested.

6.1 6

IDT7164S/L
CMOS STATIC RAM 64K (8K x 8-BIT) MILITARY AND COMMERCIAL TEMPERATURE RANGES

AC ELECTRICAL CHARACTERISTICS (Continued) (VCC = 5.0V ± 10%, All Temperature Ranges)

7164S35 7164S45

(2)

7164S55

(2)

7164S70/85

(2)

7164L35 7164L45

(2)

7164L55

(2)

7164L70/85

(2)

Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Unit

Read Cycle

tRC Read Cycle Time 35 — 45 — 55 — 70/85 — ns
tAA Address Access Time — 35 — 45 — 55 — 70/85 ns
tACS1

(3)

Chip Select-1 Access Time — 35 — 45 — 55 — 70/85 ns

tACS2

(3)

Chip Select-2 Access Time — 40 — 45 — 55 — 70/85 ns

tCLZ1,2

(4)

Chip Select-1, 2 to Output in Low-Z 5 — 5 — 5 — 5 — ns
tOE Output Enable to Output Valid — 18 — 25 — 30 — 35/40 ns
tOLZ

(4)

Output Enable to Output in Low-Z 0 — 0 — 0 — 0 — ns
tCHZ1,2

(4)

Chip Select-1, 2 to Output in High-Z — 15 — 20 — 25 — 30/35 ns
tOHZ

(4)

Output Disable to Output in High-Z — 15 — 20 — 25 — 30/35 ns
tOH Output Hold from Address Change 5 — 5 — 5 — 5 — ns
tPU

(4)

Chip Select to Power Up Time 0 — 0 — 0 — 0 — ns
tPD

(4)

Chip Deselect to Power Down Time — 35 — 45 — 55 — 70/85 ns

Write Cycle

tWC Write Cycle Time 35 — 45 — 55 — 70/85 — ns
tCW1, 2 Chip Select to End-of-Write 25 — 33 — 50 — 60/75 — ns
tAW Address Valid to End-of-Write 25 — 33 — 50 — 60/75 — ns
tAS Address Set-up Time 0 — 0 — 0 — 0 — ns
tWP Write Pulse Width 25 — 25 — 50 — 60/75 — ns
tWR1 Write Recovery Time (

CS

1,

WE

) 0—0—0— 0—ns
tWR2 Write Recovery Time (CS2) 5—5—5— 5—ns
tWHZ

(4)

Write Enable to Output in High-Z — 14 — 18 — 25 — 30/35 ns
tDW Data to Write Time Overlap 15 — 20 — 25 — 30/35 — ns
tDH1 Data Hold from Write Time (

CS

1,

WE

) 0—0—0— 0—ns
tDH2 Data Hold from Write Time (CS2) 5—5—5— 5—ns
t

OW

(4)

Output Active from End-of-Write 4 — 4 — 4 — 4 — ns

NOTES: 2967 tbl 11

1. 0° to +70°C temperature range only.

2. –55°C to +125°C temperature range only. Also available: 100ns military devices.

3. Both chip selects must be active for the device to be selected.

4. This parameter is guaranteed by device characterization, but is not production tested.

6.1 7

IDT7164S/L
CMOS STATIC RAM 64K (8K x 8-BIT) MILITARY AND COMMERCIAL TEMPERATURE RANGES

TIMING WAVEFORM OF READ CYCLE NO. 1

(1)

NOTES:

1.WE is HIGH for Read cycle.

2. Device is continuously selected,

CS

1 is LOW, CS2 is HIGH.

3. Address valid prior to or coincident with

CS

1 transition LOW and CS2 transition HIGH.

4.OE is LOW.

5. Transition is measured ±200mV from steady state.

TIMING WAVEFORM OF READ CYCLE NO. 2

(1, 2, 4)

TIMING WAVEFORM OF READ CYCLE NO. 3

(1, 3, 4)

2967 drw 05

ADDRESS

CS

1

OE

DATA

OUT

CS2

tRC

tAA tOH

tACS2

tCLZ2

(5)

tOE

tACS1

tCLZ1

(5)

tOLZ

(5)

tCHZ2

(5)

tOHZ

(5)

tCHZ1

(5)

DATA VALID

2967 drw 06

ADDRESS

DATA

OUT

tRC

tAA

tOH

tOH

DATA VALID

2967 drw 07

DATA OUT

tACS2

(5)

CS

1

CS2

tCLZ2

tACS1

(5)

tCLZ1

tPU

tPD

ICC

ISB

tCHZ2

(5)

tCHZ1

(5)

DATA VALID

POWER
SUPPLY

CURRENT

6.1 8

IDT7164S/L
CMOS STATIC RAM 64K (8K x 8-BIT) MILITARY AND COMMERCIAL TEMPERATURE RANGES

TIMING WAVEFORM OF WRITE CYCLE NO. 1 (

WEWE CONTROLLED TIMING)

(1, 2, 6)

TIMING WAVEFORM OF WRITE CYCLE NO. 2 (

CSCS CONTROLLED TIMING)

(1, 2)

NOTES:

1.WE,

CS

1 or CS2 must be inactive during all address transitions.

2. A write occurs during the overlap of a LOW WE, a LOW

CS

1 and a HIGH CS2.

3. t

WR1, 2 is measured from the earlier of CS1 or

WE

going HIGH or CS2 going LOW to the end of the write cycle.

4. During this period, I/O pins are in the output state so that the input signals must not be applied.

5. If the

CS

1 LOW transition or CS2 HIGH transition occurs simultaneously with or after the

WE

LOW transition, the outputs remain in a high-impedance state.

6.OE is continuously HIGH. If OE is LOW during a WE controlled write cycle, the write pulse width must be the larger of t

WP or (tWHZ +tDW) to allow the

I/O drivers to turn off and data to be placed on the bus for the required t

DW. If

OE

is HIGH during a WE controlled write cycle, this requirement does not

apply and the minimum write pulse width is as short as the specified t

WP.

7. Transition is measured ±200mV from steady state.

ADDRESS

tWC

tWHZ

(7)

2967 drw 08

CS

1

DATA OUT

CS2

tAS

tAW

tWR1

(3)

WE

tWP

tOW

(7)

DATA IN

tDH1, 2tDW

DATA VALID

(4)

(6)

2967 drw 09

ADDRESS

CS

1

CS2

tWC

tAS

WE

tCW

tWR2

(3)

tAW

DATA IN

tDH1,2tDW

DATA VALID

tWR1

(3)

(5)

6.1 9

IDT7164S/L
CMOS STATIC RAM 64K (8K x 8-BIT) MILITARY AND COMMERCIAL TEMPERATURE RANGES

ORDERING INFORMATION

LOW V

CC DATA RETENTION WAVEFORM

2967 drw 10

DATA

RETENTION

MODE

4.5V 4.5V
V

DR

≥

2V

V

IH

V

IH

t

R

t

CDR

V

CC

CS

V

DR

X

PowerXXSpeed

XXX

Package

X

Process/

Temperature

Range

Blank

Commercial (0°C to +70°C)

B

Military (–55°C to +125°C)
Compliant to MIL-STD-883, Class B

Y
TD
D
P
TP

300 mil SOJ (SO28-5)
300 mil CERDIP (D28-3)
600 mil CERDIP (D28-1)
600 mil Plastic DIP (P28-1)
300 mil Plastic DIP (P28-2)

15
20
25
30
35
45
55
70
85

Commercial Only

Military Only
Military Only

Military Only
Military Only

S
L

Standard Power
Low Power

Device

Type

7164

IDT

Speed in nanoseconds

2967 drw 11