Datasheet IDT7133SA20F, IDT7133SA20G, IDT7133SA20J, IDT7133SA20PF, IDT7133SA25F Datasheet (Integrated Device Technology Inc)

Integrated Device Technology, Inc.

HIGH-SPEED
2K x 16 CMOS DUAL-PORT
STATIC RAMS

IDT7133SA/LA
IDT7143SA/LA

FEATURES:

• High-speed access
— Military: 25/35/45/55/70/90ns (max.)
— Commercial: 20/25/35/45/55/70/90ns (max.)

• Low-power operation
— IDT7133/43SA

Active: 500 mW (typ.)
Standby: 5mW (typ.)

— IDT7133/43LA

Active: 500mW (typ.)
Standby: 1mW (typ.)

• Versatile control for write: separate write control for
lower and upper byte of each port

• MASTER IDT7133 easily expands data bus width to 32
bits or more using SLAVE IDT7143

• On-chip port arbitration logic (IDT7133 only)

•

BUSY

output flag on IDT7133;

• Fully asynchronous operation from either port

• Battery backup operation–2V data retention

• TTL-compatible; single 5V (±10%) power supply

• Available in 68-pin ceramic PGA, 68-pin Flatpack, 68-pin
PLCC, and 100-pin TQFP

• Military product compliant to MIL-STD-883, Class B

• Industrial temperature range (–40°C to +85°C) is avail­able, tested to military electrical specifications

BUSY

input on IDT7143

DESCRIPTION:

The IDT7133/7143 are high-speed 2K x 16 Dual-Port Static
RAMs. The IDT7133 is designed to be used as a stand-alone
16-bit Dual-Port RAM or as a “MASTER” Dual-Port RAM
together with the IDT7143 “SLAVE” Dual-Port in 32-bit-or­more word width systems. Using the IDT MASTER/SLAVE
Dual-Port RAM approach in 32-bit-or-wider memory system
applications results in full-speed, error-free operation without
the need for additional discrete logic.

Both devices provide two independent ports with separate
control, address, and I/O pins that permit independent, asyn­chronous access for reads or writes to any location in
memory. An automatic power down feature, controlled by CE,
permits the on-chip circuitry of each port to enter a very low
standby power mode.

Fabricated using IDT’s CMOS high-performance technol­ogy, these devices typically operate on only 500mW of power.
Low-power (LA) versions offer battery backup data retention
capability, with each port typically consuming 200µW for a 2V
battery.

The IDT7133/7143 devices have identical pinouts. Each is
packaged in a 68-pin ceramic PGA, a 68-pin flatpack, a 68-pin
PLCC, and a 100-pin TQFP. Military grade product is manu­factured in compliance with the latest revision of MIL-STD­883, Class B, making it ideally suited to military temperature
applications demanding the highest level of performance and
reliability.

FUNCTIONAL BLOCK DIAGRAM

(2)

R/

W

LUB

CE

L

(2)

R/

W

LLB

OE

L

I/O8L - I/O15L

I/O0L - I/O7L

(1)

BUSY

L

A10L

A0L

NOTES:

1. IDT7133 (MASTER): BUSY is
open drain output and requires
pull-up resistor of 270Ω.
IDT7143 (SLAVE): BUSY is
input.

2. "LB" designates "Lower Byte"
and "UB" designates "Upper
Byte" for the R/W signals.

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

ADDRESS

DECODER

CE

L

CONTROL

11

I/O

ARBITRATION

(IDT7133 ONLY)

MEMORY

ARRAY

LOGIC

I/O

CONTROL

ADDRESS
DECODER

11

CE

OE

I/O8R - I/O15R
I/O0R - I/O7R

A

A0R

R

MILITARY AND COMMERCIAL TEMPERATURE RANGES OCTOBER 1996

©1996 Integrated Device Technology, Inc. DSC-2746/6

For latest information contact IDT’s web site at www.idt.com or fax-on-demand at 408-492-8391.

6.14 1

R/

CE

R/

R

BUSY

10R

2746 drw 01

(2)

W

RUB

R

(2)

W

RLB

(1)

R

IDT7133SA/LA, IDT7143SA/LA
HIGH-SPEED 2K x 16 DUAL-PORT RAMS MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN CONFIGURATIONS

I/O
I/O
I/O
I/O
I/O

I/O

(1,2)

INDEX

I/O

9L

10L
11L
12L
13L
14L

15L

V

CC

GND

I/O

0R

I/O

1R

I/O

2R

I/O

3R

I/O

4R

I/O

5R

I/O

6R

I/O

7R

LUB

8L

I/O

7L

I/O

6L

I/O

5L

I/O

4L

I/O

3L

I/O

2L

I/O

1L

I/O

0L

I/O

CC

V

W

R/

LLB

W

R/

L

OE

10L

A

A9LA

98765432168 67 66 65 64 63 62 61

10
11
12
13
14
15
16
17
18
19
20

IDT7133/43

J68-1

&

F68-1

PLCC/FLATPACK

TOP VIEW

(3)

21
22
23
24
25
26

27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43

8R

I/O

9R

I/O

10R

I/O

11R

I/O

12R

I/O

13R

I/O

14R

I/O

15R

I/O

GND

RUB

W

R/

RLB

W

R/

R

OE

10R

A

9R

A

8R

A

8L

7L

A

A

6L

60

A

5L

59
58

A

4L

57

A

3L

56

A

2L

A

1L

55
54

A

0L

53

BUSY

L

52

CE

L

51

CE

R

50

BUSY

R

49

A

0R

48

A

1R

47

A

2R

46

A

3R

45

A

4R

44

A

5R

7R

6R

A

A

2746 drw 02

INDEX

N/C
N/C
N/C
N/C

I/O

10L

I/O

11L

I/O

12L

I/O

13L

GND

I/O

14L

I/O

15L

V

GND
I/O
I/O
I/O

V
I/O
I/O
I/O
I/O

N/C
N/C
N/C
N/C

LUB

LLB

9L

8L

7L

6L

5L

4L

3L

I/O

I/O

I/O

I/O

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76

1
2
3
4
5
6
7
8

9
10
11
12

CC

13

0R

14

1R

15

2R

16

CC

17

3R

18

4R

19

5R

20

6R

21

22

23

24

25

26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

7R

8R

9R

10R

I/O

I/O

I/O

I/O

I/O

11R

I/O

I/O

12R

I/O

I/O

13R

I/O

2L

I/O

14R

I/O

GND

GND

1L

I/O

15R

I/O

L

0L

CC

OE

V

I/O

IDT7133/43

PN100-1

100-PIN

TQFP

TOP VIEW

R

RLB

OE

GND

W

R/

W

R/

N/C

(3)

N/C

R

CE

L

CE

RUB

W

R/

/W

R

N/C

N/C

N/C

N/C

N/C

N/C

10R

A

10L

A

9R

A

9L

8L

7L

6L

A

A

A

A

N/C

75
74

N/C

73

N/C

72

N/C

71

5L

A

70

A

4L

69

A

3L

68

A

2L

67

A

1L

66

A

0L

65

N/C

64

BUSY

GND
N/C

BUSY

N/C

0R

A
A

1R

A

2R

A

3R

A

4R

N/C
N/C
N/C
N/C

L

R

63
62
61
60
59
58
57
56
55
54
53
52
51

8R

7R

5R

6R

A

A

A

A

2746 drw 03

NOTES:

1. Both V

CC pins must be connected to the supply to ensure reliable operation.

2. Both GND pins must be connected to the supply to ensure reliable operation.

3. This text does not indicate orientation of the actual part-marking.

6.14 2

IDT7133SA/LA, IDT7143SA/LA
HIGH-SPEED 2K x 16 DUAL-PORT RAMS MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN CONFIGURATIONS (CONT'D)

11

10

09

08

07

06

05

04

51

52 49 47 45 43 41 39 37 3553 34

A

8L

5455

A

10L

5657

R/

W

LLB

5859

V

CC

R/

6061

I/O

1L

6263

I/O

3L

6465

I/O

5L

50 48 46 44 42 40 38 36

A

7L

9L

LUB

0L

2L

4L

5L

A

4L

L

A

A

A

OE

W

I/O

I/O

I/O

6L

(1,2)

A

3L

A

1L

A

2L

A

0L

TOP VIEW

L

BUSY

CE

L

IDT7133/43

GU68-1

PGA

CE

BUSY

(3)

R

A

R

A

2R

A

3R

4R

A

5R

32 33

A

8R

30 31

A

10R

28 29

R/

W

RLB

26 27

GND

24 25

I/O

14R

22 23

I/O

12R

A

6R

A

7R

A

9R

OE

R

R/

W

RUB

I/O

15R

I/O

13R

0R

A

A

1R

6667

I/O

7L

I/O

168

2

I/O

I/O

10L

6L

3

9L

4

I/O

I/O

11L

12L

5

6

I/O

I/O

13L

14L

7

8

I/O

9

15L

GND

10

V

CC

I/O

0R

03

02

01

INDEX

I/O

8L

ABCDEFGHJKL

NOTES:

1. Both V

CC pins must be connected to the supply to ensure reliable operation.

2. Both GND pins must be connected to the supply to ensure reliable operation.

3. This text does not indicate orientation of the actual part-marking.

PIN NAMES

Left Port Right Port Names

L

CE

LUB R/WRUB Upper Byte Read/Write Enable

R/

W

LLB R/WRLB Lower Byte Read/Write Enable

R/

W

L

OE

A

0L – A10L A0R – A10R Address

0L – I/O15L I/O0R – I/O15R Data Input/Output

I/O

BUSY

L

CC Power

V
GND Ground

CE

R Chip Enable

OE

R Output Enable

BUSY

R Busy Flag

2746 tbl 01

20 21

I/O

7R

11R

19

I/O

9R

2746 drw 04

I/O

10R

11

12

I/O

I/O

13

1R

14

2R

I/O

I/O

15

3R

16

4R

I/O

I/O

18

5R

I/O

8R

17

I/O

6R

6.14 3

IDT7133SA/LA, IDT7143SA/LA
HIGH-SPEED 2K x 16 DUAL-PORT RAMS MILITARY AND COMMERCIAL TEMPERATURE RANGES

ABSOLUTE MAXIMUM RATINGS

(1)

Symbol Rating Commercial Military Unit

(2)

V

TERM

Terminal Voltage –0.5 to +7.0 –0.5 to +7.0 V
with Respect
to GND

A Operating 0 to +70 –55 to +125 °C

T

Temperature

T

BIAS Temperature –55 to +125 –65 to +135 °C

Under Bias

STG Storage –55 to +125 –65 to +150 °C

T

Temperature

(3)

P

T

Power 2.0 2.0 W
Dissipation

I

OUT DC Output 50 50 mA

Current

NOTES: 2746 tbl 02

1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating condi­tions for extended periods may affect reliability.

2. V

TERM must not exceed Vcc + 0.5V for more than 25% of the cycle time

or 10ns maximum, and is limited to
+ 0.5V.

< 20mA for the period of VTERM > Vcc

CAPACITANCE

(1)

(TA = +25°C, f = 1.0MHZ) TQFP ONLY

Symbol Parameter Conditions

C

IN Input Capacitance VIN = 3dV 9 pF

C

OUT Input/Output VOUT = 3dV 10 pF

Capacitance

NOTES: 2746 tbl 03

1. This parameter is determined by device characterization but is not
production tested.

2. 3dV represents the interpolated capacitance when the input and output
signals switch from 0V to 3V or from 3V to 0V.

(2)

Max. Unit

RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE

Ambient

Grade Temperature GND V

CC

Military –55°C to +125°C 0V 5.0V ± 10%
Commercial 0°C to +70°C 0V 5.0V ± 10%

2746 tbl 04

RECOMMENDED DC OPERATING
CONDITIONS

Symbol Parameter Min. Typ. Max. Unit

V

CC Supply Voltage 4.5 5.0 5.5 V

GND Supply Voltage 0 0 0 V
V

IH Input High Voltage 2.2 — 6.0 V
IL Input Low Voltage –0.5

V

NOTES: 2746 tbl 05

1. VIL (min.) = -1.5V for pulse width less than 10ns.

2. V

TERM must not exceed Vcc + 0.5V.

(1)

— 0.8 V

DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE

Symbol Parameter Test Conditions Min. Max. Min. Max. Unit

LI| Input Leakage Current

|I

LO| Output Leakage Current

|I
V

OL Output Low Voltage (I/O0-I/O15)IOL = 4mA — 0.4 — 0.4 V
OL Open Drain Output Low Voltage IOL = 16mA — 0.5 — 0.5 V

V

(

BUSY

)

V

OH Output High Voltage IOH = -4mA 2.4 — 2.4 — V

NOTE: 2746 tbl 06

1. At Vcc < 2.0V, input leakages are undefined.

(1)

VCC = 5.5V, VIN = 0V to VCC —10—5µA

CE

= VIH, VOUT = 0V to VCC —10—5µA

6.14 4

(Either port, VCC = 5.0V ± 10%)

IDT7133SA IDT7133LA
IDT7143SA IDT7143LA

IDT7133SA/LA, IDT7143SA/LA
HIGH-SPEED 2K x 16 DUAL-PORT RAMS MILITARY AND COMMERCIAL TEMPERATURE RANGES

DC ELECTRICAL CHARACTERISTICS

(3)

OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE

IDT7133X20

Test IDT7143X20

(2)

Symbol Parameter Condition Version Typ.

I

CC Dynamic Operating

CE

= VIL MIL. S – – 250 330 240 325 mA

Current Outputs Open L – – 230 300 220 295
(Both Ports Active) f = f

MAX

COM’L. S 250 310 250 300 240 295

(4)

L 230 280 230 270 210 250

SB1 Standby Current

I

(Both Ports — TTL f = f

CE

L and CER = VIH MIL. S – – 25 90 25 75 mA

(4)

MAX

L– – 2580 2565

Level Inputs) COM’L. S 25 80 25 80 25 70

L2570 2570 2560

I

SB2 Standby Current

(One Port — TTL
Level Inputs) f = f

CE

"A" = VIL and MIL. S – – 140 230 120 200 mA

CE

"

(5)

B" = VIH
MAX

, L – – 100 190 100 180

(4)

, Active COM’L. S 140 200 140 200 120 180

Port Outputs Open L 120 180 100 170 100 160

SB3 Full Standby Current Both Ports CEL & MIL. S – – 1 30 1 30 mA

I

(Both Ports —
CMOS Level Inputs) V

I

SB4 Full Standby Current

(One Port — All

CE

R > VCC - 0.2V L – – 0.2 10 0.2 10

IN > VCC - 0.2V or COM’L. S 1 15 1 15 1 15
IN < 0.2V, f = 0

V

CE

"A" < 0.2V and MIL. S – – 140 220 120 190 mA

CE

"B" > VCC - 0.2V

(5)

L 0.2 5 0.2 4 0.2 4

(6)

CMOS Level Inputs) VIN > VCC - 0.2V or L – – 120 200 100 170

V

IN < 0.2V COM’L. S 140 190 140 190 120 170

Active Port Outputs
Open, f = f

NOTES: 2746 tbl 07

1. Commercial only, 0°C to +70°C temperature range.

2. V

CC = 5V, TA = +25°C for Typ., and are not production tested. ICCDC = 180mA (Typ.)

3. "X" in part numbers indicates power rating (SA or LA).

4. At f = f

5. f = 0 means no address or control lines change. Applies only to inputs at CMOS level standby.

6. Port "A" may be either left or right port. Port "B" is the opposite from port "A".

MAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, and using “AC Test Conditions”

of input levels of GND to 3V.

MAX

(4)

L 120 170 120 170 100 150

Max. Typ.

(VCC = 5.0V ± 10%)

(1)

(1)

IDT7133X25 IDT7133X35
IDT7143X25 IDT7143X35

(2)

Max. Typ.

(2)

Max. Unit

6.14 5

IDT7133SA/LA, IDT7143SA/LA
HIGH-SPEED 2K x 16 DUAL-PORT RAMS MILITARY AND COMMERCIAL TEMPERATURE RANGES

DC ELECTRICAL CHARACTERISTICS

(3)

OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE

IDT7133X45 IDT7133X55 IDT7133X70/90

Test IDT7143X45 IDT7143X55 IDT7143X70/90

Symbol Parameter Condition Version Typ.

CC Dynamic Operating

I

CE

= VIL MIL. S 230 320 230 315 230 310 mA

Current Outputs Open L 210 290 210 285 210 280
(Both Ports Active) f = f

MAX

COM’L. S 230 290 230 285 230 280

(4)

L 210 260 210 255 210 250

I

SB1 Standby Current

(Both Ports — TTL f = f

CE

L and CER = VIH MIL. S 25 80 25 80 25 75 mA

(4)

MAX

L2570 2570 2565

Level Inputs) COM’L. S 25 75 25 70 25 70

L2565 2560 2560

I

SB2 Standby Current

(One Port — TTL
Level Inputs) f = f

CE

"A" = VIL and MIL. S 120 210 120 210 120 200 mA

CE

"

(5)

B" = VIH
MAX

, L 100 190 100 190 100 180

(4)

, Active COM’L. S 120 190 120 180 120 180

Port Outputs Open L 100 170 100 160 100 160

I

SB3 Full Standby Current Both Ports CEL & MIL. S 1 30 1 30 1 30 mA

(Both Ports —
CMOS Level Inputs) V

I

SB4 Full Standby Current

(One Port — All

R > VCC - 0.2V L 0.2 10 0.2 10 0.2 10

CE

IN > VCC - 0.2V or COM’L. S 1 15 1 15 1 15

V

IN < 0.2V, f = 0

CE

"A" < 0.2V and MIL. S 120 200 120 200 120 190 mA
"B" > VCC - 0.2V

CE

(5)

L 0.2 4 0.2 4 0.2 4

(6)

CMOS Level Inputs) VIN > VCC - 0.2V or L 100 180 100 180 100 170

V

IN < 0.2V COM’L. S 120 180 120 170 120 170

Active Port Outputs
Open, f = f

MAX

(4)

L 100 160 100 150 100 150

(2)

Max. Typ.

(VCC = 5.0V ± 10%)

(2)

Max. Typ.

(2)

Max. Unit

NOTES: 2746 tbl 07

1. Commercial only, 0°C to +70°C temperature range.

2. V

CC = 5V, TA = +25°C for Typ., and are not production tested. ICCDC = 180mA (Typ.)

3. "X" in part numbers indicates power rating (SA or LA).

4. At f = f

5. f = 0 means no address or control lines change. Applies only to inputs at CMOS level standby.

6. Port "A" may be either left or right port. Port "B" is the opposite from port "A".

MAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1 / tRC, and using “AC Test Conditions”

of input levels of GND to 3V.

6.14 6

IDT7133SA/LA, IDT7143SA/LA
HIGH-SPEED 2K x 16 DUAL-PORT RAMS MILITARY AND COMMERCIAL TEMPERATURE RANGES

DATA RETENTION CHARACTERISTICS

(LA Version Only) VLC = 0.2V, VHC = VCC - 0.2V

IDT7133LA/IDT7143LA

Symbol Parameter Test Condition Min. Typ. Max. Unit

V

DR VCC for Data Retention VCC = 2V 2.0 — — V

I

CCDR Data Retention Current

(3)

t

CDR
R

t

(3)

Chip Deselect to Data Retention Time 0 — — ns
Operation Recovery Time tRC

NOTES: 2746 tbl 08

1. Vcc = 2V, TA = +25°C, and are not production tested.

2. t

RC = Read Cycle Time.

3. This parameter is guaranteed but is not production tested.

CE

≥ VHC MIL. — 100 4000 µA

V

IN ≥ VHC or ≤ VLC COM’L. — 100 1500

(2)

—— ns

DATA RETENTION WAVEFORM

DATA RETENTION MODE

V

CC

t

CDR

CE

V

IH

AC TEST CONDITIONS

Input Pulse Levels GND to 3.0V
Input Rise/Fall Times 5ns
Input Timing Reference Levels 1.5V
Output Reference Levels 1.5V
Output Load Figures 1, 2, and 3

5V

1250Ω

DATA

OUT

775Ω

30pF

DATA

2746 tbl 09

OUT

V

DR

≥ 2V4.5V 4.5V

V

DR

5V

775Ω

1250Ω

5pF*

t

R

IH

V

2746 drw 05

5V

270Ω

BUSY

30pF

Figure 1. AC Output Load Figure 3.

Figure 2. Output Load

(for t

LZ, tHZ, tWZ, tOW)

*Including scope and jig

6.14 7

BUSYBUSY

BUSY

AC Output Load

BUSYBUSY

(IDT7133 only)

2746 drw 06

IDT7133SA/LA, IDT7143SA/LA
HIGH-SPEED 2K x 16 DUAL-PORT RAMS MILITARY AND COMMERCIAL TEMPERATURE RANGES

AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE

IDT7133X20
IDT7143X20

Symbol Parameter Min. Max. Min. Max. Min. Max. Unit

READ CYCLE

t

RC Read Cycle Time 20 — 25 — 35 — ns
AA Address Access Time — 20 — 25 — 35 ns

t
t

ACE Chip Enable Access Time — 20 — 25 — 35 ns

t

AOE Output Enable Access Time — 12 — 15 — 20 ns

t

OH Output Hold from Address Change 3 — 0 — 0 — ns

t

LZ Output Low-Z Time
HZ Output High-Z Time

t
t

PU Chip Enable to Power Up Time

t

PD Chip Disable to Power Down Time

Symbol Parameter Min. Max. Min. Max. Min. Max. Unit

READ CYCLE

t

RC Read Cycle Time 45 — 55 — 70/90 — ns

t

AA Address Access Time — 45 — 55 — 70/90 ns
ACE Chip Enable Access Time — 45 — 55 — 70/90 ns

t
t

AOE Output Enable Access Time — 25 — 30 — 40/40 ns

t

OH Output Hold from Address Change 0 — 0 — 0/0 — ns

t

LZ Output Low-Z Time

t

HZ Output High-Z Time
PU Chip Enable to Power Up Time

t
t

PD Chip Disable to Power Down Time

NOTES:

1. Transition is measured ±500mV from Low or High-impedance voltage with Output Test Load (Figure 2).

2. 0°C to +70°C temperature range only.

3. This parameter is guaranteed by device characterization, but is not production tested.

4. "X" in part number indicates power rating (SA or LA).

(1, 3)

(1, 3)

(1, 3)

(1, 3)

(3)

(3)

(3)

(3)

3—0—0 —ns

—12—15— 20ns

0—0—0 —ns

—20—50— 50ns

IDT7133X45 IDT7133X55 IDT7133X70/90
IDT7143X45 IDT7143X55 IDT7143X70/90

0—5—5/5—ns

— 20 — 20 — 25/25 ns

0—0—0/0—ns

— 50 — 50 — 50/50 ns

(4)

(2)
(2)

IDT7133X25 IDT7133X35
IDT7143X25 IDT7143X35

2746 tbl 10

6.14 8

IDT7133SA/LA, IDT7143SA/LA
HIGH-SPEED 2K x 16 DUAL-PORT RAMS MILITARY AND COMMERCIAL TEMPERATURE RANGES

TIMING WAVEFORM OF READ CYCLE NO. 1, EITHER SIDE

t

RC

ADDRESS

t

AA

t

OH

DATA

OUT

BUSY

OUT

TIMING WAVEFORM OF READ CYCLE NO. 2, EITHER SIDE

t

ACE

CE

(4)

t

AOE

OE

(1)

t

LZ

DATA

CURRENT

OUT

I

CC

I

SB

t

PU

50%

(1)

t

LZ

(1, 2, 4, 5)

(1, 3, 5)

t

BDD

(3,4)

DATA VALIDPREVIOUS DATA VALID

VALID DATA

t

OH

2746 drw 07

(2)

t

HZ

(2)

t

HZ

(4)

t

PD

50%

2746 drw 08

NOTES:

1. Timing depends on which signal is asserted last, OE or CE.

2. Timing depends on which signal is deasserted last, OE or CE.

3. t

BDD delay is required only in a case where the opposite port is completing a write operation to the same address location. For simultaneous read operations,

BUSY

4. Start of valid data depends on which timing becomes effective last, t

5. R/W = V

has no relationship to valid output data.

IH and the address is valid prior to or coincident with

AOE, tACE, tAA, or tBDD.

CE

transition Low.

6.14 9

IDT7133SA/LA, IDT7143SA/LA
HIGH-SPEED 2K x 16 DUAL-PORT RAMS MILITARY AND COMMERCIAL TEMPERATURE RANGES

AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE

IDT7133X20
IDT7143X20

Symbol Parameter Min. Max. Min. Max. Min. Max. Unit
WRITE CYCLE

(5)

(4)

(6)

(1,3)

(1,3)

(1,3,5)

20 — 25 — 35 — ns

15 — 20 — 25 — ns

—12 — 15—20ns

0— 0 —0—ns

—12 — 15—20ns

0— 0 —0—ns

t

WC Write Cycle Time
EW Chip Enable to End-of-Write 15 — 20 — 25 — ns

t
t

AW Address Valid to End-of-Write 15 — 20 — 25 — ns

t

AS Address Set-up Time 0 — 0 — 0 — ns
WP Write Pulse Width

t

WR Write Recovery Time 0 — 0 — 0 — ns

t
t

DW Data Valid to End-of-Write 15 — 15 — 20 — ns

t

HZ Output High-Z Time
DH Data Hold Time

t
t

WZ Write Enable to Output in High-Z

t

OW Output Active from End-of-Write

(2)
(2)

(7)

IDT7133X25 IDT7133X35
IDT7143X25 IDT7143X35

AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE

IDT7133X45 IDT7133X55
IDT7143X45 IDT7143X55

Symbol Parameter Min. Max. Min. Max. Min. Max. Unit
WRITE CYCLE

t

WC Write Cycle Time
EW Chip Enable to End-of-Write 30 — 40 — 50/50 — ns

t
t

AW Address Valid to End-of-Write 30 — 40 — 50/50 — ns

t

AS Address Set-up Time 0 — 0 — 0/0 — ns
WP Write Pulse Width

t

WR Write Recovery Time 0 — 0 — 0/0 — ns

t
t

DW Data Valid to End-of-Write 20 — 25 — 30/30 — ns

t

HZ Output High-Z Time
DH Data Hold Time

t
t

WZ Write Enable to Output in High-Z

t

OW Output Active from End-of-Write

NOTES:

1. Transition is measured ± 500mV from Low or High-impedance voltage from the Output Test Load (Figure 2)..

2. 0° C to +70°C temperature range only.

3. This parameter is guaranteed by device characterization but is not production tested.

4. For MASTER/SLAVE combination, t

5. The specification for t
over voltage and temperature, the actual t

6. This parameter is determined by device characterization, but is not production tested. Transition is measured ±200mV from steady state with the Output
Test Load (Figure 2).

7. "X" in part number indicates power rating (SA or LA).

DH must be met by the device supplying write data to the RAM under all operation conditions. Although tDH and tOW values will very

(4)

(6)

(1,3)

(5)

(1,3)

(1,3,5)

WC = tBAA + tWR + tWP, since R

DH will always be smaller than the actual tOW.

45 — 55 — 70/90 — ns

30 — 40 — 50/50 — ns

— 20 — 20 — 25/25 ns

5 — 5 — 5/5 — ns

— 20 — 20 — 25/25 ns

5 — 5 — 5/5 — ns

W

= VIL must occur after tBAA.

(7)

IDT7133X70/90
IDT7143X70/90

2746 tbl 11

6.14 10

IDT7133SA/LA, IDT7143SA/LA
HIGH-SPEED 2K x 16 DUAL-PORT RAMS MILITARY AND COMMERCIAL TEMPERATURE RANGES

AC ELECTRICAL CHARACTERISTICS OVER THE

(1)
(1)

(7)

IDT7133X25 IDT7133X35
IDT7143X25 IDT7143X35

OPERATING TEMPERATURE AND SUPPLY VOLTAGE

IDT7133X20
IDT7143X20

Symbol Parameter Min. Max. Min. Max. Min. Max. Unit
BUSY TIMING (For MASTER IDT7133)

t

BAA
BDA

t
t

BAC

t

BDC
WDD Write Pulse to Data Delay

t

DDD Write Data Valid to Read Data Delay

t
t

BDD

t

APS Arbitration Priority Set Up Time

t

WH Write Hold After

BUSY INPUT TIMING (For SLAVE IDT7143)

t

WB
WH Write Hold After

t

WDD Write Pulse to Data Delay

t
t

DDD Write Data Valid to Read Data Delay

BUSY

Access Time from Address — 20 — 20 — 30 ns

BUSY

Disable Time from Address — 20 — 20 — 30 ns

BUSY

Access Time from Chip Enable — 20 — 20 — 25 ns

BUSY

Disable Time from Chip Enable — 17 — 20 — 25 ns

BUSY

Disable to Valid Data

BUSY

Input to Write

BUSY

(5)

BUSY

(2)

(2)

(3)

(4)

(6)

(6)

(2)

(2)

—40 — 50—60ns
—30 — 35—45ns

—25 — 30—35ns

5— 5 —5—ns

20 — 20 — 25 — ns

0— 0 —0—ns

20 — 20 — 25 — ns

—40 — 50—60ns
—30 — 35—45ns

2746 tbl 12

AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE

IDT7133X45 IDT7133X55 IDT7133X70/90
IDT7143X45 IDT7143X55 IDT7143X70/90

Symbol Parameter Min. Max. Min. Max. Min. Max. Unit
BUSY TIMING (For MASTER IDT7133)

t

BAA
BDA

t
t

BAC

t

BDC
WDD Write Pulse to Data Delay

t

DDD Write Data Valid to Read Data Delay

t
t

BDD

t

APS Arbitration Priority Set Up Time

t

WH Write Hold After

BUSY INPUT TIMING (For SLAVE IDT7143)

t

WB

tWH Write Hold After

WDD Write Pulse to Data Delay

t
t

DDD Write Data Valid to Read Data Delay

NOTES:

1. 0°C to +70°C temperature range only.

2. Port-to-port delay through RAM cells from writing port to reading port, refer to “Timing Waveform of Write with Port-to-Port Read and Busy".

3. t

BDD is calculated parameter and is greater of 0, tWDD - tWP (actual), or tDDD - tDW (actual).

4 To ensure that the earlier of the two ports wins.

5. To ensure that the write cycle is inhibited on port "B" during contention on port "A".

6. To ensure that a write cycle is completed on port "B" after contention on port "A".

7. "X" in part number indicates power rating (SA or LA).

BUSY

Access Time from Address — 40 — 40 — 45/45 ns

BUSY

Disable Time from Address — 40 — 40 — 45/45 ns

BUSY

Access Time from Chip Enable — 30 — 35 — 35/35 ns

BUSY

Disable Time from Chip Enable — 25 — 30 — 30/30 ns

BUSY

Disable to Valid Data

BUSY

Input to Write

BUSY

(5)

BUSY

(2)

(2)

(3)

(4)

(6)

(6)

(2)

(2)

— 80 — 80 — 90/90 ns
— 55 — 55 — 70/70 ns

— 40 — 40 — 40/40 ns

5 — 5 — 5/5 — ns

30 — 30 — 30/30 — ns

0

30 — 30 — 30/30 — ns

— 80 — 80 — 90/90 ns
— 55 — 55 — 70/70 ns

(7)

— 0 — 0/0 — ns

2746 tbl 12

6.14 11

IDT7133SA/LA, IDT7143SA/LA
HIGH-SPEED 2K x 16 DUAL-PORT RAMS MILITARY AND COMMERCIAL TEMPERATURE RANGES

TIMING WAVEFORM OF WRITE CYCLE NO. 1 (R/

t

WC

ADDRESS

(6)

t

AS

t

AW

t

WP

(7)

t

t

LZ

WZ

(4)

R/

DATA

DATA

OE

CE

W

OUT

(9)

IN

WW

W

CONTROLLED TIMING)

WW

t

WR

(2)

t

OW

t

DW

(1, 5, 8)

(3)

(7)

t

HZ

(7)

t

HZ

(4)

t

DH

2746 drw 09

t

(1, 5)

WC

WRITE CYCLE NO. 2 (

CECE

CE

CONTROLLED TIMING)

CECE

ADDRESS

t

AW

CE

(6)

t

AS

(9)

R/

W

DATA

IN

NOTES:

1. R/W or CE must be High during all address transitions.

2. A write occurs during the overlap (t

3. t

WR is measured from the earlier of

4. During this period, the I/O pins are in the output state, and input signals must not be applied.

5. If the CE low transition occurs simultaneously with or after the R/W low transition, the outputs remain in the High-impedance state.

6. Timing depends on which enable signal (CE or R/W) is asserted last.

7. This parameter is determined by device characterization, but is not production tested. Transition is measured
Test Load (Figure 2).

8. If OE is low during a R/W controlled write cycle, the write pulse width must be the larger of t
to be placed on the bus for the required t
be as short as the specified t

9. R/W for either upper or lower byte.

EW or tWP) of a

WP.

CE

CE

or R/W going High to the end of the write cycle.

DW. If

= VIL and a R/W = VIL.

OE

is High during an R/W controlled write cycle, this requirement does not apply and the write pulse can

(2)

t

EW

t

DW

WP or (tWZ + tDW) to allow the I/O drivers to turn off and data

t

WR

t

DH

+ 200mV from steady state with the Output

2746 drw 10

6.14 12

IDT7133SA/LA, IDT7143SA/LA
HIGH-SPEED 2K x 16 DUAL-PORT RAMS MILITARY AND COMMERCIAL TEMPERATURE RANGES

DDD

(4)

(1, 2, 3)

t

BDA

t

DH

2746 drw 11

TIMING WAVEFORM OF WRITE WITH PORT-TO-PORT READ AND

t

WC

ADDR

DATA

ADDR

BUSY

DATA

R/

W

IN "A"

OUT "B"

"A"

"A"

"B"

"B"

t

APS

(1)

MATCH

t

WP

t

DW

MATCH

t

WDD

VALID

BUSYBUSY

BUSY

BUSYBUSY

t

NOTES:

1. To ensure that the earlier of the two ports wins, t

2.

CE

L = CER = VIL

3.OE = VIL for the reading port.

4. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A".

APS is ignored for Slave (IDT7143).

t

BDD

VALID

TIMING WAVEFORM OF WRITE WITH

R/

W

"A"

BUSY

"B"

R/

W

"B"

NOTES:

1. t

WH must be met for both

2.

BUSY

3. All timing is the same for left and right ports. Port "

is asserted on port "B" blocking R/W

BUSY

input (SLAVE) and output (MASTER).

"B", until

BUSY

A" may be either left or right port. Port "B" is the opposite from port "A".

BUSYBUSY

BUSY

BUSYBUSY

(M/

tWB

"B" goes High.

SS

S

= VIL)

SS

tWP

(2)

(1)

tWH

2746 drw 12

6.14 13

IDT7133SA/LA, IDT7143SA/LA
HIGH-SPEED 2K x 16 DUAL-PORT RAMS MILITARY AND COMMERCIAL TEMPERATURE RANGES

TIMING WAVEFORM OF BUSY ARBITRATION CONTROLLED BY

ADDR

"A" AND "B"

CE

"A"

CE

"B"

BUSY

"B"

t

APS

ADDRESSES MATCH

t

BAC

t

BDC

CECE

CE

TIMING

CECE

(1)

TIMING WAVEFORM OF BUSY ARBITRATION CONTROLLED BY ADDRESSES

t

ADDR

ADDR

"A"

"B"

RC

ADDRESSES MATCH

t

APS

t

BAA

OR

t

WC

ADDRESSES DO NOT MATCH

t

BDA

2746 drw 13

(1)

BUSY

"B"

NOTES:

1. All timing is the same for left and right ports. Port "

2. If t

APS is not satisfied, the

(IDT7133 only).

BUSY

will be asserted on one side or the other, but there is no guarantee on which side

A" may be either the left or right port. Port "B" is the port opposite from port "A".

BUSY

will be asserted

2746 drw 14

6.14 14

IDT7133SA/LA, IDT7143SA/LA

+5V

R/

W

L

BUSY

L

R/

W

IDT7133

MASTER

+5V

R/

W

R

BUSY

R

R/

W

BUSY

R/

W

L

BUSY

L

IDT7142

SLAVE

R/

W

R

BUSY

R

(1)

LEFT

RIGHT

2746 drw 15

IDT7143

SLAVE

270Ω

270Ω

HIGH-SPEED 2K x 16 DUAL-PORT RAMS MILITARY AND COMMERCIAL TEMPERATURE RANGES

FUNCTIONAL DESCRIPTION:

The IDT7133/43 provides two ports with separate control,
address and I/O pins that permit independent access for reads
or writes to any location in memory. The IDT7133/43 has an
automatic power down feature controlled by CE. The

CE

controls on-chip power down circuitry that permits the
respective port to go into a standby mode when not selected
(CE High). When a port is enabled, access to the entire
memory array is permitted. Non-contention READ/WRITE
conditions are illustrated in Truth Table I.

BUSY LOGIC

Busy Logic provides a hardware indication that both ports of
the RAM have accessed the same location at the same time.
It also allows one of the two accesses to proceed and signals
the other side that the RAM is “Busy”. The busy pin can then
be used to stall the access until the operation on the other side
is completed. If a write operation has been attempted from the
side that receives a busy indication, the write signal is gated
internally to prevent the write from proceeding.

The use of busy logic is not required or desirable for all
applications. In some cases it may be useful to logically OR
the busy outputs together and use any busy indication as an
interrupt source to flag the event of an illegal or illogical
operation. If the write inhibit function of busy logic is not
desirable, the busy logic can be disabled by using the IDT7143
(SLAVE). In the IDT7143, the busy pin operates solely as a
write inhibit input pin. Normal operation can be programmed
by tying the

BUSY

pins high. If desired, unintended write
operations can be prevented to a port by tying the busy pin for
that port low. The busy outputs on the IDT 7133 RAM are open
drain and require pull-up resistors.

WIDTH EXPANSION WITH BUSY LOGIC MAS­TER/SLAVE ARRAYS

When expanding an IDT7133/43 RAM array in width while
using busy logic, one master part is used to decide which side
of the RAM array will receive a busy indication, and to output
that indication. Any number of slaves to be addressed in the
same address range as the master, use the busy signal as a
write inhibit signal. Thus on the IDT7133 RAM the busy pin is
an output and on the IDT7143 RAM, the busy pin is an input
(see Figure 4).

Figure 4. Busy and chip enable routing for both width and depth
expansion with the IDT7133 (MASTER) and the IDT7143 (SLAVE).

Expanding the data bus width to 32 bits or more in a Dual­Port RAM system implies that several chips will be active at
the same time. If each chip includes a hardware arbitrator,
and the addresses for each chip arrive at the same time, it is
possible that one will activate its
activates its

BUSY

R signal. Both sides are now busy and the

BUSY

L while another

CPUs will await indefinitely for their port to become free.

To avoid the “Busy Lock-Out” problem, IDT has developed
a MASTER/SLAVE approach where only one hardware
arbitrator, in the MASTER, is used. The SLAVE has

BUSY

inputs which allow an interface to the MASTER with no
external components and with a speed advantage over other
systems.

When expanding Dual-Port RAMs in width, the writing of the
SLAVE RAMs must be delayed until after the

BUSY

input has
settled. Otherwise, the SLAVE chip may begin a write cycle
during a contention situation. Conversely, the write pulse
must extend a hold time past

BUSY

to ensure that a write cycle
takes place after the contention is resolved. This timing is
inherent in all Dual-Port memory systems where more than
one chip is active at the same time.

The write pulse to the SLAVE should be delayed by the
maximum arbitration time of the MASTER. If, then, a conten­tion occurs, the write to the SLAVE will be inhibited due to

BUSY

from the MASTER.

6.14 15

IDT7133SA/LA, IDT7143SA/LA
HIGH-SPEED 2K x 16 DUAL-PORT RAMS MILITARY AND COMMERCIAL TEMPERATURE RANGES

TRUTH TABLE I — NON-CONTENTION READ/WRITE CONTROL

LEFT OR RIGHT PORT

R/

WW

W

LB R/

WW

WW

W

WW

UB

CECE

CE

CECE

OEOE

OE

OEOE

X X H X Z Z Port Disabled and in Power Down Mode, I
XXHXZ Z
L L L X DATAIN DATAIN Data on Lower Byte and Upper Byte Written into Memory
L H L L DATAIN DATAOUT Data on Lower Byte Written into Memory

H L L L DATAOUT DATAIN Data in Memory Output on Lower Byte

L H L H DATAIN Z Data on Lower Byte Written into Memory

H L L H Z DATAIN Data on Upper Byte Written into Memory

(1)

0-7 I/O8-15 Function

I/O

CE

R = CEL = VIH, Power Down Mode, ISB1 or ISB3

Upper Byte

into Memory

(3)

(2)

(4)

SB2, ISB4

(2)

(2)

, Data in Memory Output on

(3)

, Data on Upper Byte Written

(2)
(2)

H H L L DATAOUT DATAOUT Data in Memory Output on Lower Byte and Upper Byte
H H L H Z Z High Impedance Outputs

NOTES: 2746 tbl 13

1. A0L - A10L ≠ A0R - A10R.

2. If

BUSY

3. If

4. "H" = V

= VIL, data is not written.

BUSY

= V

IL, data may not be valid, see tWDD and tDDD timing.

IH, "L" = VIL, "X" = Don’t Care, "Z" = High-Impedance, "LB" = Lower Byte, "UB" = Upper Byte.

TRUTH TABLE II —
ADDRESS BUSY ARBITRATION

Inputs Outputs

A

0L-A10L

CECE

CECE

L

CE

CECE

XX

HX

XH
LL

NOTES: 2746 tbl 14

1. Pins
Both are inputs on the IDT7143 (SLAVE). On Slaves the
internally inhibits writes.

2. "L" if the inputs to the opposite port were stable prior to the address and
enable inputs of this port. "H" if the inputs to the opposite port became
stable after the address and enable inputs of this port. If t
either
not be LOW simultaneously.

3. Writes to the left port are internally ignored when
driving LOW regardless of actual logic level on the pin. Writes to the right
port are internally ignored when
less of actual logic level on the pin.

R A0R-A10R

CE

CECE

BUSY

L and

BUSY

L or

NO MATCH H H Normal

MATCH H H Normal
MATCH H H Normal
MATCH (2) (2) Write Inhibit

BUSY

R are both outputs on the IDT7133 (MASTER).

BUSY

R = LOW will result.

BUSYBUSY

BUSY

BUSYBUSY

BUSY

(1)

L

R outputs are driving LOW regard-

BUSYBUSY

BUSY

BUSYBUSY

BUSY

(1)

R

L and

Function

APS is not met,

BUSY

R outputs can

BUSY

L outputs are

BUSY

(3)

input

6.14 16

IDT7133SA/LA, IDT7143SA/LA
HIGH-SPEED 2K x 16 DUAL-PORT RAMS MILITARY AND COMMERCIAL TEMPERATURE RANGES

ORDERING INFORMATION

IDT

XXXX

Device

Type

A

Power

999

SpeedAPackage

A

Process/

Temperature

Range

Blank
B

J
G
F
PF

20
25
35
45
55
70
90

LA
SA

7133
7143

Commercial (0°C to +70°C)
Military (–55°C to +125°C)

Compliant to MIL-STD-883, Class B

68-pin PLCC (J68-1)
68-pin PGA (G68-1)
68-pin Flatplack (F68-1)
100-pin TQFP (PN100-1)

Commercial Only

Speed in nanoseconds

Low Power
Standard Power

32K (2K x 16-Bit) MASTER Dual-Port RAM
32K (2K x 16-Bit) SLAVE Dual-Port RAM

2746 drw 16

6.14 17