Datasheet IDT7132LA35FB, IDT7132LA35J, IDT7132LA35JB, IDT7132LA35L48B, IDT7132LA35P Datasheet (Integrated Device Technology Inc)

Integrated Device Technology, Inc.

I/O

Control

Address
Decoder

MEMORY

ARRAY

ARBITRATION

LOGIC

Address
Decoder

I/O

Control

R/

W

L

CE

L

OE

L

BUSY

L

A

10L

A

0L

2692 drw 01

I/O0L- I/O

7L

CE

L

BUSY

R

I/O0R-I/O

7R

A

10R

A

0R

CE

R

(1,2) (1,2)

R/

W

R

CE

R

OE

R

11

11

HIGH-SPEED
2K x 8 DUAL-PORT
STATIC RAM

IDT7132SA/LA
IDT7142SA/LA

FEATURES:

• High-speed access
— Military: 25/35/55/100ns (max.)
— Commercial: 25/35/55/100ns (max.)
— Commercial: 20ns only in PLCC for 7132

• Low-power operation
— IDT7132/42SA

Active: 550mW (typ.)
Standby: 5mW (typ.)

— IDT7132/42LA

Active: 550mW (typ.)
Standby: 1mW (typ.)

• Fully asynchronous operation from either port

• MASTER IDT7132 easily expands data bus width to 16-or-

more bits using SLAVE IDT7142

• On-chip port arbitration logic (IDT7132 only)

•

BUSY

output flag on IDT7132;

• Battery backup operation —2V data retention

• TTL-compatible, single 5V ±10% power supply

• Available in popular hermetic and plastic packages

• Military product compliant to MIL-STD, Class B

• Standard Military Drawing # 5962-87002

• Industrial temperature range (–40°C to +85°C) is available,

tested to miliary electrical specifications

BUSY

input on IDT7142

DESCRIPTION:

The IDT7132/IDT7142 are high-speed 2K x 8 Dual-Port
Static RAMs. The IDT7132 is designed to be used as a stand­alone 8-bit Dual-Port RAM or as a “MASTER” Dual-Port RAM
together with the IDT7142 “SLAVE” Dual-Port in 16-bit-or­more word width systems. Using the IDT MASTER/SLAVE
Dual-Port RAM approach in 16-or-more-bit memory system
applications results in full-speed, error-free operation without
the need for additional discrete logic.

Both devices provide two independent ports with separate
control, address, and l/O pins that permit independent, asyn­chronous access for reads or writes to any location in memory.
An automatic power down feature, controlled by CE permits
the on-chip circuitry of each port to enter a very low standby
power mode.

Fabricated using IDT’s CMOS high-performance technol­ogy, these devices typically operate on only 550mW of power.
Low-power (LA) versions offer battery backup data retention
capability, with each Dual-Port typically consuming 200µW
from a 2V battery.

The IDT7132/7142 devices are packaged in a 48-pin
sidebraze or plastic DIPs, 48-pin LCCs, 52-pin PLCCs, and
48-lead flatpacks. Military grade product is manufactured in
compliance with the latest revision of MIL-STD-883, Class B,
making it ideally suited to military temperature applications
demanding the highest level of performance and reliability.

FUNCTIONAL BLOCK DIAGRAM

NOTES:

1. IDT7132 (MASTER):
drain output and requires pullup
resistor of 270Ω.
IDT7142 (SLAVE):

2. Open drain output: requires pullup
resistor of 270Ω.

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES OCTOBER 1996

©1996 Integrated Device Technology, Inc. DSC-2692/8

BUSY

BUSY

is open

is input.

For latest information contact IDT’s web site at www.idt.com or fax-on-demand at 408-492-8391.

6.02 1

IDT7132SA/LA AND IDT7142SA/LA

IDT7132/42

L48-1

&

F48-1

48-PIN LCC/ FLATPACK

TOP VIEW

(3)

INDEX

65432148 47 46 45 44 43

19 20 21 22 23 25 26 27 28 29 3024

42
41
40
39
38
37
36
35
34
33
32
31

7
8
9
10
11
12
13
14
15
16
17
18

2692 drw 03

GND

CE

R

CE

L

OE

L

A

0L

OE

R

A

0R

A

1R

A

2R

A

3R

A

4R

A

5R

A

6R

A

7R

A

8R

A

9R

I/O

7R

I/O

3L

A

1L

A

2L

A

3L

A

4L

A

5L

A

6L

A

7L

A

8L

A

9L

I/O

0L

I/O

1L

I/O

2L

BUSY

L

R/

W

L

R/

W

R

BUSY

R

V

CC

I/O

6R

I/O

5R

I/O

4R

I/O

3R

I/O

2R

I/O

1R

I/O

0R

I/O

7L

I/O

6L

I/O

5L

I/O

4L

A

10L

A

10R

IDT7132/42

J52-1

52-PIN PLCC

TOP VIEW

(3)

INDEX

N/C

GND

OE

R

A

0R

A

1R

A

2R

A

3R

A

4R

A

5R

A

6R

A

7R

A

8R

A

9R

N/C
I/O

7R

46
45
44
43
42
41
40
39
38
37
36
35
34

I/O

3L

A

1L

A

2L

A

3L

A

4L

A

5L

A

6L

A

7L

A

8L

A

9L

I/O

0L

I/O

1L

I/O

2L

8
9
10
11
12
13
14
15
16
17
18
19
20

474849505152

1

234567

33323130292827262524232221

2692 drw 04

A

10L

V

CC

A

10R

I/O

6R

A

0L

OE

L

N/C

CE

L

CE

R

N/C

BUSY

L

R/

W

L

R/

W

R

BUSY

R

I/O

5R

I/O

4R

I/O

3R

I/O

2R

I/O

1R

I/O

0R

I/O

7L

I/O

6L

I/O

5L

I/O

4L

HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN CONFIGURATIONS

CE

L

R/

BUSY

A

OE

I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND

NOTES:

1. All Vcc pins must be connected to the power supply.

2. All GND pins must be connected to the ground supply.

3. This text does not indicate orientation of the actual part-marking.

148

W

L

2

L

3

10L

4

L

5

A

0L

6

A

1L

7

A

2L

8

A

3L

9

A

4L

10

A

5L

11

A

6L

12

A

7L

13

A

8L

14

A

9L

15

0L

16

1L

17

2L

18

3L

19

4L

20

5L

21

6L

22

7L

23
24

(1,2)

IDT7132/

7142

P48-1

&

C48-2

DIP

TOP

(3)

VIEW

47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

V

CC

CE

R

R/

W

R

BUSY

R

A

10R

OE

R

A

0R

A

1R

A

2R

A

3R

A

4R

A

5R

A

6R

A

7R

A

8R

A

9R

I/O

7R

I/O

6R

I/O

5R

I/O

4R

I/O

3R

I/O

2R

I/O

1R

I/O

0R

2692 drw 02

ABSOLUTE MAXIMUM RATINGS

(1)

Symbol Rating Commercial Military Unit

(2)

TERM

V

Terminal Voltage -0.5 to +7.0 -0.5 to +7.0 V
with Respect to
GND

T

A Operating 0 to +70 -55 to +125 °C

Temperature

T

BIAS Temperature -55 to +125 -65 to +135 °C

Under Bias

T

STG Storage -55 to +125 -65 to +150 °C

Temperature

I

OUT DC Output 50 50 mA

Current

NOTES:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS

2. V

RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE

may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of the specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.

TERM must not exceed Vcc + 0.5V for more than 25% of the cycle time or

10ns maximum, and is limited to

0.5V.

Grade Temperature GND V

Military -55°C to +125°C 0V 5.0V ± 10%
Commercial 0°C to +70°C 0V 5.0V ± 10%

Ambient

< 20mA for the period of VTERM > Vcc +

CC

2692 tbl 01

NOTES:

1. All Vcc pins must be connected to the power supply.

2. All GND pins must be connected to the ground supply.

3. This text does not indicate orientation of the actual part-marking.

RECOMMENDED
DC OPERATING CONDITIONS

Symbol Parameter Min. Typ. Max. Unit

V

CC Supply Voltage 4.5 5.0 5.5 V

GND Supply Voltage 0 0 0 V

V

IH Input High Voltage 2.2 — 6.0

V

IL Input Low Voltage -0.5 — 0.8 V

NOTES:

1. V

IL (min.) = -1.5V for pulse width less than 10ns.
TERM must not exceed Vcc + 0.5V.

2692 tbl 02

2. V

6.02 2

(1)

(2)

V

2692 tbl 03

IDT7132SA/LA AND IDT7142SA/LA
HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES

DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE

7132X20

(2)

7132X25
7142X25

(1,6)

(VCC = 5.0V ± 10%)

(3)

7132X35 7132X55 7132X100

(3)

7142X35 7142X55 7142X100

Symbol Parameter Test Conditions Version Typ. Max. Typ. Max. Typ. Max. Typ. Max. Typ. Max. Unit

I

CC Dynamic Operating

CE

L and CER = VIL, MIL. SA — — 110 280 80 230 65 190 65 190 mA

Current (Both Ports Outputs open, LA — — 110 220 80 170 65 140 65 140
Active) f = f

MAX

(4)

COM'L. SA 110 250 110 220 80 165 65 155 65 155

LA 110 200 110 170 80 120 65 110 65 110

SB1 Standby Current

I

(Both Ports - TTL f = f

CE

L and CER = VIH, MIL. SA — — 30 80 25 80 20 65 20 65 mA

(4)

MAX

LA — — 30 60 25 60 20 45 20 45

Level Inputs) COM'L. SA 30 65 30 65 25 65 20 65 20 55

LA 30 45 30 45 25 45 20 35 20 35

I

SB2 Standby Current

(One Port - TTL

CE

"A" = VIL and MIL. SA — — 65 160 50 150 40 125 40 125 mA

CE

"B" = VIH

(7)

LA — — 65 125 50 115 40 90 40 90

Level Inputs) Active Port Outputs COM'L. SA 65 165 65 150 50 125 40 110 40 110

MAX

(4)

(5)

(7)

LA 65 125 65 115 50 90 40 75 40 75

LA 0.2 5 0.2 5 0.2 4 0.2 4 0.2 4

LA — — 60 115 45 105 40 85 40 80

SB3 Full Standby Current

I

(Both Ports - All
CMOS Level Inputs V

I

SB4 Full Standby Current

(One Port - All
CMOS Level Inputs) V

Open, f = f

CE

L and MIL. SA — — 1.0 30 1.0 30 1.0 30 1.0 30 mA

CE

R > VCC -0.2V, LA — — 0.2 10 0.2 10 0.2 10 0.2 10

IN > VCC -0.2V or COM'L. SA 1.0 15 1.0 15 1.0 15 1.0 15 1.0 15

V

IN < 0.2V,f = 0

CE

"A" < 0.2V and MIL. SA — — 60 155 45 145 40 110 40 110 mA

CE

"B" > VCC -0.2V

IN > VCC -0.2V or COM'L. SA 60 155 60 145 45 110 40 100 40 95

V

IN < 0.2V, LA 60 115 60 105 45 85 40 70 40 70

Active Port Outputs
Open, f = f

NOTES: 2689 tbl 04

1. 'X' in part numbers indicates power rating (SA or LA).

2. Com'l Only, 0°C to +70°C temperature range. PLCC package only.

3. Not available in DIP packages.

4. At f = f

5. f = 0 means no address or control lines change. Applies only to inputs at CMOS level standby.

6. Vcc = 5V, T

7. Port "A" may be either left or right port. Port "B" is opposite from port "A".

Max, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, and using “AC TEST CONDITIONS”

of input levels of GND to 3V.

A=+25°C for Typ. and is not production tested. Vcc DC = 100mA (Typ.)

MAX

(4)

DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE (VCC = 5.0V ± 10%)

7132SA 7132LA
7142SA 7142LA

Symbol Parameter Test Conditions Min. Max. Max. Max. Unit

Ll| Input Leakage VCC = 5.5V, — 10 — 5 µA

|l

|lLO| Output Leakage VCC = 5.5V, — 10 — 5 µA

V

OL Output Low Voltage lOL = 4mA — 0.4 — 0.4 V

V

OL Open Drain Output lOL = 16mA — 0.5 — 0.5 V

V

OH Output High Voltage lOH = -4mA 2.4 — 2.4 — V

NOTE: 2689 tbl 05

1. At Vcc < 2.0V leakages are undefined.

(1)

Current

(1)

Current

(l/O0-l/O

Low Voltage (

7) lOL= 16mA

BUSY, INT

)

Supply Current V

VIN = 0V to VCCIN = GND to VCC

CE

= VIH, VOUT = 0V to VCC

IN > VCC -0.2V or < 0.2V

C

6.02 3

IDT7132SA/LA AND IDT7142SA/LA
HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES

DATA RETENTION CHARACTERISTICS (LA Version Only)

Symbol Parameter Test Conditions Min. Typ. Max. Unit

V

DR VCC for Data Retention 2.0 — — V

I

CCDR Data Retention Current VCC = 2.0V,

IN ≥ VCC -0.2V or VIN ≤ 0.2V Com’l. — 100 1500 µA

V

(3)

t

CDR Chip Deselect to Data 0 — — ns

CE

≥ VCC -0.2V Mil. — 100 4000 µA

Retention Time

(3)

t

R Operation Recovery tRC ——ns

Time

NOTES:

CC = 2V, TA = +25°C, and is not production tested.

1. V

RC = Read Cycle Time

2. t

3. This parameter is guaranteed but not production tested.

lDT7132LA/IDT7142LA

(2)

2692 tbl 06

DATA RETENTION WAVEFORM

DATA RETENTION MODE

V

CC

CE

4.5V 4.5V
t

CDR

V

IH

DATA

V

DR

V

OUT

775Ω

≥

DR

2.0V
t

R

V

IH

2692 drw 05

5V

1250Ω

30pF*

100pF for 55 and 100ns versions

AC TEST CONDITIONS

Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load

DATA

OUT

775Ω

GND TO 3.0V

5ns

1.5V

1.5V

Figures 1, 2, and 3

2692 tbl 07

5V

1250Ω

5pF*

BUSY

Figure 1. AC Output Test Load

5V

270Ω

or

INT

30pF*

100pF for 55 and 100ns versions

Figure 3.

AC Output Test Load

BUSYBUSY

BUSY

BUSYBUSY

and

INTINT

INT

INTINT

2692 drw 06

Figure 2. Output Test Load

HZ, tLZ, tWZ, and tOW)

(for t

* Including scope and jig

6.02 4

IDT7132SA/LA AND IDT7142SA/LA
HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES

AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE

7132X20

Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit

Read Cycle

t

RC Read Cycle Time 20 — 25 — 35 — 55 — 100 — ns

t

AA Address Access Time — 20 — 25 — 35 — 55 — 100 ns

t

ACE Chip Enable Access Time — 20 — 25 — 35 — 55 — 100 ns

t

AOE Output Enable Access Time 11 — 12 — 20 — 25 — 40 ns

t

OH Output Hold From Address Change 3 — 3 — 3 — 3 — 10 — ns
LZ Output Low-Z Time

t
t

HZ Output High-Z Time

t

PU Chip Enable to Power Up Time

t

PD Chip Disable to Power Down Time

NOTES: 2689 tbl 08

1. Transition is measured ±500mV from Low or High-impedance voltage Output Test Load (Figure 2).

2. Com'l Only, 0°C to +70°C temperature range. PLCC package only.

3. “X” in part numbers indicates power rating (SA or LA).

4. This parameter is guaranteed by device characterization, but is not production tested.

5. Not available in DIP packages.

(1,4)

(1,4)

(4)

(4)

(2)

7132X25
7142X25

0— 0 — 0 — 5 — 5 —ns

— 10 — 10 — 15 — 25 — 40 ns

0— 0—0 — 0 —0 —ns

— 20 — 25 — 35 — 50 — 50 ns

(3)

(5)

7132X35 7132X55 7132X100

(5)

7142X35 7142X55 7142X100

TIMING WAVEFORM OF READ CYCLE NO. 1, EITHER SIDE

t

RC

(1)

ADDRESS

t

t

AA

t

OH

OUT

DATA

BUSY

OUT

NOTES:

1. R/W = V

BDD delay is required only in the case where the opposite port is completing a write operation to the same address location. For simultaneous read

2. t
operations,

3. Start of valid data depends on which timing becomes effective last t

PREVIOUS DATA VALID

t

BDDH

IH,

CE

= VIL, and is OE = VIL. Address is valid prior to the coincidental with CE transition Low.

BUSY

has no relationship to valid output data.

AOE, tACE, tAA, and tBDD.

DATA VALID

(2,3)

OH

2692 drw 07

6.02 5

IDT7132SA/LA AND IDT7142SA/LA
HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES

TIMING WAVEFORM OF READ CYCLE NO. 2, EITHER SIDE

t

ACE

(3)

CE

t

AOE

(4)

(2)

t

HZ

OE

(4)

t

HZ

(2)

50%

2692 drw 08

t

LZ

DATA

OUT

(1)

t

LZ

t

I

CC

CURRENT

I

SS

NOTES:

1. Timing depends on which signal is asserted last, OE or CE.

2. Timing depends on which signal is deaserted first, OE or CE.

3. R/W = V

4. Start of valid data depends on which timing becomes effective last t

IH, and the address is valid prior to or coincidental with

PU

50%

CE

(1)

transition Low.

AOE, tACE, tAA, and tBDD.

VALID DATA

t

PD

AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE

7132X20

(2)

7132X25
7142X25

Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit

Write Cycle

t

WC Write Cycle Time

t

EW Chip Enable to End of Write 15 — 20 — 30 — 40 — 90 — ns

t

AW Address Valid to End of Write 15 — 20 — 30 — 40 — 90 — ns

t

AS Address Set-up Time 0 — 0 — 0 — 0 — 0 — ns

t

WP Write Pulse Width

t

WR Write Recovery Time 0 — 0 — 0 — 0 — 0 — ns

t

DW Data Valid to End of Write 10 — 12 — 15 — 20 — 40 — ns

t

HZ Output High Z Time

t

DH Data Hold Time 0 — 0 — 0 — 0 — 0 — ns

t

WZ Write Enabled to Output in High Z

t

OW Output Active From End of Write

NOTES: 2692 tbl 09

1. Transition is measured ±500mV from Low or High-impedance voltage with Output Test Load (Figure 2). This parameter is guaranteed by
device characterization but is not production tested.

2. 0°C to +70°C temperature range only, PLCC package only.

3. For Master/Slave combination, t

4. If OE is low during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off
data to be placed on the bus for the required t
write pulse can be as short as the specified t

5. “X” in part numbers indicates power rating (SA or LA).

6. Not available in DIP packages.

CAPACITANCE

(1)

Symbol Parameter Conditions

C

IN Input Capacitance VIN = 3dV 11 pF

C

OUT Output Capacitance VIN = 3dV 11 pF

NOTES:

1. This parameter is determined by device characterization but is not
production tested.

2. 3dV represents the interpolated capacitance when the input and output

signals switch from 0V to 3V or from 3V to 0V.

(3)

(4)

(1)

(1)

(1)

WC = tBAA + tWP, since R/

DW. If

OE

WP.

(TA = +25°C,f = 1.0MHz)

20 — 25 — 35 — 55 — 100 — ns

15 — 15 — 25 — 30 — 55 — ns

— 10 — 10 — 15 — 25 — 40 ns

— 10 — 10 — 15 — 30 — 40 ns

0— 0— 0— 0— 0— ns

W

= VIL must occur after tBAA.

is High during a R/W controlled write cycle, this requirement does not apply and the

(2)

Max. Unit

2692 tbl 10

(6)
(6)

(5)

7132X35 7132X55 7132X100
7142X35 7142X55 7142X100

6.02 6

IDT7132SA/LA AND IDT7142SA/LA
HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES

TIMING WAVEFORM OF WRITE CYCLE NO. 1, (R/

t

WC

ADDRESS

OE

t

AW

CE

t

WP

(2)

DATA

DATA

R/

OUT

W

IN

(6)

t

AS

(7)

t

WZ

(4) (4)

TIMING WAVEFORM OF WRITE CYCLE NO. 2, (

t

WC

WW

W

CONTROLLED TIMING)

WW

(3)

t

WR

t

DW

CECE

CE

CONTROLLED TIMING)

CECE

t

DH

t

OW

(1,5,8)

(1,5)

(7)

t

HZ

(7)

t

HZ

2692 drw 09

ADDRESS

t

AW

CE

(6)

t

AS

R/

W

DATA

IN

NOTES:

1. R/W or CE must be High during all address transitions.

2. A write occurs during the overlap (t

3. tWR is measured from the earlier of CE or R/W going High to the end of the write cycle.

4. During this period, the l/O pins are in the output state and input signals must not be applied.

5. If the CE Low transition occurs simultaneously with or after the R/W Low transition, the outputs remain in the High-impedance state.

6. Timing depends on which enable signal (CE or R/W) is asserted last.

7. This parameter is determined be device characterization, but is not production tested. Transition is measured +/- 500mV from steady state
with the Output Test Load (Figure 2).

8. If OE is low during a R/W controlled write cycle, the write pulse width must be the larger of t
data to be placed on the bus for the required t
write pulse can be as short as the specified t

EW or tWP) of

WP.

CE

= VIL and R/W= VIL.

DW. If

OE

is High during a R/W controlled write cycle, this requirement does not apply and the

(2) (3)

t

EW

t

DW

WP or (tWZ + tDW) to allow the I/O drivers to turn off

t

WR

t

DH

2692 drw 10

6.02 7

IDT7132SA/LA AND IDT7142SA/LA
HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES

AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE

(1)

7132X20

7132X25

7142X25
Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
Busy Timing (For Master lDT7130 Only)

BAA

t

BDA

t

BAC

t

BDC

t

WDD Write Pulse to Data Delay

t

WH Write Hold After

t

DDD Write Data Valid to Read Data Delay

t

APS Arbitration Priority Set-up Time

t

BDD

t

BUSY

Access Time from Address — 20 — 20 — 20 — 30 — 50 ns

BUSY

Disable Time from Address — 20 — 20 — 20 — 30 — 50 ns

BUSY

Access Time from Chip Enable — 20 — 20 — 20 — 30 — 50 ns

BUSY

Disable Time from Chip Enable — 20 — 20 — 20 — 30 — 50 ns

BUSY

BUSY

Disable to Valid Data

(2)

(6)

(2)

(3)

(4)

— 50 — 50 — 60 — 80 — 120 ns
12 — 15 — 20 — 20 — 20 — ns
— 35 — 35 — 35 — 55 — 100 ns

5— 5— 5 — 5—5 — ns

— 25 — 35 — 35 — 50 — 65 ns

Busy Timing (For Slave IDT7140 Only)e5—5—5—5—5

WB Write to

t

WH Write Hold After

t

WDD Write Pulse to Data Delay

t

DDD Write Data Valid to Read Data Delay

t

NOTES: 2689 tbl 11

1. Com'l Only, 0°C to +70°C temperature range. PLCC package only.

2. Port-to-port delay through RAM cells from the writing port to the reading port, refer to “Timing Waveform of Write with Port -to-Port Read and

3. To ensure that the earlier of the two ports wins.

4. t

BDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual), or tDDD – tDW (actual).

5. To ensure that a write cycle is inhibited on port 'B' during contention on port 'A'..

6. To ensure that a write cycle is completed on port 'B' after contention on port 'A'.

7. “X” in part numbers indicates power rating (S or L).

8. Not available in DIP package

BUSY

Input

BUSY

(5)

(6)

(2)

(2)

0— 0— 0 — 0—0 — ns
12 — 15 — 20 — 20 — 20 — ns
— 40 — 50 — 60 — 80 — 120 ns
— 30 — 35 — 35 — 55 — 100 ns

TIMING WAVEFORM OF WRITE WITH PORT-TO-PORT READ AND

(7)8

(8)
(8)

M824S258M824S30 7132158M824S4

7132X35 7132X55 7132X100
7142X35 7142X55 7142X100

(1,2,3)

BUSYBUSY

BUSY

BUSYBUSY

BUSY

."

t

WC

ADDR

’A’

R/

W

’A’

DATA

IN’A’

(1)

t

APS

ADDR

’B’

BUSY

’B’

DATA

OUT’B’

NOTES:

1. To ensure that the earlier of the two ports wins.

L = CER = VIL.

2.

CE

3.OE = VIL for the reading port.

4. All timing is the same for the left and right ports. Port 'A' may be either the left or right
port. Port 'B' is opposite from port 'A'.

tAPS is ignored for Slave (IDT7142).

MATCH

t

WP

t

DW

VALID

MATCH

t

BDA

t

WDD

t

DDD

t

DH

t

BDD

VALID

2692 drw 11

6.02 8

IDT7132SA/LA AND IDT7142SA/LA
HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES

(3)

(2)

t

WP

(1)

t

WH

2692 drw 12

CECE

CE

TIMING

CECE

BUSY

t

WB

BUSYBUSY

BUSY

BUSYBUSY

'B' goes High.

TIMING WAVEFORM OF WRITE WITH

R/

W

L

BUSY

R

R/

W

R

NOTES:

WH must be met for both

1. t

2.

BUSY

is asserted on port 'B' blocking R/W'B', until

3. All timing is the same for the left and right ports. Port 'A' may be either the left or right port. Port 'B' is opposite from port 'A'.

BUSY

Input (IDT7142, slave) or Output (IDT7132, master).

TIMING WAVEFORM OF BUSY ARBITRATION CONTROLLED BY

(1)

ADDR

'A'

and

BUSY

CE

CE

'B'

'B'

(2)

t

APS

'A'

t

BAC

'A'

ADDRESSES MATCH

t

BDC

2692 drw 13

TIMING WAVEFORM OF BUSY ARBITRATION CONTROLLED BY ADDRESS MATCH TIMING

t

RC or tWC

ADDR

ADDR

BUSY

'A'

(2)

t

APS

'B'

'B'

ADDRESSES MATCH

t

BAA

ADDRESSES DO NOT MATCH

t

BDA

(1)

NOTES:

1. All timing is the same for left and right ports. Port 'A' may be either left or right port. Port 'B' is the opposite from port 'A'.

2. If t

APS is not satisified, the

BUSY

will be asserted on one side or the other, but there is no guarantee on which side

6.02 9

BUSY

2692 drw 14

will be asserted (7132 only).

IDT7132SA/LA AND IDT7142SA/LA
HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES

TRUTH TABLES

TABLE I — NON-CONTENTION
READ/WRITE CONTROL

Left or Right Port

WW

CECE

CE

CECE

OEOE

OE

OEOE

R/

W

WW

X H X Z Port Disabled and in Power-

XHX Z

L L X DATAIN Data Written Into Memory
H L L DATAOUT Data in Memory Output on Port
H L H Z High Impedance Outputs

NOTES: 2654 tbl 12

1. A0L – A10L ≠ A0R – A10R.

2. If

BUSY

3. If

4. 'H' = V

= L, data is not written.

BUSY

= L, data may not be valid, see t

IH, 'L' = VIL, 'X' = DON’T CARE, 'Z' = High-impedance.

(1)

D0–7 Function

(4)

Down Mode, I

CE

R = CEL = VIH, Power-Down

Mode, I

SB2 or ISB4

SB1 or ISB3

WDD and tDDD timing.

(2)

(3)

TABLE II — ADDRESS BUSY ARBITRATION

Inputs Outputs

0L-A10L

A

CECE

CECE

CE

CE

L

CECE

XX
HX
XH
LL

NOTES:

1. Pins
inputs for IDT7140 (slave).
drain, not push-pull outputs. On slaves the
writes.

2. 'L' if the inputs to the opposite port were stable prior to the address and
enable inputs of this port. 'H' if the inputs to the opposite port became
stable after the address and enable inputs of this port. If tAPS is not met,
either
not be low simultaneously.

3. Writes to the left port are internally ignored when
driving Low regardless of actual logic level on the pin. Writes to the right
port are internally ignored when
less of actual logic level on the pin.

R A0R-A10R

CECE

BUSY

L and

BUSY

L or

NO MATCH H H Normal

MATCH H H Normal
MATCH H H Normal
MATCH (2) (2) Write Inhibit

BUSY

R are both outputs for IDT7130 (master). Both are

BUSY

R = Low will result.

(1)

BUSYBUSY

BUSY

L

BUSYBUSY

X outputs on the IDT7130 are open

BUSY

R outputs are driving Low regard-

BUSY

(1)

BUSYBUSY

BUSY

R

BUSYBUSY

X input internally inhibits

BUSY

BUSY

L and

BUSY

BUSY

Function

(3)

2654 tbl 13

R outputs can

L outputs are

FUNCTIONAL DESCRIPTION

The IDT7132/IDT7142 provides two ports with separate
control, address and I/O pins that permit independent access
for reads or writes to any location in memory. The IDT7132/
IDT7142 has an automatic power down feature controlled by

CE

. The CE controls on-chip power down circuitry that
permits the respective port to go into a standby mode when
not selected (CE = VIL). When a port is enabled, access to the
entire memory array is permitted.

BUSY LOGIC

Busy Logic provides a hardware indication that both ports of
the RAM have accessed the same location at the same time.
It also allows one of the two accesses to proceed and signals
the other side that the RAM is “Busy”. The busy pin can then
be used to stall the access until the operation on the other
side is completed. If a write operation has been attempted
from the side that receives a busy indication, the write signal
is gated internally to prevent the write from proceeding.

The use of busy logic is not required or desirable for all
applications. In some cases it may be useful to logically OR
the busy outputs together and use any busy indication as an
interrupt source to flag the event of an illegal or illogical
operation. If the write inhibit function of busy logic is not
desirable, the busy logic can be disabled by placing the part
in slave mode with the M/S pin. Once in slave mode the

BUSY

pin operates solely as a write inhibit input pin. Normal
operation can be programmed by tying the
If desired, unintended write operations can be prevented to
a port by tying the busy pin for that port low.

The busy outputs on the IDT7132/IDT7142 RAM in master
mode, are pull-up type outputs and do not require pull up
resistors to operate. If these RAMs are being expanded in
depth, then the busy indication for the resulting array re­quires the use of an external AND gate.

BUSY

pins High.

6.02 10

IDT7132SA/LA AND IDT7142SA/LA
HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES

WIDTH EXPANSION WITH BUSY LOGIC
MASTER/SLAVE ARRAYS

When expanding an RAM array in width while using busy
logic, one master part is used to decide which side of the RAM
array will receive a busy indication, and to output that indica­tion. Any number of slaves to be addressed in the same
address range as the master, use the busy signal as a write
inhibit signal. Thus on the IDT7130/IDT7140 RAM the busy
pin is an output if the part is used as a master (M/S pin = VIH),
and the busy pin is an input if the part used as a slave (M/S pin
= VIL) as shown in Figure 4.

LEFT

R/

BUSY

+5V

R/

BUSY

W

W

IDT7132
MASTER

IDT7142

IDT7142

SLAVE

SLAVE

R/

W

BUSY

+5V

R/

W

(1)

BUSY

R/

W

USY

270 Ω

Figure 4. Busy and chip enable routing for both width and depth
expansion with IDT7132 (Master) and IDT7142 (Slave) RAMs.

270 Ω

RIGHT

R/

W

BUSY

2692 drw 15

If two or more master parts were used when expanding in
width, a split decision could result with one master indicating
busy on one side of the array and another master indicating
busy on one other side of the array. This would inhibit the write
operations from one port for part of a word and inhibit the write
operations from the other port for the other part of the word.

The busy arbitration, on a master, is based on the chip enable
and address signals only. It ignores whether an access is a
read or write. In a master/slave array, both address and chip
enable must be valid long enough for a busy flag to be output
from the master before the actual write pulse can be initiated
with either the R/W signal or the byte enables. Failure to
observe this timing can result in a glitched internal write inhibit
signal and corrupted data in the slave.

ORDERING INFORMATION

XXXXIDT

Device Type

A 999 A A

Power Speed Package

Process/

Temperature

Range

Blank
B

P
C
J
L48
F

20
25
35
55
100

LA
SA

Commercial (0°C to +70°C)
Military (–55°C to +125°C)

Compliant to MIL-STD-883, Class B

48-pin Plastic DIP (P48-1)
48-pin Sidebraze DIP (C48-2)
52-pin PLCC (J52-1)
48-pin LCC (L48-1)
48-pin Ceramic Flatpack (F48-1)

Commercial PLCC Only

Speed in nanoseconds

Low Power
Standard Power

7132
7142

6.02 11

16K (2K x 8-Bit) MASTER Dual-Port RAM
16K (2K x 8-Bit) SLAVE Dual-Port RAM

2692 drw 16