Datasheet IDT71321LA20J, IDT71321LA20PF, IDT71321LA25J, IDT71321LA25PF, IDT71321LA25TF Datasheet (Integrated Device Technology Inc)
...
Integrated Device Technology, Inc.
HIGH-SPEED 2K x 8
DUAL-PORT STATIC RAM
WITH INTERRUPTS
IDT71321SA/LA
IDT71421SA/LA
FEATURES:
• High-speed access
—Commercial: 20/25/35/45/55ns (max.)
• Low-power operation
—IDT71321/IDT71421SA
—Active: 550mW (typ.)
—Standby: 5mW (typ.)
—IDT71321/421LA
—Active: 550mW (typ.)
—Standby: 1mW (typ.)
• Two
• MASTER IDT71321 easily expands data bus width to 16-
• On-chip port arbitration logic (IDT71321 only)
•
• Fully asynchronous operation from either port
• Battery backup operation —2V data retention (LA Only)
• TTL-compatible, single 5V ±10% power supply
• Available in popular hermetic and plastic packages
• Industrial temperature range (–40°C to +85°C) is avail-
INT
flags for port-to-port communications
or-more-bits using SLAVE IDT71421
BUSY
output flag on IDT71321;
BUSY
input on IDT71421
able, tested to military electrical specifications
DESCRIPTION:
The IDT71321/IDT71421 are high-speed 2K x 8 DualPort Static RAMs with internal interrupt logic for interprocessor communications. The IDT71321 is designed to be used
as a stand-alone 8-bit Dual-Port RAM or as a "MASTER"
Dual-Port RAM together with the IDT71421 "SLAVE" DualPort in 16-bit-or-more word width systems. Using the IDT
MASTER/SLAVE Dual-Port RAM approach in 16-or-morebit memory system applications results in full speed, errorfree operation without the need for additional discrete logic.
Both devices provide two independent ports with separate control, address, and I/O pins that permit independent,
asynchronous access for reads or writes to any location in
memory. An automatic power down feature, controlled by
CE
, permits the on chip circuitry of each port to enter a very
low standby power mode.
Fabricated using IDT's CMOS high-performance technology, these devices typically operate on only 550mW of
power. Low-power (LA) versions offer battery backup data
retention capability, with each Dual-Port typically consuming 200µW from a 2V battery.
The IDT71321/IDT71421 devices are packaged in a 52pin PLCC, a 64-pin TQFP, and a 64-pin STQFP.
FUNCTIONAL BLOCK DIAGRAM
OE
L
CE
L
L
R/
W
I/O0L- I/O
7L
(1,2) (1,2)
BUSY
L
A
10L
A
0L
NOTES:
1. IDT71321 (MASTER):
is open drain output and
requires pullup resistor of 270Ω.
IDT71421 (SLAVE):
2. Open drain output: requires pullup
resistor of 270Ω.
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
BUSY
BUSY
is input.
INT
(2)
L
Address
Decoder
OE
R
CE
R
R/
W
R
I/O0R-I/O
BUSY
A
10R
A
0R
INT
7R
R
(2)
R
I/O
Control
MEMORY
ARRAY
11
ARBITRATION
CE
L
OE
L
R/
W
L
and
INTERRUPT
LOGIC
I/O
Control
Address
Decoder
11
CE
R
OE
R
R/
W
R
2691 drw 01
COMMERCIAL TEMPERATURE RANGE OCTOBER 1996
©1996 Integrated Device Technology, Inc. DSC-2691/6
For latest information contact IDT’s web site at www.idt.com or fax-on-demand at 408-492-8391.
6.03
1
IDT71321SA/LA AND IDT71421SA/LA
INDEX
IDT71321/421
PN64-1 / PP64-1
64-PIN TQFP
64-PIN STQFP
TOP VIEW
(3)
8
9
10
11
12
13
14
15
16
1
2
3
4
5
6
7
46
45
44
43
42
41
40
39
38
37
36
35
34
47
48
33
I/O
6R
N/C
A
0R
A
1R
A
2R
A
3R
A
4R
A
5R
A
6R
A
7R
A
8R
A
9R
I/O
7R
OE
R
N/C
N/C
I/O
2L
A
0L
OE
L
A
1L
A
2L
A
3L
A
4L
A
5L
A
6L
A
7L
A
8L
A
9L
I/O
0L
I/O
1L
N/C
N/C
BUSY
L
CE
L
INT
L
2691 drw 03
R/
W
L
17
18
19
20
32
31
30
29
28
27
26
25
24
23
22
21
49
50
51
52
63
62
61
605958
57
56
55
54
53
64
GND
4L
I/O
5L
I/O
6L
I/O
7L
I/O
I/O
0R
I/O
1R
I/O
2R
I/O
3R
I/O
4R
I/O
5R
I/O
3L
N/C
N/C
GND
N/C
N/C
A
10R
V
CC
CE
R
R/
W
R
BUSY
R
N/C
N/C
A
10L
V
CC
N/C
INT
R
HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATIONS
L
L
0L
NDEX
I/O
I/O
I/O
I/O
A
1L
8
A
2L
9
A
3L
10
A
4L
11
A
5L
12
A
6L
13
A
7L
14
A
8L
15
A
9L
16
0L
17
1L
18
2L
19
20
3L
OE
A
4L5L6L
I/O
I/O
10L
A
I/O
INT
7L
I/O
(1,2)
L
L
R/W
BUSY
CELVCCCE
234567474849505152
1
IDT71321/421
J52-1
PLCC
TOP VIEW
27262524232221 333231302928
0R1R2R3R4R6R5R
NC
GND
I/O
I/O
R
R
R/W
I/O
R
INT
BUSY
I/O
I/O
46
45
44
43
42
41
40
39
38
37
36
35
34
10R
A
I/O
OE
A
0R
A
1R
A
2R
A
3R
A
4R
A
5R
A
6R
A
7R
A
8R
A
9R
NC
I/O
2691 drw 02
R
(3)
I/O
NOTES:
1. All Vcc pins must be connected to the power supply.
2. All GND pins must be connected to the ground supply.
3. This text does not indicate orientation of the actual part-marking.
R
7R
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol Rating Commercial Unit
(2)
V
TERM
Terminal Voltage –0.5 to +7.0 V
with Respect to
GND
T
A Operating 0 to +70 °C
Temperature
T
BIAS Temperature –55 to +125 °C
Under Bias
T
STG Storage –55 to +125 °C
Temperature
I
OUT DC Output 50 mA
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
any other conditions above those indicated in the operational sections
of the specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
2. VTERM must not exceed Vcc + 0.5 for more than 25% of the cycle time
or 10ns maximum, and is limited to
Vcc + 0.5V.
stress rating only and functional operation of the device at these or
Current
< 20mA for the period of VTERM >
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Ambient
Grade Temperature GND V
CC
Commercial 0°C to +70°C 0V 5.0V ± 10%
2691 tbl 02
RECOMMENDED
DC OPERATING CONDITIONS
Symbol Parameter Min. Typ. Max. Unit
V
CC Supply Voltage 4.5 5.0 5.5 V
GND Supply Voltage 0 0 0 V
(2)
(2)
V
2691 tbl 03
Max. Unit
2691 tbl 04
V
2691 tbl 01
IH Input High Voltage 2.2 — 6.0
V
IL Input Low Voltage –0.5 — 0.8 V
(1)
NOTES:
IL (min.) = -1.5V for pulse width less than 10ns.
1. V
2. VTERM must not exceed Vcc + 0.5V.
CAPACITANCE
(1,3)
(TA = +25°C, f = 1.0MHz) TQFP ONLY
Symbol Parameter Conditions
C
IN Input Capacitance VIN = 3dV 9 pF
C
OUT Output Capacitance VIN = 3dV 10 pF
NOTES:
1. This parameter is determined by device characterization but is not
production tested.
2. 3dv references the interpolated capacitance when the input and output
signals switch from 0V to 3V or from 3V to 0V.
3. 11pF max. for other packages.
6.03 2
IDT71321SA/LA AND IDT71421SA/LA
HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS COMMERCIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER THE
(1,4)
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE
71321X20 71321X25 71321X35 71321X55 71321X100
71421X25 71421X35 71421X55 71421X100
Symbol Parameter Test Conditions Version Typ. Max. Typ. Max. Typ. Max. Typ. Max. Typ. Max. Unit
I
CC Dynamic Operating
Current (Both Ports Outputs open, LA — — 110 220 80 170 65 140 65 140
Active) f = f
I
SB1 Standby Current
(Both Ports - TTL f = f
Level Inputs) COM'L. SA 30 65 30 65 25 65 20 65 20 55
I
SB2 Standby Current
(One Port - TTL
Level Inputs) Active Port Outputs COM'L. SA 65 165 65 150 50 125 40 110 40 110
I
SB3 Full Standby CurrentCEL and MIL. SA — — 1.0 30 1.0 30 1.0 30 1.0 30 mA
(Both Ports - All
CMOS Level Inputs V
SB4 Full Standby Current
I
(One Port - All
CMOS Level Inputs) V
NOTES: 2689 tbl 05
1. 'X' in part numbers indicates power rating (SA or LA).
2. At f = f
3. f = 0 means no address or control lines change. Applies only to inputs at CMOS level standby.
4. Vcc = 5V, T
5. Port "A" may be either left or right port. Port "B" is opposite from port "A".
Max, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, and using “AC TEST CONDITIONS”
of input levels of GND to 3V.
A=+25°C for Typ. and is not production tested. Vcc DC = 100mA (Typ)
CE
L and CER = VIL, MIL. SA — — 110 280 80 230 65 190 65 190 mA
(2)
MAX
COM'L. SA 110 250 110 220 80 165 65 155 65 155
LA 110 200 110 170 80 120 65 110 65 110
CE
L and CER = VIH, MIL. SA — — 30 80 25 80 20 65 20 65 mA
(2)
MAX
LA — — 30 60 25 60 20 45 20 45
LA 30 45 30 45 25 45 20 35 20 35
CE
"A" = VIL and MIL. SA — — 65 160 50 150 40 125 40 125 mA
CE
"B" = VIH
Open, f = f
CE
R > VCC -0.2V, LA — — 0.2 10 0.2 10 0.2 10 0.2 10
IN > VCC -0.2V or COM'L. SA 1.0 15 1.0 15 1.0 15 1.0 15 1.0 15
V
IN < 0.2V,f = 0
CE
"A" < 0.2V and MIL. SA — — 60 155 45 145 40 110 40 110 mA
CE
"B" > VCC -0.2V
IN > VCC -0.2V or COM'L. SA 60 155 60 145 45 110 40 100 40 95
V
IN < 0.2V, LA 60 115 60 105 45 85 40 70 40 70
(5)
MAX
LA — — 65 125 50 115 40 90 40 90
(2)
(3)
(5)
LA 65 125 65 115 50 90 40 75 40 75
LA 0.2 5 0.2 5 0.2 4 0.2 4 0.2 4
LA — — 60 115 45 105 40 85 40 80
Active Port Outputs
Open, f = f
MAX
(2)
(VCC = 5.0V ± 10%)
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE
IDT71321SA
Symbol Parameter Test Conditions Min. Max. Min. Max. Unit
Ll| Input Leakage VCC = 5.5V, — 10 — 5 µA
|l
|lLO| Output Leakage
Current
Current
(1)
(1)
VIN = 0V to VCCVIN = GND to VCC
CE
= VIH, VOUT = 0V to VCC —10 — 5 µA
VCC = 5.5V
C-=S
= VIH, VOUT = GND to VCC
VOL Output Low Voltage lOL = 4mA — 0.4 — 0.4 V
(l/O
0-l/O7) lOL= 16mA
OL Open Drain Output Low lOL = 16mA — 0.5 — 0.5 V
V
Voltage (
V
OH Output High Voltage lOH = -4mA 2.4 — 2.4 — V
NOTE: 1. At Vcc < 2.0V leakages are undefined. Supply CurrentVIN > VCC -0.2V or < 0.
BUSY,INT
)
6.03 3
IDT71421SA
(VCC = 5.0V ± 10%)
lDT71321LA
lDT71421LA
2691 tbl 06
IDT71321SA/LA AND IDT71421SA/LA
HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS COMMERCIAL TEMPERATURE RANGE
DATA RETENTION CHARACTERISTICS (LA Version Only)
71321LA/71421LA
Symbol Parameter Test Conditions Min. Typ.
V
DR VCC for Data Retention 2.0 — 0 V
CCDR Data Retention Current VCC = 2.0V,
I
(3)
t
CDR
Chip Deselect to Data VIN > VCC - 0.2V or VIN≤ 0.2V 0 — — ns
CE
> VCC - 0.2V COM'L. — 100 1500 µA
Retention Time
(3)
R
t
Operation Recovery tRC
(2)
Time
NOTES:
1. V
CC = 2V, TA = +25°C, and is not production tested.
RC = Read Cycle Time
2. t
3. This parameter is guaranteed by device characterization but not production tested.
(1)
Max. Unit
—— ns
2691 tbl 07
DATA RETENTION WAVEFORM
DATA RETENTION MODE
V
CE
CC
4.5V 4.5V
t
CDR
V
IH
DATA
V
DR
≥
2.0V
V
DR
5V
OUT
775Ω
Figure 1. AC Output Test Load
AC TEST CONDITIONS
t
R
V
IH
2691 drw 04
1250Ω
30pF
100pF for 55 and 100ns versions
Input Pulse Levels GND to 3.0V
Input Rise/Fall Times 5ns
Input Timing Reference Levels 1.5V
Output Reference Levels 1.5V
Output Load Figures 1, 2, and 3
5V
1250Ω
DATA
OUT
775Ω
Figure 2. Output Test Load
HZ, tLZ, tWZ, and tOW)
(for t
* Including scope and jig.
5pF
2691 tbl 08
BUSY
or
INT
Figure 3.
AC Output Test Load
5V
270Ω
30pF
100pF for 55 and 100ns versions
BUSYBUSY
BUSY
BUSYBUSY
and I
NTNT
NT
NTNT
2691 drw 05
6.03 4
IDT71321SA/LA AND IDT71421SA/LA
HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS COMMERCIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE
71321X20 71321X25 71321X35 71321X55 71321X100
71421X25 71421X35 71421X55 71421X100
Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
Read Cycle
t
RC Read Cycle Time 20 — 25 — 35 — 55 — 100 — ns
t
AA Address Access Time — 20 — 25 — 35 — 55 — 100 ns
t
ACE Chip Enable Access Time — 20 — 25 — 35 — 55 — 100 ns
t
AOE Output Enable Access Time 11 — 12 — 20 — 25 — 40 ns
t
OH Output Hold From Address Change 3 — 3 — 3 — 3 — 10 — ns
LZ Output Low-Z Time
t
t
HZ Output High-Z Time
t
PU Chip Enable to Power Up Time
t
PD Chip Disable to Power Down Time
NOTES:
1. Transition is measured ±500mV from Low or High-impedance voltage Output Test Load (Figure 2).
2. “X” in part numbers indicates power rating (SA or LA).
3. This parameter is guaranteed by device characterization, but is not production tested.
(1,3)
(1,3)
0— 0 — 0 — 5 — 5 —ns
— 10 — 10 — 15 — 25 — 40 ns
(3)
(3)
0— 0 — 0 —0 — 0 —ns
— 20 — 25 — 35 — 50 — 50 ns
(2)
2689 tbl 09
TIMING WAVEFORM OF READ CYCLE NO. 1, EITHER SIDE
t
RC
(1)
ADDRESS
t
t
AA
t
OH
OUT
DATA
BUSY
NOTES:
1. R/W = V
2. t
BDD delay is required only in the case where the opposite port is completing a write operation to the same address location. For simultaneous read
operations
3. Start of valid data depends on which timing becomes effective last t
PREVIOUS DATA VALID
OUT
IH,
CE
= VIL, and OE = VIL. Address is valid prior to or coincidental with CE transition Low.
BUSY
has no relationship to valid output data.
t
BDDH
AOE, tACE, tAA, and tBDD.
DATA VALID
(2,3)
OH
2691 drw 06
6.03 5
IDT71321SA/LA AND IDT71421SA/LA
HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OF READ CYCLE NO. 2, EITHER SIDE
t
ACE
(3)
CE
t
AOE
(4)
(2)
t
HZ
OE
t
LZ
OUT
DATA
(1)
t
LZ
50%
I
CC
CURRENT
I
SS
t
PU
NOTES:
1. Timing depends on which signal is asserted last, OE or CE.
2. Timing depends on which signal is deaserted first, OE or CE.
3. R/W = V
IH and the address is valid prior to or coincidental with
CE
4. Start of valid data depends on which timing becomes effective last t
(1)
transition Low.
AOE, tACE, tAA, and tBDD.
VALID DATA
t
PD
(2)
t
HZ
(4)
50%
2691 drw 07
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE
71321X20 71321X25 71321X35 71321X55 71321X100
71421X25 71421X35 71421X55 71421X100
Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
Write Cycle
t
WC Write Cycle Time
t
EW Chip Enable to End of Write 15 — 20 — 30 — 40 — 90 — ns
t
AW Address Valid to End of Write 15 — 20 — 30 — 40 — 90 — ns
t
AS Address Set-up Time 0 — 0 — 0 — 0 — 0 — ns
t
WP Write Pulse Width
t
WR Write Recovery Time 0 — 0 — 0 — 0 — 0 — ns
t
DW Data Valid to End of Write 10 — 12 — 15 — 20 — 40 — ns
t
HZ Output High-Z Time
t
DH Data Hold Time 0 — 0 — 0 — 0 — 0 — ns
t
WZ Write Enabled to Output in High-Z
t
OW Output Active From End of Write
NOTES: 2692 tbl 10
1. Transition is measured ±500mV from Low or High-impedance voltage with Output Test Load (Figure 2). This parameter is guaranteed by
device characterization but is not production tested.
2. For Master/Slave combination, t
3. If OE is low during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off
data to be placed on the bus for the required t
write pulse can be as short as the specified t
4. “X” in part numbers indicates power rating (SA or LA).
(2)
(3)
(1)
(1)
(1)
WC = tBAA + tWP, since R/
DW. If
WP.
20 — 25 — 35 — 55 — 100 — ns
15 — 15 — 25 — 30 — 55 — ns
— 10 — 10 — 15 — 25 — 40 ns
— 10 — 10 — 15 — 30 — 40 ns
0— 0— 0— 0— 0— ns
W
= VIL must occur after tBAA .
OE
is High during a R/W controlled write cycle, this requirement does not apply and the
(4)
6.03 6
IDT71321SA/LA AND IDT71421SA/LA
HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OF WRITE CYCLE NO. 1, (R/
t
WC
ADDRESS
OE
t
AW
CE
DATA
DATA
R/
OUT
W
(6)
t
AS
(7)
t
WZ
(4) (4)
IN
t
WP
(2)
TIMING WAVEFORM OF WRITE CYCLE NO. 2, (
WW
W
CONTROLLED TIMING)
WW
(3)
t
WR
t
DW
CECE
CE
CONTROLLED TIMING)
CECE
t
DH
t
OW
(1,5,8)
(1,5)
(7)
t
HZ
(7)
t
HZ
2691 drw 08
t
WC
ADDRESS
t
AW
CE
(6)
t
AS
R/
W
IN
DATA
NOTES:
1. R/W or CE must be High during all address transitions.
2. A write occurs during the overlap (t
3. tWR is measured from the earlier of CE or R/W going High to the end of the write cycle.
4. During this period, the l/O pins are in the output state and input signals must not be applied.
5. If the CE Low transition occurs simultaneously with or after the R/W Low transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal (CE or R/W) is asserted last.
7. This parameter is determined be device characterization, but is not production tested. Transition is measured +/- 500mV from steady state
with the Output Test Load (Figure 2).
8. If OE is Low during a R/W controlled write cycle, the write pulse width must be the larger of t
data to be placed on the bus for the required t
write pulse can be as short as the specified t
EW or tWP) of
WP.
CE
= VIL and R/W= VIL.
DW. If
OE
is High during a R/W controlled write cycle, this requirement does not apply and the
t
EW
(2)
t
DW
WP or (tWZ + tDW) to allow the I/O drivers to turn off
t
WR
(3)
t
DH
2691 drw 09
6.03 7
IDT71321SA/LA AND IDT71421SA/LA
HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS COMMERCIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS OVER THE
(6)8
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE
71321X20 71321X25 71321X35 71321X55 71321X100
71421X25 71421X35 71421X55 71421X100
Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
Busy Timing (For Master lDT71321 Only)
BAA
t
BDA
t
BAC
t
BDC
t
WH Write Hold After
t
WDD Write Pulse to Data Delay
t
DDD Write Data Valid to Read Data Delay
t
APS Arbitration Priority Set-up Time
t
BDD
t
Busy Timing (For Slave IDT71421 Only)e5—5—5—5—5
WB Write to
t
WH Write Hold After
t
WDD Write Pulse to Data Delay
t
DDD Write Data Valid to Read Data Delay
t
NOTES: 2689 tbl 11
1. Port-to-port delay through RAM cells from the writing port to the reading port, refer to “Timing Waveform of Write with Port-to-Port Read and
2. To ensure that the earlier of the two ports wins.
3. t
4. To ensure that a write cycle is inhibited on port 'B' during contention on port 'A'.
5. To ensure that a write cycle is completed on port 'B' after contention on port 'A'.
6. “X” in part numbers indicates power rating (S or L).
BUSY
Access Time from Address — 20 — 20 — 20 — 30 — 50 ns
BUSY
Disable Time from Address — 20 — 20 — 20 — 30 — 50 ns
BUSY
Access Time from Chip Enable — 20 — 20 — 20 — 30 — 50 ns
BUSY
Disable Time from Chip Enable — 20 — 20 — 20 — 30 — 50 ns
BUSY
Disable to Valid Data
BUSY
Input
BDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual), or tDDD – tDW (actual).
BUSY
(4)
BUSY
(5)
(1)
(1)
(2)
(3)
12 — 15 — 20 — 20 — 20 — ns
— 50 — 50 — 60 — 80 — 120 ns
— 35 — 35 — 35 — 55 — 100 ns
5— 5— 5 — 5—5 — ns
— 25 — 35 — 35 — 50 — 65 ns
0— 0— 0 — 0—0 — ns
(5)
(1)
(1)
12 — 15 — 20 — 20 — 20 — ns
— 40 — 50 — 60 — 80 — 120 ns
— 30 — 35 — 35 — 55 — 100 ns
M824S258M824S30 7132158M824S4
BUSY
."
t
DH
(2,3,4)
t
BDD
t
DDD
BUSYBUSY
BUSY
BUSYBUSY
TIMING WAVEFORM OF WRITE WITH PORT-TO-PORT READ AND
t
WC
ADDR
’A’
R/
W
’A’
DATA
IN’A’
(1)
t
APS
ADDR
’B’
BUSY
’B’
DATA
OUT’B’
NOTES:
1. To ensure that the earlier of the two ports wins.
2.
CE
L = CER = VIL.
3.OE = VIL for the reading port.
4. All timing is the same for the left and right ports. Port 'A' may be either the left or right port. Port 'B' is opposite from port 'A'.
tAPS is ignored for Slave (IDT71421).
MATCH
t
WP
t
DW
VALID
MATCH
t
BDA
t
WDD
VALID
2691 drw 10
6.03 8
IDT71321SA/LA AND IDT71421SA/LA
HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS COMMERCIAL TEMPERATURE RANGE
(3)
(2)
t
WP
t
(1)
WH
2691 drw 11
t
WB
BUSY
'B' goes High.
BUSYBUSY
BUSY
BUSYBUSY
TIMING WAVEFORM OF WRITE WITH
R/
W
L
BUSY
R
R/
W
R
NOTES:
WH must be met for both
1. t
2.
BUSY
is asserted on port 'B' blocking R/
3. All timing is the same for the left and right ports. Port 'A' may be either the left or right port. Port 'B' is opposite from port 'A'.
BUSY
Input (IDT71421, slave) or Output (IDT71321, master).
W
'B', until
TIMING WAVEFORM OF BUSY ARBITRATION CONTROLLED BY
ADDR
and
CE
CE
BUSY
'A'
'B'
'B'
(2)
t
APS
'A'
t
BAC
'A'
ADDRESSES MATCH
t
BDC
CECE
CE
TIMING
CECE
(1)
2691 drw 12
TIMING WAVEFORM OF BUSY ARBITRATION CONTROLLED BY ADDRESS MATCH TIMING
t
RC OR tWC
ADDR
'A'
(2)
t
APS
ADDRESSES MATCH
ADDRESSES DO NOT MATCH
(1)
ADDR
'B'
t
BAA
BUSY
'B'
NOTES:
1. All timing is the same for left and right ports. Port 'A' may be either left or right port. Port 'B' is the opposite from port 'A'.
APS is not satisified, the
2. If t
asserted (71321 only).
BUSY
will be asserted on one side or the other, but there is no guarantee on which side
6.03 9
t
BDA
BUSY
2691 drw 13
will be
IDT71321SA/LA AND IDT71421SA/LA
HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS COMMERCIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS OVER THE
(1)
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE
8M824S25 8M824S308M824S35
71321X25 71321X35 71321X45 71321X55
71421X25 71421X35 71421X45 71421X55
Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Unit
Interrupt Timing
t
AS Address Set-up Time 0 — 0 — 0 — 0 — ns
t
WR Write Recovery Time 0 — 0 — 0 — 0 — ns
t
INS Interrupt Set Time — 25 — 25 — 35 — 45 ns
t
INR Interrupt Reset Time — 25 — 25 — 35 — 45 ns
NOTE:
1. "X" in part numbers indicates power rating (S or L).
2689 tbl 12
TIMING WAVEFORM OF INTERRUPT MODE
INTINT
SET
INT
INTINT
ADDR
'A'
R/
W
'A'
INT
'B'
CLEAR
'B'
ADDR
OE
'B'
INTINT
INT
INTINT
t
WC
INTERRUPT ADDRESS
(3)
t
AS
(3)
t
INS
(2)
(4)
t
WR
2691 drw 14
t
RC
INTERRUPT CLEAR ADDRESS
(3)
t
AS
(3)
t
INR
INT
'B'
NOTES:
1. All timing is the same for left and right ports. Port 'A' may be either left or right port. Port 'B' is the opposite from port 'A'.
2. See Interrupt Truth Table.
3. Timing depends on which enable signal (CE or R/W) is asserted last.
4. Timing depends on which enable signal (CE or R/W) is de-asserted first.
6.03 10
2691 drw 15
IDT71321SA/LA AND IDT71421SA/LA
HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS COMMERCIAL TEMPERATURE RANGE
TRUTH TABLES
TABLE I —
NON-CONTENTION READ/WRITE CONTROL
Left or Right Port
WW
CECE
CE
CECE
OEOE
OE
OEOE
R/
W
WW
X H X Z Port Disabled and in Power-
XHX Z
L L X DATAIN Data on Port Written Into Memory
H L L DATAOUT Data in Memory Output on Port
H L H Z High-impedance Outputs
NOTES: 2654 tbl 13
1. A0L – A10L ≠ A0R – A10R.
2. If
BUSY
3. If
BUSY
4. 'H' = V
IL, data is not written.
= V
IL, data may not be valid, see tWDD and tDDD timing.
= V
IH, 'L' = VIL, 'X' = DON’T CARE, 'Z' = High-impedance.
TABLE II — INTERRUPT FLAG
WW
R/
LLX 7FF XXXX X L
X X X X X X L L 7FF H
XXX X L
X L L 7FE H
NOTES: 2654 tbl 14
1. Assumes
2. If
3. If
4. 'H' = V
CECE
W
CE
L
WW
BUSY
BUSY
L
CECE
BUSY
L = VIL, then No Change.
R = VIL, then No Change.
IH, 'L' = VIL, 'X' = DON’T CARE.
(1)
D0–7 Function
Down Mode, I
CE
R = CEL = VIH, Power-Down
Mode, I
SB2 or ISB4
SB1 or ISB3
(1,4)
Left Port Right Port
L =
OEOE
OE
OEOE
BUSY
L A10L – A0L
R = VIH
INTINT
INT
INTINT
L R/
(3)
(2)
WW
W
WW
L L X 7FE X Set Left
X X X X X Reset Left
(4)
(2)
(3)
CECE
CE
R
CECE
OEOE
OE
R
R A10L – A0R
OEOE
INTINT
INT
R Function
INTINT
(2)
(3)
Set Right
Reset Right
INT
INT
R Flag
INT
L Flag
INT
R Flag
L Flag
TABLE III — ADDRESS BUSY ARBITRATION
Inputs Outputs
0L-A10L
A
CECE
CECE
CE
CE
L
CECE
XX
HX
XH
LL
NOTES:
1. Pins
inputs for IDT71421 (slave).
drain, not push-pull outputs. On slaves the
writes.
2. 'L' if the inputs to the opposite port were stable prior to the address and
enable inputs of this port. 'H' if the inputs to the opposite port became
stable after the address and enable inputs of this port. If tAPS is not met,
either
can not be low simultaneously.
3. Writes to the left port are internally ignored when
driving Low regardless of actual logic level on the pin. Writes to the right
port are internally ignored when
less of actual logic level on the pin.
R A0R-A10R
CECE
L and
BUSY
BUSY
L or
NO MATCH H H Normal
MATCH H H Normal
MATCH H H Normal
MATCH (2) (2) Write Inhibit
BUSY
R are both outputs for IDT71321 (master). Both are
BUSY
R = Low will result.
(1)
BUSYBUSY
BUSY
L
BUSYBUSY
X outputs on the IDT71321 are open
BUSY
R outputs are driving Low regard-
BUSY
(1)
BUSYBUSY
BUSY
R
BUSYBUSY
BUSY
X input internally inhibits
BUSY
L and
BUSY
BUSY
Function
(3)
2689 tbl 15
R outputs
L outputs are
6.03 11
IDT71321SA/LA AND IDT71421SA/LA
2691 drw 16
MASTER
Dual Port
RAM
BUSY
L
BUSY
R
CE
MASTER
Dual Port
RAM
BUSY
L
BUSY
R
CE
SLAVE
Dual Port
RAM
BUSY
L
BUSY
R
CE
SLAVE
Dual Port
RAM
BUSY
L
BUSY
R
CE
BUSY
L
BUSY
R
DECODER
5V
5V
270Ω
270Ω
HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS COMMERCIAL TEMPERATURE RANGE
FUNCTIONAL DESCRIPTION
The IDT71321/IDT71421 provides two ports with separate
control, address and I/O pins that permit independent access
for reads or writes to any location in memory. The IDT71321/
IDT71421 has an automatic power down feature controlled
by CE. The CE controls on-chip power down circuitry that
permits the respective port to go into a standby mode when
not selected (CE = VIH). When a port is enabled, access to the
entire memory array is permitted.
INTERRUPTS
If the user chooses to use the interrupt function, a memory
location (mail box or message center) is assigned to each
port. The left port interrupt flag (
right port writes to memory location 7FE (HEX), where a write
is defined as the CE = R/W = VIL per the Truth Table. The left
port clears the interrupt by access address location 7FE
access when
CE
R = OER = VIL, R/
Likewise, the right port interrupt flag (
the left port writes to memory location 7FF (HEX) and to clear
the interrupt flag (
INT
R), the right port must access the
memory location 7FF. The message (8 bits) at 7FE or 7FF
is user-defined, since it is an addressable SRAM location. If
the interrupt function is not used, address locations 7FE and
7FF are not used as mail boxes, but as part of the random
access memory. Refer to Table I for the interrupt operation.
INT
L) is asserted when the
W
is a "Don't Care".
INT
R) is asserted when
The Busy outputs on the IDT71321 RAM (Master) are open
drain type outputs and require open drain resistors to operate.
If these RAMs are being expanded in depth, then the Busy
indication for the resulting array does not require the use of an
external AND gate.
WIDTH EXPANSION WITH BUSY LOGIC
MASTER/SLAVE ARRAYS
When expanding an RAM array in width while using busy
logic, one master part is used to decide which side of the RAM
array will receive a busy indication, and to output that indication. Any number of slaves to be addressed in the same
address range as the master, use the busy signal as a write
inhibit signal. Thus on the IDT71321/IDT71421 RAMs the
Busy pin is an output if the part is Master (IDT71321), and the
Busy pin is an input if the part is a Slave (IDT71421) as shown
in Figure 4.
BUSY LOGIC
Busy Logic provides a hardware indication that both ports of
the RAM have accessed the same location at the same time.
It also allows one of the two accesses to proceed and signals
the other side that the RAM is “Busy”. The Busy pin can then
be used to stall the access until the operation on the other
side is completed. If a write operation has been attempted
from the side that receives a busy indication, the write signal
is gated internally to prevent the write from proceeding.
The use of busy logic is not required or desirable for all
applications. In some cases it may be useful to logically OR
the busy outputs together and use any busy indication as an
interrupt source to flag the event of an illegal or illogical
operation. In slave mode the
a write inhibit input pin. Normal operation can be programmed by tying the
BUSY
write operations can be prevented to a port by tying the Busy
pin for that port Low.
BUSY
pin operates solely as
pins High. If desired, unintended
Figure 4. Busy and chip enable routing for both width and depth
expansion with IDT71321 (Master) and (Slave) IDT71421 RAMs.
If two or more master parts were used when expanding in
width, a split decision could result with one master indicating
busy on one side of the array and another master indicating
busy on one other side of the array. This would inhibit the write
operations from one port for part of a word and inhibit the write
operations from the other port for the other part of the word.
The Busy arbitration, on a Master, is based on the chip enable
and address signals only. It ignores whether an access is a
read or write. In a master/slave array, both address and chip
enable must be valid long enough for a busy flag to be output
from the master before the actual write pulse can be initiated
with either the R/W signal or the byte enables. Failure to
observe this timing can result in a glitched internal write inhibit
signal and corrupted data in the slave.
6.03 12
IDT71321SA/LA AND IDT71421SA/LA
HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS COMMERCIAL TEMPERATURE RANGE
ORDERING INFORMATION
XXXXIDT
Device Type
A 999 A A
Power Speed Package
Temperature
Process/
Range
Blank
J
PF
TF
20
25
35
45
55
LA
SA
71321
71421
Commercial (0°C to +70°C)
52-pin PLCC (J52-1)
64-pin TQFP (PN64-1)
64-pin STQFP (PP64-1)
Speed in nanoseconds
Low Power
Standard Power
16K (2K x 8-Bit) MASTER Dual-Port RAM
w/ Interrupt
16K (2K x 8-Bit) SLAVE Dual-Port RAM
w/ Interrupt
2691 drw 17
6.03 13
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