Datasheet IDT7130SA, IDT7130LA, IDT7140SA, IDT7140LA Datasheet (IDT)

查询IDT7130LA100C供应商

HIGH-SPEED
1K x 8 DUAL-PORT
STATIC RAM

Integrated Device Technology, Inc.

FEATURES

• High-speed access
—Military: 25/35/55/100ns (max.)
—Commercial: 25/35/55/100ns (max.)
—Commercial: 20ns 7130 in PLCC and TQFP

• Low-power operation
—IDT7130/IDT7140SA

—Active: 550mW (typ.)
—Standby: 5mW (typ.)

—IDT7130/IDT7140LA

—Active: 550mW (typ.)
—Standby: 1mW (typ.)

• MASTER IDT7130 easily expands data bus width to
16-or-more-bits using SLAVE IDT7140

• On-chip port arbitration logic (IDT7130 Only)

•

BUSY

output flag on IDT7130;

• Interrupt flags for port-to-port communication

• Fully asynchronous operation from either port

• Battery backup operation–2V data retention (LA only)

• TTL-compatible, single 5V ±10% power supply

• Military product compliant to MIL-STD-883, Class B

• Standard Military Drawing #5962-86875

• Industrial temperature range (–40°C to +85°C) is avail­able, tested to military electrical specifications

BUSY

input on IDT7140

IDT7130SA/LA
IDT7140SA/LA

DESCRIPTION

The IDT7130/IDT7140 are high-speed 1K x 8 Dual-Port
Static RAMs. The IDT7130 is designed to be used as a
stand-alone 8-bit Dual-Port RAM or as a "MASTER" Dual­Port RAM together with the IDT7140 "SLAVE" Dual-Port in
16-bit-or-more word width systems. Using the IDT MAS­TER/SLAVE Dual-Port RAM approach in 16-or-more-bit
memory system applications results in full-speed, error-free
operation without the need for additional discrete logic.

Both devices provide two independent ports with sepa­rate control, address, and I/O pins that permit independent
asynchronous access for reads or writes to any location in
memory. An automatic power down feature, controlled by

CE

, permits the on chip circuitry of each port to enter a very

low standby power mode.

Fabricated using IDT's CMOS high-performance tech­nology, these devices typically operate on only 550mW of
power. Low-power (LA) versions offer battery backup data
retention capability, with each Dual-Port typically consum­ing 200µW from a 2V battery.

The IDT7130/IDT7140 devices are packaged in 48-pin
sidebraze or plastic DIPs, LCCs, or flatpacks, 52-pin PLCC,
and 64-pin TQFP and STQFP. Military grade product is
manufactured in compliance with the latest revision of MIL­STD-883, Class B, making it ideally suited to military tem­perature applications demanding the highest level of per­formance and reliability.

FUNCTIONAL BLOCK DIAGRAM

OE

CE

R/

I/O0R-I/O7R

BUSY

INT

2689 drw 01

W

A9R
A0R

R

R

R

R

(2)

R

OE

L

CE

L

R/

W

L

I/O0L- I/O7L

(1,2) (1,2)

BUSY

L

A9L

A0L

NOTES:

1. IDT7130 (MASTER):
drain output and requires pullup
resistor of 270Ω.
IDT7140 (SLAVE):

2. Open drain output: requires pullup
resistor of 270Ω.

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

BUSY

BUSY

is open

is input.

INT

(2)

L

Address
Decoder

R/

CE
OE

L
L

W

L

10

I/O

Control

MEMORY

ARRAY

ARBITRATION

and

INTERRUPT

LOGIC

I/O

Control

Address
Decoder

10

CE

R

OE

R

R/

W

R

MILITARY AND COMMERCIAL TEMPERATURE RANGES OCTOBER 1996

©1996 Integrated Device Technology, Inc. DSC-2689/7

For latest information contact IDT’s web site at www.idt.com or fax-on-demand at 408-492-8391.

6.01 1

IDT7130SA/LA AND IDT7140SA/LA

INDEX

IDT7130/40

PP64-1 & PN64-1

64-PIN STQFP

64-PIN TQFP
TOP VIEW

(3)

8

9
10
11
12
13
14
15
16

1

2

3

4

5

6

7

46
45
44
43
42
41
40
39
38
37
36
35
34

47

48

33

I/O

6R

N/C

A

0R

A

1R

A

2R

A

3R

A

4R

A

5R

A

6R

A

7R

A

8R

A

9R

I/O

7R

OE

R

N/C
N/C

I/O

2L

A

0L

OE

L

A

1L

A

2L

A

3L

A

4L

A

5L

A

6L

A

7L

A

8L

A

9L

I/O

0L

I/O

1L

N/C

N/C

2689 drw 05

17

18

19

20

32

31

30

29

28

27

26

25

24

23

22

21

49

50

51

52

63

62

61

605958

57

56

55

54

53

64

N/C

N/C

BUSY

R

INT

R

N/C

N/C

N/C

N/C

GND

N/C

N/C

GND

N/C

CE

L

R/

W

R

CE

R

V

CC

V

CC

R/

W

L

BUSY

L

INT

L

I/O

3L

I/O

4L

I/O

5L

I/O

6L

I/O

7L

I/O

0R

I/O

1R

I/O

2R

I/O

3R

I/O

4R

I/O

5R

HIGH-SPEED 1K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN CONFIGURATIONS

CE

L

R/

BUSY

INT

OE

I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND

148

W

L

2

L

3

L

4

L

5

A

0L

6

A

1L

7

A

2L

8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23

IDT7130/

IDT7140

P48-1

&

C48-2

DIP

TOP

VIEW

A

3L

A

4L

A

5L

A

6L

A

7L

A

8L

A

9L
0L
1L
2L
3L
4L
5L
6L
7L

24

(1,2)

(3)

47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

V

CC

CE

R

R/

W

R

BUSY

R

INT

R

OE

R

A

0R

A

1R

A

2R

A

3R

A

4R

A

5R

A

6R

A

7R

A

8R

A

9R

I/O

7R
6R

I/O
I/O

5R

I/O

4R

I/O

3R

I/O

2R

I/O

1R

I/O

0R

2689 drw 02

INDEX

I/O
I/O
I/O
I/O

L

L

0L

A

OE

N/C

8

A

1L

9

A

2L

10

A

3L

11

A

4L

12

A

5L

13

A

6L

14

A

7L

15

A

8L

16

A

9L

17

0L

18

1L

19

2L

20

3L

6L

5L

4L

I/O

I/O

I/O

L

W

INTLBUSY

R/

234567

1

IDT7130/40

J52-1

52-PIN PLCC
TOP VIEW

7L

N/C

I/O

GND

L

CE

0R

I/O

CC

V

(3)

1R

I/O

R

CE

2R

I/O

R

W

R/

3R

I/O

R

BUSYRINT

5R

4R

I/O

I/O

N/C

474849505152

46

OE

45
44
43
42
41
40
39
38
37
36
35
34

33323130292827262524232221

6R

I/O

R

A

0R

A

1R

A

2R

A

3R

A

4R

A

5R

A

6R

A

7R

A

8R

A

9R

N/C
I/O

7R

2689 drw 04

L

INDEX

L

A0L

OE

INT

W

BUSY

R/

L

CE

L

L

VCC

R

CE

R

W

R/

65432148 47 46 45 44 43

7

A1L
A2L

8

A3L

9
A4L
A5L
A6L
A7L
A8L
A9L

I/O0L
I/O1L
I/O2L

NOTES:

1. All Vcc pins must be connected to the power supply.

2. All GND pins must be connected to the ground supply.

3. This text does not indicate orientation of the actual part-marking.

10

11

12

13

14

15

16

17

18

19 20 21 22 23 25 26 27 28 29 3024

I/O3L

48-PIN LCC/ FLATPACK

I/O5L

I/O4L

IDT7130/40

L48-1

&

F48-1

TOP VIEW

I/O7L

I/O6L

GND

I/O0R

(3)

I/O1R

I/O2R

R

R

BUSY

INT

I/O4R

I/O3R

R

OE

42
41
40
39
38
37
36
35
34
33
32
31

I/O5R

A0R

A1R
A2R

A3R

A4R
A5R

A6R
A7R
A8R

A9R

I/O7R

I/O6R

2689 drw 03

6.01 2

IDT7130SA/LA AND IDT7140SA/LA
HIGH-SPEED 1K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS MILITARY AND COMMERCIAL TEMPERATURE RANGES

ABSOLUTE MAXIMUM RATINGS

(1)

Symbol Rating Commercial Military Unit

(2)

V

TERM

Terminal Voltage –0.5 to +7.0 –0.5 to +7.0 V
with Respect to
GND

A Operating 0 to +70 –55 to +125 °C

T

Temperature

BIAS Temperature –55 to +125 –65 to +135 °C

T

Under Bias

STG Storage –55 to +125 –65 to +150 °C

T

Temperature

I

OUT DC Output 50 50 mA

RECOMMENDED
DC OPERATING CONDITIONS

Symbol Parameter Min. Typ. Max. Unit

V

CC Supply Voltage 4.5 5.0 5.5 V

GND Supply Voltage 0 0 0 V
V

IH Input High Voltage 2.2 — 6.0

V

IL Input Low Voltage –0.5 — 0.8 V

NOTES:

1. V

IL (min.) > -1.5V for pulse width less than 10ns.

2. V

TERM must not exceed Vcc + 0.5V.

(1)

(2)

2689 tbl 02

V

Current

NOTES:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of the specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.

2. VTERM must not exceed Vcc + 0.5 for more than 25% of the cycle time
or 10ns maximum, and is limited to
+ 0.5V.

< 20mA for the period of VTERM > Vcc

2689 tbl 01

RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE

Ambient

Grade Temperature GND V

Military –55 °C to +125°C 0V 5.0V ± 10%
Commercial 0°C to +70°C 0V 5.0V ± 10%

CC

2689 tbl 03

DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE

Symbol Parameter Test Conditions Min. Max. Max. Max. Unit

Ll| Input Leakage VCC = 5.5V, — 10 — 5 µA

|l

|lLO| Output Leakage VCC = 5.5V, — 10 — 5 µA

OL Output Low Voltage lOL = 4mA — 0.4 — 0.4 V

V

OL Open Drain Output lOL = 16mA — 0.5 — 0.5 V

V

OH Output High Voltage lOH = -4mA 2.4 — 2.4 — V

V

NOTE: 2689 tbl 04

1. At Vcc < 2.0V leakages are undefined.

(1)

Current

(1)

Current

(l/O0-l/O

7) lOL= 16mA

Low Voltage (

BUSY, INT

VIN = 0V to VCCIN = GND to VCC

CE

= VIH, VOUT = 0V to VCC

)

C

(VCC = 5.0V ± 10%)

7130SA 7130LA
7140SA 7140LA

CAPACITANCE

(TA = +25°C, f = 1.0MHz) TQFP ONLY

Symbol Parameter Conditions

C

IN Input Capacitance VIN = 3dV 9 pF
OUT Output Capacitance VIN = 3dV 10 pF

C

NOTES:

1. This parameter is determined by device characterization but is not
production tested.

2. 3dv references the interpolated capacitance when the input and

output signals switch from 0V to 3V or from 3V to 0V.

3. 11pF max. for other packages.

(1)

(3)

(2)

Max. Unit

2689 tbl 05

6.01 3

IDT7130SA/LA AND IDT7140SA/LA
HIGH-SPEED 1K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS MILITARY AND COMMERCIAL TEMPERATURE RANGES

DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE

7130X20

(2)

7130X25
7140X25

(1,6)

(VCC = 5.0V ± 10%)

(3)

7130X35 7130X55 7130X100

(3)

7140X35 7140X55 7140X100

Symbol Parameter Test Conditions Version Typ. Max. Typ. Max. Typ. Max. Typ.Max. Typ. Max. Unit

CC Dynamic Operating

I

CE

L and CER = VIL, MIL. SA — — 110 280 110 230 110 190 110 190 mA

Current (Both Ports Outputs open, LA — — 110 220 110 170 110 140 110 140
Active) f = f

MAX

COM'L. SA 110 250 110 220 110 165 110 155 110 155

(4)

LA 110 200 110 170 110 120 110 110 110 110

SB1 Standby Current

I

(Both Ports - TTL f = f

CE

L and CER = VIH, MIL. SA — — 30 80 25 80 20 65 20 65 mA

(4)

MAX

LA — — 30 60 25 60 20 45 20 45

Level Inputs) COM'L. SA 30 65 30 65 25 65 20 65 20 55

LA 30 45 30 45 25 45 20 35 20 35

I

SB2 Standby Current

(One Port - TTL

CE

"A" = VIL and MIL. SA — — 65 160 50 150 40 125 40 125 mA

"B" = VIH

CE

(7)

LA — — 65 125 50 115 40 90 40 90

Level Inputs) Active Port Outputs COM'L. SA 65 165 65 150 50 125 40 110 40 110

(4)

Open, f = f

I

SB3 Full Standby Current

(Both Ports - All
CMOS Level Inputs V

SB4 Full Standby Current

I

(One Port - All
CMOS Level Inputs) V

CE

L and MIL. SA — — 1.0 30 1.0 30 1.0 30 1.0 30 mA

CE

R > VCC -0.2V, LA — — 0.2 10 0.2 10 0.2 10 0.2 10

IN > VCC -0.2V or COM'L. SA 1.0 15 1.0 15 1.0 15 1.0 15 1.0 15

V

IN < 0.2V,f = 0

CE

"A" < 0.2V and MIL. SA — — 60 155 45 145 40 110 40 110 mA
"B" > VCC -0.2V

CE

IN > VCC -0.2V or COM'L. SA 60 155 60 145 45 110 40 100 40 95
IN < 0.2V, LA 60 115 60 105 45 85 40 70 40 70

V
Active Port Outputs
Open, f = f

NOTES: 2689 tbl 06

1. 'X' in part numbers indicates power rating (SA or LA).

2. Com'l Only, 0°C to +70°C temperature range. PLCC and TQFP packages.

3. Not available in DIP packages.

4. At f = f

5. f = 0 means no address or control lines change. Applies only to inputs at CMOS level standby.

6. Vcc = 5V, T

7. Port "A" may be either left or right port. Port "B" is opposite from port "A".

Max, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, and using “AC TEST CONDITIONS”

of input levels of GND to 3V.

A=+25°C for Typ and is not production tested. Vcc DC = 100 mA (Typ.)

MAX

MAX

(5)

(7)

(4)

LA 65 125 65 115 50 90 40 75 40 75

LA 0.2 5 0.2 5 0.2 4 0.2 4 0.2 4

LA — — 60 115 45 105 40 85 40 80

DATA RETENTION CHARACTERISTICS (LA Version Only)

Symbol Parameter Min. Typ.

DR VCC for Data Retention 2.0 — — V

V
I

CCDR Data Retention Current — 100 4000 µA

VCC = 2.0V,

(3)

CDR Chip Deselect to Data 0 — — ns

t

Retention Time

(3)

R Operation Recovery tRC ——ns

t

V

IN > VCC -0.2V or VIN < 0.2V

Test Conditions

CE

> VCC -0.2V

Mil.
Com’l.

lDT7130LA/IDT7140LA

— 100 1500 µA

(2)

Time

NOTES:

1. V

CC = 2V, TA = +25°C, and is not production tested.

2. t

RC = Read Cycle Time

3. This parameter is guaranteed but not production tested.

6.01 4

(1)

Max. Unit

2689 tbl 07

IDT7130SA/LA AND IDT7140SA/LA
HIGH-SPEED 1K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS MILITARY AND COMMERCIAL TEMPERATURE RANGES

DATA RETENTION WAVEFORM

DATA RETENTION MODE

V

CC

CE

4.5V 4.5V

t

CDR

V

IH

V

DR

≥

2.0V
t

R

V

DR

V

IH

2692 drw 06

AC TEST CONDITIONS

Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load

GND to 3.0V

5ns

1.5V

1.5V

Figures 1, 2, and 3

DATA

BUSY

OUT

775Ω

or

5V

1250Ω

30pF*

Figure 1. Output Test Load

5V

270Ω

INT

2689 tbl 08

(*100pF for 55 and
100ns versions)

DATA

5V

OUT

775Ω

Figure 2. Output Test Load

(for t

HZ, tLZ, tWZ, and tOW)

* including scope and jig

1250Ω

5pF*

30pF*

Figure 3.

AC Output Test Load

BUSYBUSY

BUSY

BUSYBUSY

and

*

100pF for 55 and 100ns versions

INTINT

INT

INTINT

6.01 5

2689 drw 07

IDT7130SA/LA AND IDT7140SA/LA
HIGH-SPEED 1K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS MILITARY AND COMMERCIAL TEMPERATURE RANGES

AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE

7130X20

Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit

Read Cycle

RC Read Cycle Time 20 — 25 — 35 — 55 — 100 — ns

t
t

AA Address Access Time — 20 — 25 — 35 — 55 — 100 ns
ACE Chip Enable Access Time — 20 — 25 — 35 — 55 — 100 ns

t
t

AOE Output Enable Access Time 11 — 12 — 20 — 25 — 40 ns
OH Output Hold From Address Change 3 — 3 — 3 — 3 — 10 — ns

t

LZ Output Low-Z Time

t
t

HZ Output High-Z Time
PU Chip Enable to Power Up Time

t
t

PD Chip Disable to Power Down Time

NOTES: 2689 tbl 09

1. Transition is measured ±500mV from Low or High-impedance voltage Output Test Load (Figure 2).

2. Com'l Only, 0°C to +70°C temperature range. PLCC and TQFP package.

3. “X” in part numbers indicates power rating (SA or LA).

4. This parameter is guaranteed by device characterization, but is not production tested.

5. Not available in DIP packages.

(1,4)

(1,4)

(4)

— 10 — 10 — 15 — 25 — 40 ns

(4)

— 20 — 25 — 35 — 50 — 50 ns

(2)

7130X25
7140X25

0— 0 — 0 — 5 — 5 —ns

0— 0—0 — 0 — 0 —ns

(3)

(5)

7130X35 7130X55 7130X100

(5)

7140X35 7140X55 7140X100

TIMING WAVEFORM OF READ CYCLE NO. 1, EITHER SIDE

t

RC

(1)

ADDRESS

t

AA

t

OH

OUT

DATA

BUSY

OUT

NOTES:

1. R/W = V

2. t

BDD delay is required only in the case where the opposite port is completing a write operation to the same the

address location. For simultaneous read operations,

3. Start of valid data depends on which timing becomes effective last t

PREVIOUS DATA VALID

(2,3)

t

BDD

IH,

CE

= VIL, and is OE = VIL. Address is valid prior to the coincidental with CE transition Low.

BUSY

has no relationship to valid output data.

AOE, tACE, tAA, and tBDD.

DATA VALID

t

OH

2689 drw 08

6.01 6

IDT7130SA/LA AND IDT7140SA/LA
HIGH-SPEED 1K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS MILITARY AND COMMERCIAL TEMPERATURE RANGES

TIMING WAVEFORM OF READ CYCLE NO. 2, EITHER SIDE

t

ACE

(4)

t

AOE

(1)

t

LZ

DATA

OUT

I

CC

CURRENT

I

SS

t

PU

50%

(1)

t

LZ

(3)

t

HZ

VALID DATA

t

PD

(2)

(2)

t

HZ

(4)

50%

2689 drw 09

NOTES:

1. Timing depends on which signal is asserted last,

2. Timing depends on which signal is deaserted first,

3. R/W = V

IH and the address is valid prior to or coincidental with

4. Start of valid data depends on which timing becomes effective last t

OE or CE

OE or CE

.

.

CE

transition Low.

AOE, tACE, tAA, and tBDD.

AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE

7130X20

(2)

7130X25
7140X25

Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit

Write Cycle

WC Write Cycle Time

t
t

EW Chip Enable to End-of-Write 15 — 20 — 30 — 40 — 90 — ns
AW Address Valid to End-of-Write 15 — 20 — 30 — 40 — 90 — ns

t
t

AS Address Set-up Time 0 — 0 — 0 — 0 — 0 — ns
WP Write Pulse Width

t
t

WR Write Recovery Time 0 — 0 — 0 — 0 — 0 — ns
DW Data Valid to End-of-Write 10 — 12 — 15 — 20 — 40 — ns

t
t

HZ Output High-Z Time
DH Data Hold Time 0 — 0 — 0 — 0 — 0 — ns

t
t

WZ Write Enabled to Output in High-Z
OW Output Active From End-of-Write

t

NOTES: 2689 tbl 10

1. Transition is measured ±500mV from Low or High-impedance voltage with Output Test Load (Figure 2). This parameter is guaranteed by
device characterization but is not production tested.

2. 0°C to +70°C temperature range only, PLCC and TQFP packages.

3. For MASTER/SLAVE combination, t

4. If OE is low during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off
data to be placed on the bus for the required t
write pulse can be as short as the specified t

5. “X” in part numbers indicates power rating (SA or LA).

6. Not available in DIP packages.

(3)

(4)

(1)

WC = tBAA + tWP, since R/

DW. If

WP.

20 — 25 — 35 — 55 — 100 — ns

15 — 15 — 25 — 30 — 55 — ns

—10 —10 —15 —25 —40 ns

(1)

(1)

—10 —10 —15 —25 —40 ns

0— 0— 0— 0— 0— ns

W

= VIL must occur after tBAA.

OE

is High during a R/W controlled write cycle, this requirement does not apply and the

(6)
(6)

(5)

7130X35 7130X55 7130X100
7140X35 7140X55 7140X100

6.01 7

IDT7130SA/LA AND IDT7140SA/LA
HIGH-SPEED 1K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS MILITARY AND COMMERCIAL TEMPERATURE RANGES

TIMING WAVEFORM OF WRITE CYCLE NO. 1, (R/

tWC

ADDRESS

OE

tAW

CE

tWP

(2)

DATA

DATAIN

R/

OUT

W

(6)

tAS

(7)

tWZ

(4) (4)

WW

W

CONTROLLED TIMING)

WW

(3)

tWR

tDW

tDH

tOW

(1,5,8)

tHZ

(7)

(7)

tHZ

2689 drw 10

TIMING WAVEFORM OF WRITE CYCLE NO. 2, (

t

WC

CECE

CE

CONTROLLED TIMING)

CECE

(1,5)

ADDRESS

t

AW

CE

(6)

t

AS

R/

W

DATA

IN

NOTES:

1. R/W or CE must be High during all address transitions.

2. A write occurs during the overlap (t

3. tWR is measured from the earlier of CE or R/W going High to the end of the write cycle.

4. During this period, the l/O pins are in the output state and input signals must not be applied.

5. If the CE Low transition occurs simultaneously with or after the R/W Low transition, the outputs remain in the High-impedance state.

6. Timing depends on which enable signal (CE or R/W) is asserted last.

7. This parameter is determined be device characterization, but is not production tested. Transition is measured +/- 500mV from steady state
with the Output Test Load (Figure 2).

8. If OE is low during a R/W controlled write cycle, the write pulse width must be the larger of t
and data to be placed on the bus for the required t
the write pulse can be as short as the specified t

EW or tWP) of

CE

= VIL and R/W = VIL.

DW. If

OE

WP.

is High during a R/W controlled write cycle, this requirement does not apply and

t

EW

(2)

t

DW

WP or (tWZ + tDW) to allow the I/O drivers to turn off

t

WR

(3)

t

DH

2689 drw 11

6.01 8

IDT7130SA/LA AND IDT7140SA/LA
HIGH-SPEED 1K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS MILITARY AND COMMERCIAL TEMPERATURE RANGES

AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE

7130X20

Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
Busy Timing (For Master lDT7130 Only)

BAA

t
t

BDA
BAC

t
t

BDC

t

WH Write Hold After
WDD Write Pulse to Data Delay

t
t

DDD Write Data Valid to Read Data Delay
APS Arbitration Priority Set-up Time

t
t

BDD

BUSY

Access Time from Address — 20 — 20 — 20 — 30 — 50 ns

BUSY

Disable Time from Address — 20 — 20 — 20 — 30 — 50 ns

BUSY

Access Time from Chip Enable — 20 — 20 — 20 — 30 — 50 ns

BUSY

Disable Time from Chip Enable — 20 — 20 — 20 — 30 — 50 ns

BUSY

Disable to Valid Data

BUSY

(6)

(2)

(2)

(3)

(4)

12 — 15 — 20 — 20 — 20 — ns

Busy Timing (For Slave IDT7140 Only)e 5—5—5—5—5

WB Write to

t
t

WH Write Hold After
WDD Write Pulse to Data Delay

t
t

DDD Write Data Valid to Read Data Delay

NOTES: 2689 tbl 11

1. Com'l Only, 0°C to +70°C temperature range. PLCC and TQFP packages only.

2. Port-to-port delay through RAM cells from the writing port to the reading port, refer to “Timing Waveform of Write with Port-to-Port Read and

3. To ensure that the earlier of the two ports wins.

4. t

BDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual), or tDDD – tDW (actual).

5. To ensure that a write cycle is inhibited on port 'B' during contention on port 'A'.

6. To ensure that a write cycle is completed on port 'B' after contention on port 'A'.

7. “X” in part numbers indicates power rating (SA or LA).

8. Not available in DIP packages.

BUSY

Input

BUSY

(5)

(6)

(2)

(2)

12 — 15 — 20 — 20 — 20 — ns

(1)

7130X25
7140X25

— 40 — 50 — 60 — 80 — 120 ns
— 30 — 35 — 35 — 55 — 100 ns

5— 5— 5 — 5—5 — ns

— 25 — 35 — 35 — 50 — 65 ns

0— 0— 0 — 0—0 — ns

— 40 — 50 — 60 — 80 — 120 ns
— 30 — 35 — 35 — 55 — 100 ns

(7)8

(9)
(9)

M824S258M824S30 7132158M824S4

7130X35 7130X55 7130X100
7140X35 7140X55 7140X100

BUSY

."

t

DDD

(2,3,4)

t

DH

t

BDD

t

BDA

t

WDD

BUSYBUSY

BUSY

BUSYBUSY

TIMING WAVEFORM OF WRITE WITH PORT-TO-PORT READ AND

t

WC

ADDR

’A’

R/

W

’A’

DATA

IN’A’

(1)

t

APS

ADDR

’B’

BUSY

’B’

DATA

OUT’B’

NOTES:

1. To ensure that the earlier of the two ports wins.

L = CER = VIL.

2.

CE

3. OE = VIL for the reading port.

4. All timing is the same for the left and right ports. Port 'A' may be either the left or right port. Port "B" is opposite from port "A".

tBDD is ignored for slave (IDT7140).

MATCH

t

WP

t

DW

VALID

MATCH

VALID

2689 drw 12

6.01 9

IDT7130SA/LA AND IDT7140SA/LA
HIGH-SPEED 1K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS MILITARY AND COMMERCIAL TEMPERATURE RANGES

TIMING WAVEFORM OF WRITE WITH

R/

W

'A'

BUSY

'B'

R/

W

'B'

NOTES:

1. t

WH must be met for both BUSY Input (IDT7140, slave) or Output (IDT7130 master).

2. BUSY is asserted on port 'B' blocking R/W'B', until BUSY'B' goes High.

3. All timing is the same for the left and right ports. Port 'A' may be either the left or right
port. Port "B" is opposite from port "A".

BUSYBUSY

BUSY

BUSYBUSY

t

WB

(3)

t

WP

t

WH

(2)

TIMING WAVEFORM OF BUSY ARBITRATION CONTROLLED BY

'A'

ADDR

AND

'B'

ADDRESSES MATCH

(1)

CECE

CE

CECE

2689 drw 13

TIMING

(1)

CE

'B'

(2)

t

APS

CE

'A'

t

BUSY

BAC

'A'

t

BDC

2689 drw 14

TIMING WAVEFORM OF BUSY ARBITRATION CONTROLLED BY ADDRESS MATCH TIMING

t

RC OR tWC

ADDR

ADDR

BUSY

'A'

(2)

t

APS

'B'

'B'

ADDRESSES MATCH

t

BAA

ADDRESSES DO NOT MATCH

t

BDA

2689 drw 15

(1)

NOTES:

1. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.

2. If t

APS is not satisified, the

asserted (7130 only).

BUSY

will be asserted on one side or the other, but there is no guarantee on which side

6.01 10

BUSY

will be

IDT7130SA/LA AND IDT7140SA/LA
HIGH-SPEED 1K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS MILITARY AND COMMERCIAL TEMPERATURE RANGES

AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE

7130X20

(1)

7130X25
7140X25

Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
Interrupt Timing

AS Address Set-up Time 0 — 0 — 0 — 0 — 0 — ns

t
t

WR Write Recovery Time 0 — 0 — 0 — 0 — 0 — ns
INS Interrupt Set Time — 20 — 25 — 25 — 45 — 60 ns

t
t

INR Interrupt Reset Time — 20 — 25 — 25 — 45 — 60 ns

NOTES:

1. 0°C to +70°C temperature range only, PLCC and TQFP packages.

2. “X” in part numbers indicates power rating (SA or LA).

3. Not available in DIP packages .

(3)
(3)

7130X35 7130X55 7130X100
7140X35 7140X55 7140X100

(2)

8M824S25 8M824S308M824S35

2689 tbl 12

TIMING WAVEFORM OF INTERRUPT MODE

INTINT

INT

SET:

INTINT

t

WC

ADDR

'A'

INTERRUPT ADDRESS

(3)

t

AS

(2)

(4)

t

WR

R/

W

'A'

(3)

t

INS

INT

'B'

INTINT

INT

CLEAR:

INTINT

t

RC

ADDR

'B'

OE

'B'

INT

'B'

NOTES:.

1. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.

2. See Interrupt Truth Table.

3. Timing depends on which enable signal (CE or R/W) is asserted last.

4. Timing depends on which enable signal (CE or R/W) is de-asserted first.

INTERRUPT CLEAR ADDRESS

(3)

t

AS

(3)

t

INR

2689 drw 16

2689 drw 17

6.01 11

IDT7130SA/LA AND IDT7140SA/LA
HIGH-SPEED 1K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS MILITARY AND COMMERCIAL TEMPERATURE RANGES

TRUTH TABLES
TABLE I — NON-CONTENTION

READ/WRITE CONTROL

Left or Right Port

WW

CECE

CE

CECE

OEOE

OE

OEOE

R/

W

WW

X H X Z Port Disabled and in Power-

XHX Z

L L X DATAIN Data on Port Written Into Memory
H L L DATAOUT Data in Memory Output on Port
H L H Z High Impedance Outputs

NOTES: 2689 tbl 13

1. A0L – A10L ≠ A0R – A10R.

2. If

BUSY

3. If

4. 'H' = V

= L, data is not written.

BUSY

= L, data may not be valid, see t

IH, 'L' = VIL, 'X' = DON’T CARE, 'Z' = HIGH IMPEDANCE

(1)

D0–7 Function

TABLE II — INTERRUPT FLAG

Left Port Right Port

WW

R/

CECE

W

L

CE

WW

CECE

LLX 3FF XXXX X L
X X X X X X L L 3FF H
XXX X L
X L L 3FE H

NOTES: 2689 tbl 14

1. Assumes

2. If

3. If

4. 'H' = HIGH,' L' = LOW,' X' = DON’T CARE

BUSY

BUSY

L = VIL, then No Change.

BUSY

R = VIL, then No Change.

OEOE

L

L =

OE

OEOE

BUSY

L A9L – A0L

R = VIH

(4)

Down Mode, I

CE

R = CEL = VIH, Power-Down

Mode, I

SB2 or ISB4

SB1 or ISB3

WDD and tDDD timing.

(1,4)

INTINT

L R/

INT

INTINT

(3)
(2)

(2)

(3)

WW

CECE

W

R

CE

WW

CECE

L L X 3FE X Set Left

OEOE

R

R A9L – A0R

OE

OEOE

INTINT

R Function

INT

INTINT

(2)

(3)

Set Right
Reset Right

INT

X X X X X Reset Left

INT

INT

R Flag

INT

L Flag

L Flag

R Flag

TABLE III — ADDRESS BUSY ARBITRATION

Inputs Outputs

A

0L-A9L

CECE

CECE

L

CE

CECE

XX

HX

XH
LL

NOTES: 2689 tbl 15

1. Pins
inputs for IDT7140 (slave).
not push-pull outputs. On slaves the

2. 'L' if the inputs to the opposite port were stable prior to the address and
enable inputs of this port. 'H' if the inputs to the opposite port became
stable after the address and enable inputs of this port. If tAPS is not met,
either
not be low simultaneously.

3. Writes to the left port are internally ignored when
driving Low regardless of actual logic level on the pin. Writes to the right
port are internally ignored when
less of actual logic level on the pin.

R A0R-A9R

CE

CECE

BUSY

L and

BUSY

NO MATCH H H Normal

MATCH H H Normal
MATCH H H Normal
MATCH (2) (2) Write Inhibit

BUSY

R are both outputs for IDT7130 (master). Both are

BUSY

L or

BUSY

R = Low will result.

(1)

BUSYBUSY

L

BUSY

BUSYBUSY

X outputs on the IDT7130 are open drain,

BUSY

BUSY

BUSY

R outputs are driving Low regard-

(1)

BUSYBUSY

R

BUSY

BUSYBUSY

X input internally inhibits writes.

L and

BUSY

BUSY

Function

R outputs can
L outputs are

(3)

6.01 12

IDT7130SA/LA AND IDT7140SA/LA

2689 drw 18

MASTER
Dual Port
RAM

BUSY

(L)

BUSY

(R)

CE

MASTER
Dual Port
RAM

BUSY

(L)

BUSY

(R)

CE

SLAVE
Dual Port
RAM

BUSY

(L)

BUSY

(R)

CE

SLAVE
Dual Port
RAM

BUSY

(L)

BUSY

(R)

CE

BUSY

L

BUSY

R

DECODER

5V

5V

270Ω

270Ω

HIGH-SPEED 1K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS MILITARY AND COMMERCIAL TEMPERATURE RANGES

FUNCTIONAL DESCRIPTION

The IDT7130/IDT7140 provides two ports with separate con­trol, address and I/O pins that permit independent access for
reads or writes to any location in memory. The IDT7130/
IDT7140 has an automatic power down feature controlled by

CE

. The CE controls on-chip power down circuitry that permits
the respective port to go into a standby mode when not
selected (CE = VIH). When a port is enabled, access to the
entire memory array is permitted.

INTERRUPTS

If the user chooses to use the interrupt function, a memory
location (mail box or message center) is assigned to each
port. The left port interrupt flag (
right port writes to memory location 3FE (HEX), where a write
is defined as the CE = R/W = VIL per the Truth Table. The left
port clears the interrupt by access address location 3FE
access when

CE

R = OER = VIL, R/

the right port interrupt flag (
writes to memory location 3FF (HEX) and to clear the interrupt
flag (

INT

R), the right port must access the memory location

3FF. The message (8 bits) at 3FE or 3FF is user-defined,
since it is an addressable SRAM location. If the interrupt
function is not used, address locations 3FE and 3FF are not
used as mail boxes, but as part of the random access
memory. Refer to Table II for the interrupt operation.

INT

L) is asserted when the

W

is a "don't care". Likewise,

INT

R) is asserted when the left port

The Busy outputs on the IDT7130 RAM (Master) are open
drain type outputs and require open drain resistors to operate.
If these RAMs are being expanded in depth, then the Busy
indication for the resulting array does not require the use of an
external AND gate.

WIDTH EXPANSION WITH BUSY LOGIC
MASTER/SLAVE ARRAYS

When expanding an RAM array in width while using busy
logic, one master part is used to decide which side of the RAM
array will receive a busy indication, and to output that indica­tion. Any number of slaves to be addressed in the same
address range as the master, use the busy signal as a write
inhibit signal. Thus on the IDT7130/IDT7140 RAMs the Busy
pin is an output if the part is Master (IDT7130), and the Busy
pin is an input if the part is a Slave (IDT7140) as shown in
Figure 4.

BUSY LOGIC

Busy Logic provides a hardware indication that both ports of
the RAM have accessed the same location at the same time.
It also allows one of the two accesses to proceed and signals
the other side that the RAM is “Busy”. The Busy pin can then
be used to stall the access until the operation on the other side
is completed. If a write operation has been attempted from the
side that receives a busy indication, the write signal is gated
internally to prevent the write from proceeding.
The use of busy logic is not required or desirable for all
applications. In some cases it may be useful to logically OR
the busy outputs together and use any busy indication as an
interrupt source to flag the event of an illegal or illogical
operation. In slave mode the
write inhibit input pin. Normal operation can be programmed
by tying the

BUSY

pins High. If desired, unintended write
operations can be prevented to a port by tying the Busy pin for
that port Low.

BUSY

pin operates solely as a

Figure 4. Busy and chip enable routing for both width and depth

expansion with IDT7130 (Master) and IDT7140 (Slave) RAMs.

If two or more master parts were used when expanding in
width, a split decision could result with one master indicating
busy on one side of the array and another master indicating
busy on one other side of the array. This would inhibit the write
operations from one port for part of a word and inhibit the write
operations from the other port for the other part of the word.

The Busy arbitration, on a Master, is based on the chip enable
and address signals only. It ignores whether an access is a
read or write. In a master/slave array, both address and chip
enable must be valid long enough for a busy flag to be output
from the master before the actual write pulse can be initiated
with either the R/W signal or the byte enables. Failure to
observe this timing can result in a glitched internal write inhibit
signal and corrupted data in the slave.

6.01 13

IDT7130SA/LA AND IDT7140SA/LA
HIGH-SPEED 1K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS MILITARY AND COMMERCIAL TEMPERATURE RANGES

ORDERING INFORMATION

XXXXIDT

Device Type

A 999 A A

Power Speed Package

Temperature

Process/

Range

Blank
B

P
C
J
L48
F
PF
TF

20
25
35
55
100

LA
SA

Commercial (0°C to +70°C)
Military (–55°C to +125°C)
Compliant to MIL-STD-883, Class B

48-pin Plastic DIP (P48-1)
48-pin Sidebraze DIP (C48-2)
52-pin PLCC (J52-1)
48-pin LCC (L48-1)
48-pin Ceramic Flatpack (F48-1)
64-pin TQFP (PN64-1)
64-pin STQFP (PP64-1)

Commercial PLCC and TQFP Only
LCC, PLCC, and TQFP Only

Speed in nanoseconds

Low Power
Standard Power

7130
7140

8K (1K x 8-Bit) MASTER Dual-Port RAM
8K (1K x 8-Bit) SLAVE Dual-Port RAM

2689 drw 19

6.01 14