Datasheet IDT71342SA35PF, IDT71342SA45J, IDT71342SA45PF, IDT71342SA55J, IDT71342SA55PF Datasheet (Integrated Device Technology Inc)

Integrated Device Technology, Inc.

HIGH-SPEED
4K x 8 DUAL-PORT
STATIC RAM WITH SEMAPHORE

IDT71342SA/LA

FEATURES:

• High-speed access
— Commercial: 20/25/35/45/55/70ns (max.)

• Low-power operation
— IDT71342SA

Active: 500mW (typ.)
Standby: 5mW (typ.)

— IDT71342LA

Active: 500mW (typ.)
Standby: 1mW (typ.)

• Fully asynchronous operation from either port

• Full on-chip hardware support of semaphore signalling
between ports

• Battery backup operation—2V data retention

• TTL-compatible; single 5V (±10%) power supply

• Available in plastic packages

• Industrial temperature range (–40°C to +85°C) is avail-

able, tested to military electrical specifications

FUNCTIONAL BLOCK DIAGRAM

R/

W

L

CE

L

DESCRIPTION:

The IDT71342 is an extremely high-speed 4K x 8 Dual-Port
Static RAM with full on-chip hardware support of semaphore
signalling between the two ports.

The IDT71342 provides two independent ports with separate
control, address, and I/O pins that permit independent,
asynchronous access for reads or writes to any location in
memory. To assist in arbitrating between ports, a fully
independent semaphore logic block is provided. This block
contains unassigned flags which can be accessed by either
side; however, only one side can control the flag at any time.
An automatic power down feature, controlled by CE and
permits the on-chip circuitry of each port to enter a very low
standby power mode (both CE and

SEM

High).

Fabricated using IDT’s CMOS high-performance
technology, this device typically operates on only 500mW of
power. Low-power (LA) versions offer battery backup data
retention capability, with each port typically consuming 200µW
from a 2V battery. The device is packaged in either a 64-pin
TQFP, thin quad plastic flatpack, or a 52-pin PLCC.

R/

W

R

CE

R

SEM

,

OE

I/O

R

0R

- I/O

7R

OE

I/O0L- I/O

7L

L

COLUMN

I/O

COLUMN

I/O

MEMORY

ARRAY

SEMAPHORE

LOGIC

SEM

SEM

L

LEFT SIDE

A0L- A

11L

ADDRESS

DECODE

LOGIC

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

RIGHT SIDE

ADDRESS

DECODE

LOGIC

R

A0R- A

11R

2721 drw 01

COMMERCIAL TEMPERATURE RANGE OCTOBER 1996

©1996 Integrated Device Technology, Inc. DSC-2721/4

For latest information contact IDT’s web site at www.idt.com or fax-on-demand at 408-492-8391.

6.05

1

IDT71342SA/LA
HIGH-SPEED 4K x 8 DUAL-PORT STATIC RAM WITH SEMAPHORE COMMERCIAL TEMPERATURE RANGE

PIN CONFIGURATIONS

L

INDEX

I/O
I/O
I/O
I/O

INDEX

OE

A

0L

A

1L

A

2L

A

3L

A

4L

A

5L

A

6L

N/C

A

7L

A

8L

A

9L

N/C

I/O

0L

I/O

1L

I/O

2L

0L

A

8

A

1L

9

A

2L

10

A

3L

11

A

4L

12

A

5L

13

A

6L

14

A

7L

15

A

8L

16

A

9L

17

0L

18

1L

19

2L

20

3L

4L

I/O

N/C

64

1

L

2
3

4
5
6

7
8
9

10
11
12

13
14
15

16

171819

3L

I/O

11L

10L

OE

A

A

5L

7L

I/O

I/O6LI/O

L

10L

11L

SEM

A

A

N/C

636261605958575655

20

21

N/C

I/O4LI/O5LI/O6LI/O

(1,2)

L

L

L

W

CC

V

R/

CE

SEM

234567

1

IDT71342

J52-1

PLCC

TOP VIEW

N/C

GND

I/O0RI/O1RI/O

L

L

W

CC

CE

R/

V

N/C

71342

PN64-1

64-PIN TQFP

TOP VIEW

25

24

23

22

7L

N/C

N/C

GND

R

R

R

W

11R

SEM

I/O4RI/O5RI/O

11R

A

52

53

29

A

10R

A

51

30

N/C

474849505152

33323130292827262524232221

10R

A

46
45
44
43
42
41
40
39
38
37
36
35
34

6R

N/C

50

31

N/C

49

32

5R

R/

CE

(3)

2R

3R

I/O

R

R

R

W

CE

R/

SEM

54

(3)

28

27

26

I/O0RI/O1RI/O2RI/O3RI/O4RI/O

OE

A
A
A
A
A
A
A
A
A
A
N/C
I/O

2721 drw 02

48
47

46
45

44
43

42
41
40

39
38
37

36
35
34
33

2721 drw 03

NOTES:

1. All Vcc pins must be connected to the power supply.

2. All GND pins must be connected to the ground supply.

3. This text does not indicate orientation of the actual part-marking.

ABSOLUTE MAXIMUM RATINGS

(1)

Symbol Rating Com’l. Mil. Unit

(2)

V

TERM

Terminal Voltage –0.5 to +7.0 –0.5 to +7.0 V
with Respect
to Ground

R
0R
1R
2R
3R
4R
5R
6R
7R
8R
9R

7R

OE

R

A

0R

A

1R

A

2R

A

3R

A

4R

A

5R

A

6R

N/C
A

7R

A

8R

A

9R

N/C
N/C
I/O

7R

I/O

6R

T

A Operating 0 to +70 –55 to +125 °C

Temperature

T

BIAS Temperature –55 to +125 –65 to +135 °C

Under Bias

STG Storage –55 to +125 –65 to +150 °C

T

Temperature

(3)

P

T

Power Dissipation 1.5 1.5 W

OUT DC Output Current 50 50 mA

I

NOTES: 2721 tbl 01

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.

2. V

TERM must not exceed Vcc + 0.5V for more than 25%of the cycle time or

10 ns maximum, and is limited to

< 20mA for the period of VTERM > Vcc

+0.5V.

CAPACITANCE

(1)

(TA = +25°C, f = 1.0MHz) TQFP Only

Symbol Parameter Conditions

C

IN Input Capacitance VIN = 3dV 9 pF
OUT Output Capacitance VOUT = 3dV 10 pF

C

NOTES: 2721 tbl 02

1. This parameter is determined by device characterization but is not
production tested.

2. 3dv references the interpolated capacitance when the input and output
signals switch from 0V to 3V and from 3V to 0V.

(2)

Max. Unit

RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE

Ambient

Grade Temperature GND V

CC

Commercial 0°C to +70°C 0V 5.0V ± 10%

2721 tbl 03

RECOMMENDED DC OPERATING CONDITIONS

Symbol Parameter Min. Typ. Max. Unit

CC Supply Voltage 4.5 5.0 5.5 V

V
GND Ground 0 0 0 V

IH Input High Voltage 2.2 — 6.0

V
V

IL Input Low Voltage –0.5

(1)

— 0.8 V

NOTES: 2721 tbl 04

1. VIL (min.) > -1.5V for pulse width less than 10ns.

TERM must not exceed Vcc + 0.5V.

2. V

(2)

V

6.05 2

IDT71342SA/LA
HIGH-SPEED 4K x 8 DUAL-PORT STATIC RAM WITH SEMAPHORE COMMERCIAL TEMPERATURE RANGE

DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE

Symbol Parameter Test Conditions Min. Max. Min. Max. Unit

LI| Input Leakage Current

|I
|I

LO| Output Leakage Current

OL Output Low Voltage IOL = 6mA — 0.4 — 0.4 V

V

OH Output High Voltage IOH = –4mA 2.4 — 2.4 — V

V

NOTE:

1. At Vcc < 2.0V input leakages are undefined.

(1)

VCC = 5.5V, VIN = 0V to VCC —10— 5µA

CE

= VIH, VOUT = 0V to VCC —10— 5µA

OL = 8mA — 0.5 — 0.5 V

I

(VCC = 5V ± 10%)

IDT71342SA IDT71342LA

2721 tbl 05

DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE

71342X20 71342X25 71342X35 71342X45 71342X55 71342X70

Symbol Parameter Test Conditions Version Typ.

ICC Dynamic Operating

IL COM’L. S — 280 — 280 — 260 — 240 — 240 — 240 mA

CE

= V

(2)

Max. Typ.

Current Outputs Open L — 240 — 240 — 220 — 200 — 200 — 200
(Both Ports Active)

ICC1 Dynamic Operating

SEM

= Don't Care

(3)

f = f

MAX

CE

= VIH COM’L. S — 280 — 200 — 185 — 170 — 170 — 170 mA

Current Outputs Open L — 240 — 170 — 155 — 140 — 140 — 140
(Semaphores
Both Sides) f = fMAX

ISB1 Standby Current

(Both Ports—TTL
Level Inputs) f = f

ISB2 Standby Current

(One Port—TTL
Level Inputs) Active Port Outputs

ISB3 Full Standby Current Both Ports

(Both Ports—All
CMOS Level Inputs) V

ISB4 Full Standby Current One Port

(One Port—All
CMOS Level Inputs) V

SEM

< VIL

(3)

CE

L and CER = VIH COM’L. S 25 80 25 80 25 75 25 70 25 70 25 70 mA

SEM

L =

SEM

R > VIH L 25 80 25 50 25 45 25 40 25 40 25 40

(3)

MAX

CE

"A"

= VIL and COM’L. S — 180 — 180 — 170 — 160 — 160 — 160 mA

CE

Open, f = f

CE

IN > VCC - 0.2V or
IN < 0.2V

V

SEM

V

CC - 0.2V, f = 0

CE

IN > VCC - 0.2V or
IN < 0.2V

V

SEM

CC - 0.2V

V
Active Port Outputs
Open, f = f

(5)

"B" = VIH

MAX

CE

R > VCC - 0.2V L 0.2 4.5 0.2 4.0 0.2 4.0 0.2 4.0 0.2 4.0 0.2 4.0

L =

SEM

CE

"B" > VCC - 0.2V L — 140 — 140 — 130 — 120 — 120 — 120

L =

SEM

MAX

L — 150 — 150 — 140 — 130 — 130 — 130

(3)

L and COM’L. S 1.0 15 1.0 15 1.0 15 1.0 15 1.0 15 1.0 15 mA

R >

(4)

"A" or COM’L. S — 170 — 170 — 150 — 150 — 150 — 150 mA

R >

(3)

NOTES:

1. “X” in part number indicates power rating (SA or LA).

CC = 5V, TA = +25°C for typical values, and parameters are not production tested.

2. V

MAX = 1/tRC = All inputs cycling at f = 1/tRC (except Output Enable).

3. f

4. f = 0 means no address or control lines change. Applies only to inputs at CMOS level standby I

5. Port "A" may be either left or right port. Port "B" is opposite from port "A".

(2)

Max. Typ.

(1)

(VCC = 5.0V ± 10%)

(2)

SB3.

Max. Typ.

(2)

Max. Typ.

(2)

Max. Typ.

(2)

Max. Unit

2721 tbl 06

6.05 3

IDT71342SA/LA

+5V

1250Ω

5pF *775Ω

DATA

OUT

2721 drw 06

HIGH-SPEED 4K x 8 DUAL-PORT STATIC RAM WITH SEMAPHORE COMMERCIAL TEMPERATURE RANGE

DATA RETENTION CHARACTERISTICS

(LA Version Only) VLC = 0.2V, VHC = VCC - 0.2V

Symbol Parameter Test Condition Min. Typ.

V

DR VCC for Data Retention — 2.0 — — V

CCDR Data Retention Current VCC = 2V,

I

SEM

(3)

tCDR

(3)

t

R

NOTES:

1. V

CC = 2V, TA = +25°C, and are not production tested.

RC = Read Cycle Time.

2. t

3. This parameter is guaranteed by device characterization, but is not production tested.

Chip Deselect to Data Retention Time VIN ≥ VHC or ≤ VLC 0——ns
Operation Recovery Time tRC

≥ V

CE

≥ VHC COM’L. — 100 1500 µA

HC

(2)

(1)

Max. Unit

——ns

2721 tbl 07

DATA RETENTION WAVEFORM

DATA RETENTION MODE

V

CC

t

CDR

CE

V

IH

AC TEST CONDITIONS

Input Pulse Levels GND to 3.0V
Input Rise/Fall Times 5ns
Input Timing Reference Levels 1.5V
Output Reference Levels 1.5V
Output Load Figures 1 and 2

+5V

1250Ω

OUT

DATA

30pF775Ω

2721 tbl 08

V

DR

≥ 2V

V

DR

4.5V4.5V
t

R

V

IH

2721 drw 04

Figure 1. AC Output Test Load

2721 drw 05

Figure 2. Output Test Load

6.05 4

LZ, tHZ, tWZ, tOW)

(for t

*Including scope and jig

IDT71342SA/LA
HIGH-SPEED 4K x 8 DUAL-PORT STATIC RAM WITH SEMAPHORE COMMERCIAL TEMPERATURE RANGE

AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE

71342X20 71342X25 71342X35

Symbol Parameter Min. Max. Min. Max. Min. Max. Unit

READ CYCLE

RC Read Cycle Time 20 — 25 — 35 — ns

t

AA Address Access Time — 20 — 25 — 35 ns

t

(1, 2)

(1, 2)

(3)

OE

(4)

or

—20—25—35ns

0—0—0—ns

—15—15—20ns

(2)

(2)

SEM

)——10—15—ns

0—0—0—ns

—50—50—50ns

—40—50—60ns

(4)

—30—30—35ns

ACE Chip Enable Access Time

t
t

AOE Output Enable Access Time — 15 — 15 — 20 ns

OH Output Hold from Address Change 0 — 0 — 0 — ns

t

t

LZ Output Low-Z Time
HZ Output High-Z Time

t

PU Chip Enable to Power Up Time

t

PD Chip Disable to Power Down Time

t

SOP SEM Flag Update Pulse (

t

WDD Write Pulse to Data Delay

t

DDD Write Data Valid to Read Data Delay

t

t

SAA Semaphore Address Access Time — — — 25 — 35 ns

(4)

2721 tbl 09

AC ELECTRICAL CHARACTERISTICS OVER THE

(4)

OPERATING TEMPERATURE AND SUPPLY VOLTAGE

71342X45 71342X55 71342X70

Symbol Parameter Min. Max. Min. Max. Min. Max. Unit

READ CYCLE

RC Read Cycle Time 45 — 55 — 70 — ns

t

AA Address Access Time — 45 — 55 — 70 ns

t

(1, 2)

(1, 2)

(3)

OE

(4)

or

—45 —55—70ns

5— 5—5—ns

—20 —25—30ns

(2)

(2)

SEM

)15—20—20—ns

0— 0—0—ns

—50 —50—50ns

—70 —80—90ns

(4)

—45 —55—70ns

SEM

t

ACE Chip Enable Access Time

t

AOE Output Enable Access Time — 25 — 30 — 40 ns

OH Output Hold from Address Change 0 — 0 — 0 — ns

t

t

LZ Output Low-Z Time
HZ Output High-Z Time

t

PU Chip Enable to Power Up Time

t

PD Chip Disable to Power Down Time

t

SOP SEM Flag Update Pulse (

t

WDD Write Pulse to Data Delay

t

DDD Write Data Valid to Read Data Delay

t

t

SAA Semaphore Address Access Time — 45 — 55 — 70 ns

NOTES:

1. Transition is measured ±500mV from Low or High-impedance voltage with the Ouput Test Load (Figure 2).

2. This parameter is guaranteed by device characterization, but is not production tested.

3. To access RAM, CE = V

4. “X” in part number indicates power rating (SA or LA).

IL,

SEM

= VIH. To access semaphore, CE = VIH, and

(CONT'D)

2721 tbl 10

= VIL.

6.05 5

IDT71342SA/LA
HIGH-SPEED 4K x 8 DUAL-PORT STATIC RAM WITH SEMAPHORE COMMERCIAL TEMPERATURE RANGE

TIMING WAVEFORM OF READ CYCLE NO. 1, EITHER SIDE

t

RC

ADDRESS

t

AA or tSAA

OH

DATA

OUT

t

PREVIOUS DATA VALID DATA VALID

TIMING WAVEFORM OF READ CYCLE NO. 2, EITHER SIDE

t

SOP

SEM

(5)

t

SOP

CE

or

OE

OUT

DATA

t

I

CC

PU

CURRENT

I

SB

NOTES:

1. Timing depends on which signal is asserted last, OE or CE.

2. Timing depends on which signal is de-asserted first, OE or CE.

3. R/W = V

4. Start of valid data depends on which timing becomes effective last; t

5. To access RAM, CE = VIL and

6. R/W = V

IH and address is valid prior to or coincident with

SEM

= VIH. To access semaphore, CE = VIH and

Address Access.

IH,

CE

= VIL, and OE = VIL. Address is valid prior to or coincident with CE transition Low.

t

ACE

(4)

t

AOE

(1)

t

LZ

(1)

t

LZ

CE

transition Low.

AOE, tACE, or tAA.

SEM

= VIL. tAA is for RAM Address Access and tSAA is for Semaphore

(1, 2, 4, 6)

(1, 3)

VALID DATA

t

OH

2721 drw 07

(2)

t

HZ

(2)

t

HZ

(4)

t

PD

50%50%

2721 drw 08

TIMING WAVEFORM OF WRITE WITH PORT-TO-PORT READ

t

WC

ADDR

"A"

(1)

R/

W

"A"

DATA

IN "A"

ADDR

"B"

DATA

OUT "B"

NOTES:

1. Write cycle parameters should be adhered to, in order to ensure proper writing.

L = CER = VIL. CE"B" = VIL.

2.

CE

3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".

MATCH

t

WP

t

DW

VALID

t

WDD

(1, 2)

MATCH

t

DDD

t

DH

VALID

2721 drw 09

6.05 6

IDT71342SA/LA
HIGH-SPEED 4K x 8 DUAL-PORT STATIC RAM WITH SEMAPHORE COMMERCIAL TEMPERATURE RANGE

AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE

71342X20 71342X25 71342X35

Symbol Parameter Min. Max. Min. Max. Min. Max. Unit

WRITE CYCLE

WC Write Cycle Time 20 — 25 — 35 — ns

t

EW Chip Enable to End-of-Write

t
t

AW Address Valid to End-of-Write 15 — 20 — 30 — ns

AS Address Set-up Time 0 — 0 — 0 — ns

t

WP Write Pulse Width 15 — 20 — 25 — ns

t

WR Write Recovery Time 0 — 0 — 0 — ns

t

DW Data Valid to End-of-Write 15 — 15 — 20 — ns

t

t

HZ Output High-Z Time

DH Data Hold Time

t

WZ Write Enabled to Output in High-Z

t

OW Output Active from End-of-Write

t

SWR SEM Flag Write to Read Time 10 — 10 — 10 — ns

t

SPS SEM Flag Contention Window 10 — 10 — 10 — ns

t

(1, 2)

(4)

(3)

(1, 2)

(1, 2, 4)

15 — 20 — 30 — ns

—15—15—20ns

0—0—3—ns

—15—15—20ns

3—3—3—ns

(5)

2721 tbl 11

AC ELECTRICAL CHARACTERISTICS OVER THE

(5)

OPERATING TEMPERATURE AND SUPPLY VOLTAGE

71342X45 71342X55 71342X70

Symbol Parameter Min. Max. Min. Max. Min. Max. Unit

WRITE CYCLE

WC Write Cycle Time 45 — 55 — 70 — ns

t
t

EW Chip Enable to End-of-Write

t

AW Address Valid to End-of-Write 40 — 50 — 60 — ns

AS Address Set-up Time 0 — 0 — 0 — ns

t

WP Write Pulse Width 40 — 50 — 60 — ns

t

WR Write Recovery Time 0 — 0 — 0 — ns

t

DW Data Valid to End-of-Write 20 — 25 — 30 — ns

t

t

HZ Output High-Z Time

DH Data Hold Time

t

WZ Write Enabled to Output in High-Z

t
t

OW Output Active from End-of-Write

SWR SEM Flag Write to Read Time 10 — 10 — 10 — ns

t

SPS SEM Flag Contention Window 10 — 10 — 10 — ns

t

NOTES:

1. Transition is measured ±500mV from Low or High-impedance voltage with Output Test Load (Figure 2).

2. This parameter is guaranteed by device characterization but is not production tested.

3. To access RAM, CE = V

4. The specification for t
over voltage and temperature, the actual t

5. “X” in part number indicates power rating (SA or LA).

IL and

DH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values will vary

(1, 2)

(4)

SEM

(3)

40 — 50 — 60 — ns

—20—25—30ns

3—3—3—ns

(1, 2)

(1, 2, 4)

= VIH. To access semaphore, CE = VIH and

DH will always be smaller than the actual tOW.

—20—25—30ns

3—3—3—ns

(CONT'D)

SEM

= VIL. Either condition must be valid for the entire tEW time.

2721 tbl 12

6.05 7

IDT71342SA/LA
HIGH-SPEED 4K x 8 DUAL-PORT STATIC RAM WITH SEMAPHORE COMMERCIAL TEMPERATURE RANGE

TIMING WAVEFORM OF WRITE CYCLE NO. 1, R/

t

WC

ADDRESS

(6)

t

AS

OE

t

AW

SEM

R/

W

OUT

IN

(9)

t

(7)

t

t

LZ

WZ

(4)

CE

or

DATA

DATA

WW

W

CONTROLLED TIMING

WW

(3)

t

WR

(2)

WP

t

OW

t

DW

(1, 5, 8)

(7)

t

HZ

(7)

t

HZ

(4)

t

DH

2721 drw 10

TIMING WAVEFORM OF WRITE CYCLE NO. 2,

CECE

CE

CONTROLLED TIMING

CECE

(1, 5)

tWC

ADDRESS

tAW

SEM

R/

W

(9)

tAS

(6)

tEW

(2)

tDW

tWR

(3)

tDH

CE

or

DATAIN

NOTES:

1. R/W or CE must be High during all address transitions.

2. A write occurs during the overlap (t

WR is measured from the earlier of

3. t

4. During this period, the I/O pins are in the output state, and input signals must not be applied.

5. If the CE Low transition occurs simultaneously with or after the R/W Low transition, the outputs remain in the High-impedance state.

6. Timing depends on which enable signal (CE or R/W) is asserted last.

7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured
Test Load (Figure 2).

8. If OE is Low during a R/W controlled write cycle, the write pulse width must be the larger of t
be placed on the bus for the required t
as short as the specified t

9. To access RAM, CE =V

IL

WP.

and

EW or tWP) of either

CE

or R/W going High to the end-of-write cycle.

DW. If

OE

SEM

= VIH. To access semaphore, CE = VIH and

CE

or

SEM

= VIL and R/W = VIL.

is High during an R/W controlled write cycle, this requirement does not apply and the write pulse can be

+ 500mV from steady state with the Output

WP or (tWZ + tDW) to allow the I/O drivers to turn off data to

SEM

= VIL. Either condition must be valid for the entire tEW time.

2721 drw 11

6.05 8

IDT71342SA/LA
HIGH-SPEED 4K x 8 DUAL-PORT STATIC RAM WITH SEMAPHORE COMMERCIAL TEMPERATURE RANGE

TIMING WAVEFORM OF SEMAPHORE READ AFTER WRITE TIMING, EITHER SIDE

tSAA

A0 - A2 VALID ADDRESSVALID ADDRESS

SEM

DATA

0

R/

W

OE

NOTES:

1.CE = V

2. "DATA

tAW

tEW

IH for the duration of the above timing (both write and read cycle).

OUT VALID" represents all I/O's (I/O0-I/O7) equal to the semaphore value.

tWR

tDW

DATAIN VALID

tSOP

tACE

DATAOUT

VALID

tOH

(2)

tDHtWPtAS

tSWRD

Write Cycle 2721 drw 12

Test Cycle

tAOE

(Read Cycle)

(1)

MATCH

t

SPS

MATCH

(1, 3, 4)

SEM

"B" goes High.

2721 drw 13

TIMING WAVEFORM OF SEMAPHORE CONTENTION

A

0"A"

- A

2"A"

(2)

SIDE

NOTES:

0R = D0L = VIL, CER = CEL = VIH, Semaphore Flag is released from both sides (reads as ones from both sides) at cycle start.

1. D

2. All timing is the same for left and right ports. Port "A" may be either left or right port. Port "B" is the opposite from port "A".

3. This parameter is measured from the point where R/W "

SPS is not satisfied, there is no guarantee which side will be granted the semaphore flag.

4. If t

"A"

(2)

"B"SIDE

A

SEM

0"B"

R/

R/

SEM

W

- A

"A"

"A"

2"B"

W

"B

"

"B"

A" or

SEM

"A" goes High until R/W "B" or

6.05 9

IDT71342SA/LA
HIGH-SPEED 4K x 8 DUAL-PORT STATIC RAM WITH SEMAPHORE COMMERCIAL TEMPERATURE RANGE

FUNCTIONAL DESCRIPTION

The IDT71342 is an extremely fast Dual-Port 4K x 8 CMOS
Static RAM with an additional 8 address locations dedicated
to binary semaphore flags. These flags allow either processor
on the left or right side of the Dual-Port RAM to claim a
privilege over the other processor for functions defined by the
system designer’s software. As an example, the semaphore
can be used by one processor to inhibit the other from
accessing a portion of the Dual-Port RAM or any other shared
resource.

The Dual-Port RAM features a fast access time, and both
ports are completely independent of each other. This means
that the activity on the left port in no way slows the access time
of the right port. Both ports are identical in function to standard
CMOS Static RAMs and can be read from or written to at the
same time, with the only possible conflict arising from the
simultaneous writing of, or a simultaneous READ/WRITE of,
a non-semaphore location. Semaphores are protected against
such ambiguous situations and may be used by the system
program to avoid any conflicts in the non-semaphore portion
of the Dual-Port RAM. These devices have an automatic
power-down feature controlled by CE, the Dual-Port RAM
enable, and

SEM

, the semaphore enable. The CE and

SEM

pins control on-chip power down circuitry that permits the
respective port to go into standby mode when not selected.
This is the condition which is shown in Table 1 where CE and

SEM

are both high.

Systems which can best use the IDT71342 contain multiple
processors or controllers and are typically very high-speed
systems which are software controlled or software intensive.
These systems can benefit from a performance increase
offered by the IDT71342’s hardware semaphores, which
provide a lockout mechanism without requiring complex
programming.

Software handshaking between processors offers the
maximum in system flexibility by permitting shared resources
to be allocated in varying configurations. The IDT71342 does
not use its semaphore flags to control any resources through
hardware, thus allowing the system designer total flexibility in
system architecture.

An advantage of using semaphores rather than the more
common methods of hardware arbitration is that wait states
are never incurred in either processor. This can prove to be
a major advantage in very high-speed systems.

HOW THE SEMAPHORE FLAGS WORK

The semaphore logic is a set of eight latches which are
independent of the Dual-Port RAM. These latches can be
used to pass a flag, or token, from one port to the other to
indicate that a shared resource is in use. The semaphores
provide a hardware assist for a use assignment method called
“Token Passing Allocation.” In this method, the state of a
semaphore latch is used as a token indicating that a shared
resource is in use. If the left processor wants to use this
resource, it requests the token by setting the latch. This
processor then verifies its success in setting the latch by

reading it. If it was successful, it proceeds to assume control
over the shared resource. If it was not successful in setting the
latch, it determines that the right side processor had set the
latch first, has the token and is using the shared resource. The
left processor can then either repeatedly request that
semaphore’s status or remove its request for that semaphore
to perform another task and occasionally attempt again to gain
control of the token via the set and test sequence. Once the
right side has relinquished the token, the left side should
succeed in gaining control.

The semaphore flags are active low. A token is requested
by writing a zero into a semaphore latch and is released when
the same side writes a one to that latch.

The eight semaphore flags reside within the IDT71342 in a
separate memory space from the Dual-Port RAM. This
address space is accessed by placing a low input on the

SEM

pin (which acts as a chip select for the semaphore flags) and
using the other control pins (Address, OE, and R/W) as they
would be used in accessing a standard Static RAM. Each of
the flags has a unique address which can be accessed by
either side through the address pins A

0–A2. When accessing

the semaphores, none of the other address pins has any
effect.

When writing to a semaphore, only data pin D0 is used. If
a low level is written into an unused semaphore location, that
flag will be set to a zero on that side and a one on the other (see
Table II). That semaphore can now only be modified by the
side showing the zero. When a one is written into the same
location from the same side, the flag will be set to a one for both
sides (unless a semaphore request from the other side is
pending) and then can be written to by both sides. The fact
that the side which is able to write a zero into a semaphore
subsequently locks out writes from the other side is what
makes semaphore flags useful in interprocessor
communications. (A thorough discussion on the use of this
feature follows shortly.) A zero written into the same location
from the other side will be stored in the semaphore request
latch for that side until the semaphore is freed by the first side.

When a semaphore flag is read, its value is spread into all
data bits so that a flag that is a one reads as a one in all data
bits and a flag containing a zero reads as all zeros. The read
value is latched into one side’s output register when that side’s
semaphore select (

SEM

) and output enable (OE) signals go
active. This serves to disallow the semaphore from changing
state in the middle of a read cycle due to a write cycle from the
other side. Because of this latch, a repeated read of a
semaphore in a test loop must cause either signal (

SEM

or OE)

to go inactive or the output will never change.

A sequence of WRITE/READ must be used by the
semaphore in order to guarantee that no system level
contention will occur. A processor requests access to shared
resources by attempting to write a zero into a semaphore
location. If the semaphore is already in use, the semaphore
request latch will contain a zero, yet the semaphore flag will
appear as a one, a fact which the processor will verify by the
subsequent read (see Table II). As an example, assume a

6.05 10

IDT71342SA/LA
HIGH-SPEED 4K x 8 DUAL-PORT STATIC RAM WITH SEMAPHORE COMMERCIAL TEMPERATURE RANGE

processor writes a zero in the left port at a free semaphore
location. On a subsequent read, the processor will verify that
it has written successfully to that location and will assume
control over the resource in question. Meanwhile, if a processor
on the right side attempts to write a zero to the same semaphore
flag it will fail, as will be verified by the fact that a one will be
read from that semaphore on the right side during a subsequent
read. Had a sequence of READ/WRITE been used instead,
system contention problems could have occurred during the
gap between the read and write cycles.

It is important to note that a failed semaphore request must
be followed by either repeated reads or by writing a one into
the same location. The reason for this is easily understood by
looking at the simple logic diagram of the semaphore flag in
Figure 3. Two semaphore request latches feed into a
semaphore flag. Whichever latch is first to present a zero to

the semaphore flag will force its side of the semaphore flag low
and the other side high. This condition will continue until a one
is written to the same semaphore request latch. Should the
other side’s semaphore request latch have been written to a
zero in the meantime, the semaphore flag will now stay low
until its semaphore request latch is written to a one. From this
it is easy to understand that, if a semaphore is requested and
the processor which requested it no longer needs the resource,
the entire can hang up until a one is written into that semaphore
request latch.

The critical case of semaphore timing is when both sides
request a single token by attempting to write a zero into it at
the same time. The semaphore logic is specially designed to
resolve this problem. If simultaneous requests are made, the
logic guarantees that only one side receives the token. If one
side is earlier than the other in making the request, the first

TABLE I — NON-CONTENTION READ/WRITE CONTROL

Left or Right Port

WW

R/

W

WW

X H H X Z Port Disabled and in Power Down Mode
H H L L DATA
X X X H Z Output Disabled

u

H L H L DATA

L L H X DATA

X L L X — Not Allowed

NOTE:

1. A

OL = A10L ≠ A0R - A10R.

"H" = HIGH, "L" = LOW, "X" = Don’t Care, "Z" = High-impedance, and "u" = Low-to-High transition.

CECE

CE

CECE

H L X DATAIN Port Data Bit D0 Written Into Semaphore Flag

(1)

SEMSEM

SEM

SEMSEM

OEOE

OE

OEOE

D0-7 Function

OUT Data in Semaphore Flag Output on Port

OUT Data in Memory Output on Port

IN Data on Port Written Into Memory

2721 tbl 13

TABLE II — EXAMPLE SEMAPHORE PROCUREMENT SEQUENCE

Function D0 - D7 Left D0 - D7 Right Status

No Action 1 1 Semaphore free
Left Port Writes “0” to Semaphore 0 1 Left port has semaphore token
Right Port Writes “0” to Semaphore 0 1 No change. Right side has no write access to semaphore
Left Port Writes “1” to Semaphore 1 0 Right port obtains semaphore token
Left Port Writes “0” to Semaphore 1 0 No change. Left side has no write access to semaphore
Right Port Writes “1” to Semaphore 0 1 Left port obtains semaphore token
Left Port Writes “1” to Semaphore 1 1 Semaphore free
Right Port Writes “0” to Semaphore 1 0 Right port has semaphore token
Right Port Writes “1” to Semaphore 1 1 Semaphore free
Left Port Writes “0” to Semaphore 0 1 Left port has semaphore token
Left Port Writes “1” to Semaphore 1 1 Semaphore free

NOTES:

1. This table denotes a sequence of events for only one of the eight semaphores on the IDT71342.

2. There are eight semaphore flags written to via I/O

0 and read from all I/O's (I/O0-I/O7). These eight semaphores are addressed by A0 - A2.

6.05 11

(1,2)

2721 tbl 14

IDT71342SA/LA
HIGH-SPEED 4K x 8 DUAL-PORT STATIC RAM WITH SEMAPHORE COMMERCIAL TEMPERATURE RANGE

side to make the request will receive the token. If both
requests arrive at the same time, the assignment will be
arbitrarily made to one port or the other.

One caution that should be noted when using semaphores
is that semaphores alone do not guarantee that access to a
resource is secure. As with any powerful programming
technique, if semaphores are misused or misinterpreted, a
software error can easily happen. Code integrity is of the
utmost importance when semaphores are used instead of
slower, more restrictive hardware intensive schemes.

Initialization of the semaphores is not automatic and must
be handled via the initialization program at power up. Since
any semaphore request flag which contains a zero must be
reset to a one, all semaphores on both sides should have a
one written into them at initialization from both sides to assure
that they will be free when needed.

USING SEMAPHORES–Some examples

Perhaps the simplest application of semaphores is their
application as resource markers for the IDT71342’s Dual-Port
RAM. Say the 4K x 8 RAM was to be divided into two 2K x 8
blocks which were to be dedicated at any one time to servicing
either the left or right port. Semaphore 0 could be used to
indicate the side which would control the lower section of
memory, and Semaphore 1 could be defined as the indicator
for the upper section of the memory.

To take a resource, in this example the lower 2K of Dual­Port RAM, the processor on the left port could write and then
read a zero into Semaphore 0. If this task were successfully
completed (a zero was read back rather than a one), the left
processor would assume control of the lower 2K. Meanwhile,
the right processor would attempt to perform the same function.
Since this processor was attempting to gain control of the
resource after the left processor, it would read back a one in
response to the zero it had attempted to write into Semaphore

0. At this point, the software could choose to try and gain
control of the second 2K section by writing, then reading a zero
into Semaphore 1. If it succeeded in gaining control, it would
lock out the left side.

Once the left side was finished with its task, it would write

a one to Semaphore 0 and may then try to gain access to
Semaphore 1. If Semaphore 1 was still occupied by the right
side, the left side could undo its semaphore request and
perform other tasks until it was able to write, then read a zero
into Semaphore 1. If the right processor performs a similar
task with Semaphore 0, this protocol would allow the two
processors to swap 2K blocks of Dual-Port RAM with each
other.

The blocks do not have to by any particular size and can
even be variable, depending upon the complexity of the
software using the semaphore flags. All eight semaphores
could be used to divide the Dual-Port RAM or other shared
resources into eight parts. Semaphores can even be assigned
different meanings on different sides rather than being given
a common meaning as was shown in the example above.

Semaphores are a useful form of arbitration in systems like
disk interfaces where the CPU must be locked out of a section
of memory during a transfer and the I/O device cannot tolerate
any wait states. With the use of semaphores, once the two
devices had determined which memory area was “off limits” to
the CPU, both the CPU and the I/O devices could access their
assigned portions of memory continuously without any wait
states.

Semaphores are also useful in applications where no
memory “WAIT” state is available on one or both sides. Once
a semaphore handshake has been performed, both processors
can access their assigned RAM segments at full speed.

Another application is in the area of complex data structures.
In this case, block arbitration is very important. For this
application one processor may be responsible for building and
updating a data structure. The other processor then reads
and interprets that data structure. If the interpreting processor
reads an incomplete data structure, a major error condition
may exist. Therefore, some sort of arbitration must be used
between the two different processors. The building processor
arbitrates for the block, locks it and then is able to go in and
update the data structure. When the update is completed, the
data structure block is released. This allows the interpreting
processor to come back and read the complete data structure,
thereby guaranteeing a consistent data structure.

L PORT

REQUEST FLIP FLOP

0

D

WRITE

SEMAPHORE

READ

SEMAPHORE

DQ

Figure 3. IDT71342 Semaphore Logic

R PORT

SEMAPHORE

REQUEST FLIP FLOP

QD

SEMAPHORE
READ

6.05 12

0

D

WRITE

2721 drw 14

IDT71342SA/LA
HIGH-SPEED 4K x 8 DUAL-PORT STATIC RAM WITH SEMAPHORE COMMERCIAL TEMPERATURE RANGE

ORDERING INFORMATION

IDT XXXX A 999 A A

Device Type Power Speed Package Process/

Temperature

Range

Blank

J

PF

20
25
35
45
55
70

LA
SA

71342

Commercial (0°C to +70°C)
52-pin PLCC (J52-1)

64-pin TQFP (PN64-1)

Speed in nanoseconds

Low Power
Standard Power

32K (4K x 8-Bit) Dual-Port RAM w/ Semaphore

2721 drw 15

6.05 13