Datasheet IDT71256SA70P, IDT71256SA70PZ, IDT71256SA70TP, IDT71256SA70Y Datasheet (Integrated Device Technology Inc)

Integrated Device Technology, Inc.

FEATURES:

• 32K x 8 CMOS static RAM

• Equal access and cycle times

-- Commercial: 70ns

• One Chip Select plus one Output Enable pin

• Bidirectional data inputs and outputs directly
TTL-compatible

• Low power consumption via chip deselect

• Available in 28-pin 30 mil Plastic SOJ, 28-pin 300 mil
Plastic Dip, 28-pin 300 mil TSOP Type I, and 28-pin 600
mil Plastic Dip.

DESCRIPTION:

The IDT71256SA is a 262,144-bit medium-speed Static
RAM organized as 32K x 8. It is fabricated using IDT’s high­perfomance, high-reliability CMOS technology. This state-of­the-art technology, combined with innovative circuit design
techniques, provides a cost-effective solution for your memory
needs.

All bidirectional inputs and outputs of the IDT71256SA are
TTL-compatible and operation is from a single 5V supply.
Fully static asynchronous circuitry is used, requiring no clocks
or refresh for operation.

The IDT71256SA is packaged in a 28-pin 300 mil Plastic
SOJ, 28-pin 300 mil Plastic Dip, 28-pin 300 mil TSOP Type I
and 28-pin 600 mil Plastic Dip.

FUNCTIONAL BLOCK DIAGRAM

1

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

COMMERCIAL TEMPERATURE RANGE JULY 1996

1996 Integrated Device Technology, Inc. 3567/1

A

ADDRESS

DECODER

262,144 BIT

MEMORY ARRAY

I/O CONTROL

3567 drw 01

INPUT

DATA

CIRCUIT

WE

CS

V

CC

GND

0

A14

I/O 0

I/O

7

CONTROL

CIRCUIT

OE

CMOS STATIC RAM
256K (32K x 8-BIT)

IDT71256SA70

IDT71256SA70
CMOS STATIC RAM 256K (32K x 8-BIT) COMMERCIAL TEMPERATURE RANGES

2

PIN CONFIGURATION

CAPACITANCE

(TA = +25°C, f = 1.0MHz, SOJ package)

Symbol Parameter

(1)

Conditions Max. Unit

C

IN Input Capacitance VIN = 3dV 11 pF

C

I/O I/O Capacitance VOUT = 3dV 11 pF

NOTE: 3567 tbl 03

1. This parameter is guaranteed by device characterization, but not prod-

uction tested.

3567 tbl 05

DC ELECTRICAL CHARACTERISTICS

VCC = 5.0V ± 10%

IDT71256SA

Symbol Parameter Test Condition Min. Max. Unit

|I

LI| Input Leakage Current VCC = Max., VIN = GND to VCC — 5 µA

|I

LO| Output Leakage Current VCC = Max.,

CS

= VIH, VOUT = GND to VCC — 5 µA

V

OL Output Low Voltage IOL = 8mA, VCC = Min. — 0.4 V

V

OH Output High Voltage IOH = –4mA, VCC = Min. 2.4 — V

TRUTH TABLE

(1,2)

CSCSOEOEWEWE I/O Function

L L H DATA

OUT Read Data

L X L DATA

IN Write Data

L H H High-Z Outputs Disabled

H X X High-Z Deselected — Standby (I

SB)

V

HC X X High-Z Deselected — Standby (ISB1)

NOTES: 3567 tbl 04

1. H = VIH, L = VIL, x = Don't care.

2. V

LC = 0.2V, VHC = VCC –0.2V.

3. Other inputs ≥V

HC or ≤VLC.

(3)

RECOMMENDED DC OPERATING
CONDITIONS

Symbol Parameter Min. Typ. Max. Unit

V

CC Supply Voltage 4.5 5.0 5.5 V

GND Supply Voltage 0 0 0 V
V

IH Input High Voltage 2.2 — VCC+0.5 V

V

IL Input Low Voltage –0.5

(1)

— 0.8 V

NOTE: 3567 tbl 01

1. VIL (min.) = –1.5V for pulse width less than 10ns, once per cycle.

ABSOLUTE MAXIMUM RATINGS

(1)

Symbol Rating Com’l. Unit

V

TERM

(2)

Terminal Voltage –0.5 to +7.0 V
with Respect
to GND

T

A Operating 0 to +70 °C

Temperature

T

BIAS Temperature –55 to +125 °C

Under Bias

T

STG Storage –55 to +125 °C

Temperature

P

T Power 1.0 W

Dissipation

I

OUT DC Output 50 mA

Current

NOTES: 3567 tbl 02

1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.

3567 drw 02

5
6
7
8

9
10
11
12

GND

1

2

3

4

24
23

22
21

20
19

18
17

SO28-5

P28-1
P28-2

13
14

28
27
26
25

A7
A6
A5
A4
A3
A2
A1

A0
I/O0
I/O1
I/O2

VCC

A14

WE

A

13

A8

A10

A11

OE

A

12

CS

I/O

7

I/O6
I/O5
I/O4
I/O3

A9

16
15

SOJ/DIP

TOP VIEW

3567 drw 03

22
23
24
25
26
27
28
1
2
3
4
5

7

6

21
20
19
18
17
16
15
14
13
12
11
10

9
8

A10

CS

I/O

7

I/O6
I/O5
I/O4
I/O3
GND
I/O

2

I/O1
I/O0
A0
A1
A2

SO28-8

OE

A

11

A9
A8

A13

A14

A7
A6
A5
A4
A3

A12

WE

V

CC

TSOP

TOP VIEW

IDT71256SA70
CMOS STATIC RAM 256K (32K x 8-BIT) COMMERCIAL TEMPERATURE RANGES

3

AC TEST CONDITIONS

Input Pulse Levels GND to 3.0V
Input Rise/Fall Times 3ns
Input Timing Reference Levels 1.5V
Output Reference Levels 1.5V
AC Test Load See Figures 1 and 2

3567 tbl 07

Figure 2. AC Test Load

(for t

CLZ, tOLZ, tCHZ, tOHZ, tOW, and tWHZ)

Figure 1. AC Test Load

*Including jig and scope capacitance.

3567 drw 04

480Ω

255Ω

30pF*

DATA

OUT

5V

3567 drw 05

480Ω

255Ω

5pF*

DATA

OUT

5V

DC ELECTRICAL CHARACTERISTICS

(1)

(VCC = 5.0V ± 10%, VLC = 0.2V, VHC = VCC–0.2V)

71256SA70

Symbol Parameter Com’l. Unit

I

CC Dynamic Operating Current 130 mA

CS

≤ V

IL, Outputs Open, VCC = Max., f = fMAX

(2)

ISB Standby Power Supply Current (TTL Level) 20 mA

CS

≥ V

IH, Outputs Open, VCC = Max., f = fMAX

(2)

ISB1 Standby Power Supply Current (CMOS Level) 15 mA

CS

≥ V

HC, Outputs Open, VCC = Max., f = 0

(2)

VIN ≤ VLC or VIN ≥ VHC

NOTES: 3567 tbl 06

1. All values are maximum guaranteed values.

2. f

MAX = 1/tRC (all address inputs are cycling at fMAX); f = 0 means no address input lines are changing .

IDT71256SA70
CMOS STATIC RAM 256K (32K x 8-BIT) COMMERCIAL TEMPERATURE RANGES

4

TIMING WAVEFORM OF READ CYCLE NO. 1

(1)

AC ELECTRICAL CHARACTERISTICS (VCC = 5.0V ± 10%, CommercialTemperature Range Only)

71256SA70

Symbol Parameter Min. Max. Unit
Read Cycle

t

RC Read Cycle Time 70 — ns

t

AA Address Access Time —70ns

t

ACS Chip Select Access Time —70ns

t

CLZ

(2)

Chip Select to Output in Low-Z 4 — ns

t

CHZ

(2)

Chip Deselect to Output in High-Z 0 11 ns

t

OE Output Enable to Output Valid — 11 ns

t

OLZ

(2)

Output Enable to Output in Low-Z 0 — ns

t

OHZ

(2)

Output Disable to Output in High-Z 0 10 ns

t

OH Output Hold from Address Change 3 — ns

t

PU

(2)

Chip Select to Power Up Time 0 — ns

t

PD

(2)

Chip Deselect to Power Down Time — 25 ns

Write Cycle

t

WC Write Cycle Time 70 — ns

t

AW Address Valid to End of Write 20 — ns

t

CW Chip Select to End of Write 20 — ns

t

AS Address Set-up Time 0—ns

t

WP Write Pulse Width 20 — ns

t

WR Write Recovery Time 0—ns

t

DW Data Valid to End of Write 13 — ns

t

DH Data Hold Time 0—ns

t

OW

(2)

Output Active from End of Write 4 — ns

t

WHZ

(2)

Write Enable to Output in High-Z 0 11 ns

NOTES: 3567 tbl 08

1. 0° to +70°C temperature range only.

2. This parameter is guaranteed with the AC Load (Figure 2) by device characterization, but is not production tested.

ADDRESS

OE

CS

DATA

OUT

VCC SUPPLY

CURRENT

3567 drw 06

(5)

(5)

(5)

(5)

DATA VALID

HIGH IMPEDANCE

t

AA

tRC

tOE

tACS

tOLZ

tCHZ

tCLZ

(3)

tOHZ

OUT

tPU

tPD

ICC
ISB

IDT71256SA70
CMOS STATIC RAM 256K (32K x 8-BIT) COMMERCIAL TEMPERATURE RANGES

5

TIMING WAVEFORM OF READ CYCLE NO. 2

(1,2,4)

TIMING WAVEFORM OF WRITE CYCLE NO.1 (

WEWE CONTROLLED TIMING)

(1,2,3,5)

NOTES:

1.WE or

CS

must be HIGH during all address transitions.

2. A write occurs during the overlap of a LOW CS and a LOW WE.

3.OE is continuously HIGH. If during a WE controlled write cycle OE is LOW, t

WP must be greater than or equal to tWHZ + tDW to allow the I/O drivers to turn

off and data to be placed on the bus for the required t

DW. If

OE

is HIGH during a WE controlled write cycle, this requirement does not apply and the

minimum write pulse is as short as the specified t

WP.

4. During this period, I/O pins are in the output state, and input signals must not be applied.

5. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state.

6. Transition is measured ±200mV from steady state.

TIMING WAVEFORM OF WRITE CYCLE NO.2 (

CSCS CONTROLLED TIMING)

(1,2,5)

NOTES:

1.WE is HIGH for Read Cycle.

2. Device is continuously selected, CS is LOW.

3. Address must be valid prior to or coincident with the later of CS transition LOW; otherwise t

AA is the limiting parameter.

4.OE is LOW.

5. Transition is measured ±200mV from steady state.

DATAOUT

ADDRESS

3567 drw 07

tRC

tAA

tOH tOH

DATAOUT VALID

PREVIOUS DATAOUT VALID

ADDRESS

CS

WE

DATA

OUT

DATAIN

3567 drw 08

(6)

(4)

(4)

(3)

(6)

(6)

DATAIN VALID

HIGH IMPEDANCE

t

WC

tAS

tWHZ

tWP

tCHZ

tOW

tDW

tWR

tAW

tDH

CS

ADDRESS

WE

3567 drw 09

DATAIN VALID

tAW

tWC

tCW

tAS

tWR

tDW

tDH

DATAIN

IDT71256SA70
CMOS STATIC RAM 256K (32K x 8-BIT) COMMERCIAL TEMPERATURE RANGES

6

ORDERING INFORMATION

SA

PowerXXSpeed

XXX

Package

X

Process/

Temperature

Range

Blank

Commercial (0

°

C to +70°C)

P
TP
Y
PZ

600-mil Plastic Dip (P28-1)
300-mil Plastic DIP (P28-2)
300-mil SOJ (SO28-5)
TSOP Type I (SO28-8)

70

71256

Device

Type

IDT

Speed in nanoseconds

3567 drw 10