Datasheet IDT71256SA12P, IDT71256SA12PZ, IDT71256SA12TP, IDT71256SA12Y, IDT71256SA15P Datasheet (Integrated Device Technology Inc)
...Page 1
Integrated Device Technology, Inc.
INDUSTRIAL AND COMMERCIAL TEMPERATURE RANGES MAY 1997
1997 Integrated Device Technology, Inc. DSC-2948/04
FEATURES:
• 32K x 8 advanced high-speed CMOS static RAM
• Commercial (0° to 70°C) and Industrial (-40° to 85°C)
temperature options
• Equal access and cycle times
— Commercial: 12/15/20/25ns
— Industrial: 15/20ns
• One Chip Select plus one Output Enable pin
• Bidirectional data inputs and outputs directly
TTL-compatible
• Low power consumption via chip deselect
• Commercial product available in 28-pin 300- and 600-mil
Plastic DIP, 300 mil Plastic SOJ and TSOP packages
• Industrial product available in 28-pin 300 mil Plastic SOJ
and TSOP packages
DESCRIPTION:
The ID71256SA is a 262,144-bit high-speed Static RAM
organized as 32K x 8. It is fabricated using IDT’s highperfomance, high-reliability CMOS technology. This state-ofthe-art technology, combined with innovative circuit design
techniques, provides a cost-effective solution for high-speed
memory needs.
The IDT71256SA has an output enable pin which operates
as fast as 6ns, with address access times as fast as 12ns. All
bidirectional inputs and outputs of the IDT71256SA are TTLcompatible and operation is from a single 5V supply. Fully
static asynchronous circuitry is used, requiring no clocks or
refresh for operation.
The IDT71256SA is packaged in 28-pin 300- and 600-mil
Plastic DIP, 28-pin 300 mil Plastic SOJ and TSOP.
FUNCTIONAL BLOCK DIAGRAM
1
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
A10
A11
A12
A13
A14
A0
A
1
A2
A
3
A4
A
5
A6
A
7
A8
A
9
262,144-BIT
MEMORY
ARRAY
I/O CONTROL
I/O0– I/O
7
CONTROL
LOGIC
WE
OE
CS
2948 drw 01
8 8
ADDRESS
DECODER
CMOS STATIC RAM
256K (32K x 8-BIT)
IDT71256SA
Page 2
2
IDT71256SA
CMOS STATIC RAM 256K (32K x 8-BIT) INDUSTRIAL AND COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol Rating Value Unit
V
CC Supply Voltage –0.5 to +7.0 V
Relative to GND
V
TERM Terminal Voltage –0.5 to VCC+0.5 V
Relative to GND
T
BIAS Temperature –55 to +125 °C
Under Bias
T
STG Storage –55 to +125 °C
Temperature
P
T Power 1.0 W
Dissipation
I
OUT DC Output 50 mA
Current
NOTES: 2948 tbl 02
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
PIN CONFIGURATIONS
2948 tbl 05
DC ELECTRICAL CHARACTERISTICS
VCC = 5.0V ± 10%
IDT71256SA
Symbol Parameter Test Condition Min. Max. Unit
|I
LI| Input Leakage Current VCC = Max., VIN = GND to VCC — 5 µA
|I
LO| Output Leakage Current VCC = Max.,
CS
= VIH, VOUT = GND to VCC — 5 µA
V
OL Output Low Voltage IOL = 8mA, VCC = Min. — 0.4 V
V
OH Output High Voltage IOH = –4mA, VCC = Min. 2.4 — V
2948 drw 02
5
6
7
8
9
10
11
12
GND
1
2
3
4
24
23
22
21
20
19
18
17
SO28-5
P28-2
P28-1
13
14
28
27
26
25
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
I/O
0
I/O
1
I/O
2
V
CC
A
14
WE
A
13
A
8
A
10
A
11
OE
A
12
CS
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
A
9
16
15
DIP/SOJ
TOP VIEW
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Grade Temperature GND VCC
Commercial 0°C to +70°C 0V 4.5V to 5.5V
Industrial -40°C to +85°C 0V 4.5V to 5.5V
3948 tbl 09
RECOMMENDED DC OPERATING
CONDITIONS
Symbol Parameter Min. Typ. Max. Unit
V
CC Supply Voltage 4.5 5.0 5.5 V
GND Supply Voltage 0 0 0 V
V
IH Input High Voltage 2.2 — VCC+0.5 V
V
IL Input Low Voltage –0.5
(1)
— 0.8 V
NOTE: 2948 tbl 01
1. VIL (min.) = –1.5V for pulse width less than 10ns, once per cycle.
TRUTH TABLE
(1,2)
CSCSOEOEWEWE I/O Function
L L H DATA
OUT Read Data
L X L DATA
IN Write Data
L H H High-Z Outputs Disabled
H X X High-Z Deselected — Standby (I
SB)
V
HC X X High-Z Deselected — Standby (ISB1)
NOTES: 2948 tbl 04
1. H = VIH, L = VIL, x = Don't care.
2. V
LC = 0.2V, VHC = VCC –0.2V.
3. Other inputs ≥V
HC or ≤VLC.
(3)
TSOP
TOP VIEW
2948 drw 11
22
23
24
25
26
27
28
1
2
3
4
5
7
6
21
20
19
18
17
16
15
14
13
12
11
10
9
8
A10
CS
I/O
7
I/O6
I/O5
I/O4
I/O3
GND
I/O
2
I/O1
I/O0
A0
A1
A2
SO28-8
OE
A
11
A9
A8
A13
A14
A7
A6
A5
A4
A3
A12
WE
V
CC
Page 3
3
IDT71256SA
CMOS STATIC RAM 256K (32K x 8-BIT) INDUSTRIAL AND COMMERCIAL TEMPERATURE RANGES
Figure 2. AC Test Load
(for t
CLZ, tOLZ, tCHZ, tOHZ, tOW, and tWHZ)
Figure 1. AC Test Load
*Including jig and scope capacitance.
2948 drw 03
480
Ω
255
Ω
30pF*
DATA
OUT
5V
2948 drw 04
480
Ω
255
Ω
5pF*
DATA
OUT
5V
DC ELECTRICAL CHARACTERISTICS
(1)
(VCC = 5.0V ± 10%, VLC = 0.2V, VHC = VCC–0.2V)
Symbol Parameter 71256SA12
(3)
71256SA15 71256SA20 71256SA25
(3)
Unit
I
CC Dynamic Operating Current 160 150 145 145 mA
CS
≤ V
IL, Outputs Open, VCC = Max., f = fMAX
(2)
ISB Standby Power Supply Current (TTL Level) 50 40 40 40 mA
CS
≥ V
IH, Outputs Open, VCC = Max., f = fMAX
(2)
ISB1 Standby Power Supply Current (CMOS Level) 15 15 15 15 mA
CS
≥ V
HC, Outputs Open, VCC = Max., f = 0
(2)
VIN ≤ VLC or VIN ≥ VHC
NOTES: 2948 tbl 06
1. All values are maximum guaranteed values.
2. f
MAX = 1/tRC (all address inputs are cycling at fMAX); f = 0 means no address input lines are changing .
3. Commercial temperature range only.
AC TEST CONDITIONS
Input Pulse Levels GND to 3.0V
Input Rise/Fall Times 3ns
Input Timing Reference Levels 1.5V
Output Reference Levels 1.5V
AC Test Load See Figures 1 and 2
2948 tbl 07
CAPACITANCE
(TA = +25°C, f = 1.0MHz, SOJ package)
Symbol Parameter
(1)
Conditions Max. Unit
C
IN Input Capacitance VIN = 3dV 7 pF
C
I/O I/O Capacitance VOUT = 3dV 7 pF
NOTE: 2948 tbl 03
1. This parameter is guaranteed by device characterization, but not production tested.
Page 4
4
IDT71256SA
CMOS STATIC RAM 256K (32K x 8-BIT) INDUSTRIAL AND COMMERCIAL TEMPERATURE RANGES
ADDRESS
OE
CS
DATA
OUT
VCC SUPPLY
CURRENT
2948 drw 05
(5)
(5)
(5)
(5)
DATA VALID
HIGH IMPEDANCE
t
AA
tRC
tOE
tACS
tOLZ
tCHZ
tCLZ
(3)
tOHZ
OUT
tPU
tPD
ICC
ISB
TIMING WAVEFORM OF READ CYCLE NO. 1
(1)
AC ELECTRICAL CHARACTERISTICS (VCC = 5.0V ± 10%)
71256SA12
(2)
71256SA15 71256SA20 71256SA25
(2)
Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max.
Read Cycle
t
RC Read Cycle Time 12 — 15 — 20 — 25 — ns
t
AA Address Access Time — 12 — 15 — 20 — 25 ns
t
ACS Chip Select Access Time — 12 — 15 — 20 — 25 ns
t
CLZ
(1)
Chip Select to Output in Low-Z 4 — 4 — 4 — 4 — ns
t
CHZ
(1)
Chip Deselect to Output in High-Z 0607010011ns
t
OE Output Enable to Output Valid — 6 — 7 — 10 — 11 ns
t
OLZ
(1)
Output Enable to Output in Low-Z 0 — 0 — 0 — 0 — ns
t
OHZ
(1)
Output Disable to Output in High-Z 060608010ns
t
OH Output Hold from Address Change 3 — 3 — 3 — 3 — ns
t
PU
(1)
Chip Select to Power Up Time 0 — 0 — 0 — 0 — ns
t
PD
(1)
Chip Deselect to Power Down Time — 12 — 15 — 20 — 25 ns
Write Cycle
t
WC Write Cycle Time 12 — 15 — 20 — 25 — ns
t
AW Address Valid to End of Write 9 — 10 — 15 — 20 — ns
t
CW Chip Select to End of Write 9 — 10 — 15 — 20 — ns
t
AS Address Set-up Time 0 — 0 — 0 — 0 — ns
t
WP Write Pulse Width 9 — 10 — 15 — 20 — ns
t
WR Write Recovery Time 0 — 0 — 0 — 0 — ns
t
DW Data Valid to End of Write 6 — 7 — 11 — 13 — ns
t
DH Data Hold Time 0 — 0 — 0 — 0 — ns
t
OW
(1)
Output Active from End of Write 4 — 4 — 4 — 4 — ns
t
WHZ
(1)
Write Enable to Output in High-Z 0606010011ns
NOTE: 2948 tbl 08
1. This parameter is guaranteed with the AC Load (Figure 2) by device characterization, but is not production tested.
2. Commercial temperature range only.
Page 5
5
IDT71256SA
CMOS STATIC RAM 256K (32K x 8-BIT) INDUSTRIAL AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF READ CYCLE NO. 2
(1,2,4)
TIMING WAVEFORM OF WRITE CYCLE NO.1 (
WEWE CONTROLLED TIMING)
(1,2,3,5)
NOTES:
1.WE or
CS
must be HIGH during all address transitions.
2. A write occurs during the overlap of a LOW CS and a LOW WE.
3.OE is continuously HIGH. If during a WE controlled write cycle OE is LOW, t
WP must be greater than or equal to tWHZ + tDW to allow the I/O drivers to turn
off and data to be placed on the bus for the required t
DW. If
OE
is HIGH during a WE controlled write cycle, this requirement does not apply and the
minimum write pulse is as short as the specified t
WP.
4. During this period, I/O pins are in the output state, and input signals must not be applied.
5. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state.
6. Transition is measured ±200mV from steady state.
TIMING WAVEFORM OF WRITE CYCLE NO.2 (
CSCS CONTROLLED TIMING)
(1,2,5)
NOTES:
1.WE is HIGH for Read Cycle.
2. Device is continuously selected, CS is LOW.
3. Address must be valid prior to or coincident with the later of CS transition LOW; otherwise t
AA is the limiting parameter.
4.OE is LOW.
5. Transition is measured ±200mV from steady state.
DATA
OUT
ADDRESS
2948 drw 06
t
RC
t
AA
t
OH
t
OH
DATA
OUT
VALID
PREVIOUS DATA
OUT
VALID
ADDRESS
CS
WE
DATA
OUT
DATA
IN
2948 drw 07
(6)
(4)
(4)
(3)
(6)
(6)
DATA
IN
VALID
HIGH IMPEDANCE
t
WC
t
AS
t
WHZ
t
WP
t
CHZ
t
OW
t
DW
t
WR
t
AW
t
DH
CS
ADDRESS
WE
2948 drw 08
DATA
IN
VALID
t
AW
t
WC
t
CW
t
AS
t
WR
t
DW
t
DH
DATA
IN
Page 6
6
IDT71256SA
CMOS STATIC RAM 256K (32K x 8-BIT) INDUSTRIAL AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION - COMMERCIAL
SA
PowerXXSpeed
XXX
Package
X
Process/
Temperature
Range
Blank
Commercial (0°C to +70°C)
P
TP
Y
PZ
600-mil Plastic DIP (P28-1)
300-mil Plastic DIP (P28-2)
300-mil SOJ (SO28-5)
TSOP Type I (SO28-8)
12
15
20
25
71256
Device
Type
IDT
Speed in nanoseconds
2948 drw 09
SA
PowerXXSpeed
XXX
Package
X
Process/
Temperature
Range
I
Industrial (-40
°
C to +85°C)
Y
PZ
300-mil SOJ (SO28-5)
TSOP Type I (SO28-8)
15
20
71256
Device
Type
IDT
Speed in nanoseconds
2948 drw 10
ORDERING INFORMATION - INDUSTRIAL
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