Datasheet IDT71256S, IDT71256L Datasheet (Integrated Device Technology)

HIGH-SPEED
4K x 8 DUAL-PORT
STATIC SRAM

IDT7134SA/LA

Feature s

◆◆

◆

◆◆

High-speed access

– Military: 25/35/45/55/70ns (max.)
– Industrial: 25/35/55ns (max.)
– Commercial: 20/25/35/45/55/70ns (max.)

◆◆

◆

◆◆

Low-power operation

– IDT7134SA

Active: 700mW (typ.)
Standby: 5mW (typ.)

– IDT7134LA

Active: 700mW (typ.)
Standby: 1mW (typ.)

Functional Block Diagram

R/W

L

CE

L

OE

L

◆◆

◆

◆◆

Fully asynchronous operation from either port

◆◆

◆

◆◆

Battery backup operation—2V data retention (LA only)

◆◆

◆

◆◆

TTL-compatible; single 5V (±10%) power supply

◆◆

◆

◆◆

Available in 48-pin DIP, LCC, Flatpack and 52-pin PLCC

◆◆

◆

◆◆

Military product compliant to MIL-PRF-38535 QML

◆◆

◆

◆◆

Industrial temperature range (–40°C to +85°C) is available for
selected speeds

◆◆

◆

◆◆

Green parts available, see ordering information

R/W

R

CE

R

OE

R

I/O0L-I/O

A0L-A

©2006 Integrated Device Technology, Inc.

7L

11L

ADDRESS

DECODER

I/O

CONTROL

MEMORY

ARRAY

1

I/O

CONTROL

ADDRESS

DECODER

I/O0R-I/O

A0R-A

7R

11R

2720 drw 01

JANUARY 2006

DSC-2720/13

IDT7134SA/LA
High-Speed 4K x 8 Dual-Port Static SRAM Military, Industrial and Commercial Temperature Ranges

Description

The IDT7134 is a high-speed 4K x 8 Dual-Port Static RAM
designed to be used in systems where on-chip hardware port arbitration
is not needed. This part lends itself to those systems which cannot
tolerate wait states or are designed to be able to externally arbitrate or
withstand contention when both sides simultaneously access the
same Dual-Port RAM location.

The IDT7134 provides two independent ports with separate control,
address, and I/O pins that permit independent, asynchronous access
for reads or writes to any location in memory. It is the user’s responsibility
to ensure data integrity when simultaneously accessing the same
memory location from both ports. An automatic power down feature,

controlled by CE, permits the on-chip circuitry of each port to enter a very
low standby power mode.

Fabricated using IDT’s CMOS high-performance technology, these
Dual-Ports typically operate on only 700mW of power. Low-power (LA)
versions offer battery backup data retention capability, with each port
typically consuming 200µW from a 2V battery.

The IDT7134 is packaged on either a sidebraze or plastic 48-pin
DIP, 48-pin LCC, 52-pin PLCC and 48-pin Flatpack. Military grade
product is manufactured in compliance with the latest revision of MIL­PRF-38535 QML, making it ideally suited to military temperature
applications demanding the highest level of performance and reliability.

Pin Configurations

CE

L

148

R/W

A

A

OE

A
A

A
A
A

A
A

A
A
A

I/O
I/O

I/O
I/O
I/O
I/O
I/O
I/O

GND

11L
10L

0L
1L

2L
3L
4L

5L
6L

7L
8L
9L

L

L

0L
1L

2L
3L
4L
5L
6L
7L

2
3
4
5
6
7
8

IDT7134P or C

P48-1

9
10

C48-2

11
12

48-Pin

13

View

14
15
16
17
18
19
20
21
22
23
24

Top

47
46
45
44
43
42
41

(4)

40

&

39

(4)

38
37
36

(5)

35
34
33
32
31
30
29
28
27
26
25

(1,2,3)

CC

V

CE

R/W
A

11R

A

10R

OE

A

0R

A

1R

A

2R

A

3R

A

4R

A

5R

A

6R

A

7R

A

8R

A

9R

I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O

2720 drw 02

R

7R
6R
5R
4R
3R
2R
1R
0R

L

L
0

8
9
10
11
12
13
14
15
16
17
18
19
20

A

L
4

O

/

I

L

0

A

INDEX

A

I/O
I/O
I/O
I/O

1L

A

2L

A

3L

A

4L

A

5L

A

6L

A

7L

A

8L

A

9L
0L
1L
2L
3L

R

R

,

INDEX

1

0

E

1

1

O

A

A

L

L

L

5

6

7

O

O

O

/

/

/

I

I

I

L

L

L

0

1

E

1

1

O

A

A

L

C

W

/

/

E

N

R

C

234567

1

IDT7134J

J52-1

52-Pin

PLCC

Top View

R

D

C

/

0

N

N

O

/

G

I

L

L

W

E

/

C

R

(4)

L

L

L

R

R

R

C

W

/

E

C

V

C

R

R

C

1

0

/

1

1

N

A

A

474849505152

46

OE

R

45

A

0R

44

A

1R

43

A

2R

42

A

3R

41

A

4R

40

A

5R

39

A

(5)

38
37
36
35
34

33323130292827262524232221

R

R

R

R

R

1

2

3

O

O

O

/

/

/

I

I

I

R

R

C

W

E

/

C

C

R

V

R

4

5

6

O

O

O

/

/

/

I

I

I

R

R

R

1

0

E

1

1

O

A

A

6R

A

7R

A

8R

A

9R

N/C
I/O

2720 drw03

7R

NOTES:

CC pins must be connected to the power supply.

1. All V

2. All GND pins must be connected to the ground supply.

3. P48-1 package body is approximately .55 in x 2.43 in x .18 in.
C48-2 package body is approximately .62 in x 2.43 in x .15 in.
J52-1 package body is approximately .75 in x .75 in x .17 in.
L48-1 package body is approximately .57 in x .57 in x .68 in.
F48-1 package body is approxiamtely .75 in x .75 in x .11 in.

4. This package code is used to reference the package diagram.

5. This text does not indicate orientation of actual part-marking.

65432148 47 46 45 44 43

42
41
40
39
38
37
36
35
34
33
32
31

A
A
A
A
A
A
A
A
A
A
I/O
I/O

0R
1R
2R
3R
4R
5R
6R
7R
8R
9R

,

7R
6R

I/O
I/O
I/O

A

1L

7

A

2L

8

A

3L

9

A

4L

10

A

5L

11

A

6L

12

A

7L

13

A

8L

14

A

9L

15

0L

16

1L

17

2L

18

IDT7134L48 or F

48-Pin LCC/Flatpack

L48-1

&

F48-1

Top View

(4)

(4)

(5)

19 20 21 22 23 25 26 27 28 29 3024

2720 drw 04

L

3

O

/

I

L

L

L

L

5

6

4

O

O

O

/

/

/

I

I

I

R

D

R

7

N

O

/

G

I

R

0

1

2

O

O

O

/

/

/

I

I

I

R

R

R

5

4

3

O

O

O

/

/

/

I

I

I

2

IDT7134SA/LA
High-Speed 4K x 8 Dual-Port Static SRAM Military, Industrial and Commercial Temperature Ranges

Absolute Maximum Ratings

Symbol Rating Commercial

& Ind ust ria l

V

TERM

(2)

Te rminal Vo ltage

-0.5 to +7.0 -0.5 to +7.0 V
with Re s p ec t
to G ND

T

BIAS

Temperature

-55 to +125 -65 to +135
Unde r Bias

STG

T

Storage

-65 to +150 -65 to +150
Temperature

(3)

T

P

Power

1.5 1.5 W

Military Unit

(1)

Recommended Operating
Temperature and Supply Voltage

Military -55

o

Commercial 0

C

Industrial -40

o

C

NOTES:

1. This is the parameter T

Grade Ambient

Temperature

O

C to + 12 5OC0V 5.0V + 10%

O

C to + 70OC0V5.0V

O

C to + 85OC0V 5.0V + 10%

A. This is the "instant on" case temperature.

GND Vcc

+

10%

2720 tbl 03

Dissipation

I

OUT

DC Output

50 50 mA

Current

NOTES:

27 20 tb l 01

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.

TERM must not exceed Vcc + 10% for more than 25%of the cycle time or 10 ns

2. V
maximum, and is limited to

TERM = 5.5V.

3. V

Capacitance

Symbol Parameter Conditions

C

IN

Input Capacitance VIN = 3dV 11 pF

< 20mA for the period of VTERM > Vcc +10%.

(1)

(TA = +25°C, f = 1.0MHz)

(2)

Max. Unit

Recommended DC Operating
Conditions

Symbol Parameter Min. Typ. Max. Unit

V

CC

Sup pl y Vo ltag e 4.5 5.0 5.5 V

GND Ground 0 0 0 V

IH

Input Hi gh Vo ltage 2.2

V
V

IL

Input Lo w Voltag e -0.5

NOTES:

1. V

IL (min.) > -1.5V for pulse width less than 10ns.
TERM must not exceed Vcc + 10%.

2. V

____

(1)

____

(2)

6.0

0.8 V

2720 tbl 04

(1,2)

V

C

OUT

Outp ut Ca p aci tanc e V

NOTES:

OUT

= 3dV 11 pF

2720 tbl 02

1. This parameter is determined by device characterization but is not production
tested.

2. 3dV references the interpolated capacitance when the input and output signals
switch from 0V to 3V and from 3V to 0V.

DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range

Symbol Parameter Test Conditions

|I

LI

| Input Leakage Current

|I

LO

| Outp ut Le ak age C urren t

Output Lo w Vo ltag e

OL

V

V

OH

Output High Voltage IOH = -4mA 2.4

NOTES:

1. At Vcc

< 2.0V input leakages are undefined.

(1)

VCC = 5.5V, VIN = 0V to V

IH

, V

OUT

CE - V
I

OL

= 6mA

I

OL

= 8mA

= 0V to V

(VCC = 5V ± 10%)

CC

CC

___

___

___

___

7134SA 7134LA

10
10

0.4

0.5

___

___

___

___

___

2.4

UnitMin. Max. Min. Max.

5µA
5µA

0.4 V

0.5 V

___

V

2720 t bl 0 5

3

IDT7134SA/LA
High-Speed 4K x 8 Dual-Port Static SRAM Military, Industrial and Commercial Temperature Ranges

DC Electrical Characteristics Over the Operating

(1,2)

T emperature and Supply Voltage Range

Symbol Parameter Test Condition Version Typ. Max. Typ. Max. Typ. Max. U nit

CC

Dynam ic O p e rati ng

I

Current
(Both Ports Active)

SB1

Stand b y Cu rre nt

I

(Both Po rts - TTL
Lev e l Inp uts )

SB2

Stand b y Cu rre nt

I

(One P ort - TTL
Lev e l Inp uts )

I

SB3

Full Standby Current
(Both P o r ts ­CMOS Le v e l Inp uts )

I

SB4

Full Standby Current
(One P ort ­CMOS Le v e l Inp uts )

IL

CE = V
Outputs Disabled

(3)

MAX

f = f

CE

L

and CER = V

f = f

MAX

"A"

= VIL and CE

CE

Active Port Outputs Disabled,

(3)

f=f

MAX

Both Ports CE

CE

R

> VCC - 0. 2V

V

IN

> VCC - 0.2V o r

IN

< 0.2V, f = 0

V

One P o rt CE

CE

"B"

> VCC - 0.2V

V

IN

> VCC - 0.2V or VIN < 0.2V
Active Port Outputs Disabled,
f = f

MAX

IH

(3)

"B"

= V

IH

L

and

(3)

"A"

or

(3)

(VCC = 5.0V ± 10%)

7134X20

Com'l Only

COM'L SALA170

MIL &
IND

SA
LA

170

____
____

280
240

____
____

COM'L SALA252510080252580

____

MIL &
IND

SA
LA

COM'L SALA105

MIL &
IND

SA
LA

COM'L SALA1.0

MIL &
IND

SA
LA

COM'L SALA105

MIL &
IND

SA
LA

____

____

____

180

105

1509595

____

____

____

____

0.2154.5

____

____

____

____

170

105

1309595

____

____

____

____

7134X25
Com' l, I nd
& Mi li t ary

160
160

160
160

25251008025

9595210

1.0

0.2154.0

1.0

0.23010

9595210

280
220

310
260

50

180
1408585

1708585

170
1208585

1508585

7134X35

Com'l, Ind

& Military

150

260

150

210

150

300

150

250

25
25

25

170
130

200
160

1.0

0.2154.0

1.0

0.23010
160

110
190

130

7545mA

75
55

mA

mA

mA

mA

2720 tbl 06a

7134X45
Com' l &

Military

7134X55

Com'l, Ind

& Mi li ta ry

7134X70
Com' l &

Military

Symbol Parameter Test Condition Version Typ. Max. Typ. Max. Typ. Max. Unit

CC

Dynamic Operating

I

Current
(Both Ports Active)

SB1

Standby Current

I

(Both Ports - TTL
Lev el Inp uts)

SB2

Standby Current

I

(One Po rt - TTL
Lev el Inp uts)

SB3

Full Standby Current

I

(Bo th P o rts ­CMO S Le v e l Inp u ts )

SB4

Full Standby Current

I

(One Po rt ­CMO S Le v e l Inp u ts )

IL

CE = V
Outputs Disabled

(3)

MAX

f = f

L

and CER = V

CE

f = f

MAX

"A"

= VIL and CE

CE

Active Port Outputs Disabled,

(3)

MAX

f=f

Bo th Po rts CE

R

> VCC - 0.2V

CE

IN

> VCC - 0.2 V o r

V

IN

< 0.2V, f = 0

V

One Po rt CE

"B"

> VCC - 0.2V

CE

IN

> VCC - 0.2V or VIN < 0.2V

V
Active Port Outputs Disabled,

MAX

f = f

IH

(3)

"B"

= V

IH

L

and

(3)

"A"

or

(3)

COM'L SALA140

MIL &
IND

SALA140

COM'L SALA252570

MIL &
IND

SALA252570

COM'L SALA7575160

MIL &
IND

SALA7575190

COM'L SALA1.0

MIL &
IND

SALA1.0

COM'L SALA7575150

MIL &
IND

SALA7575180

240

140

200
280

140

240

1307575

1507575

0.2154.0

0.23010

1007575

1207575

40

50

140

240

140

200

140

270

140

220

2525704025

2525705025

160
1307575

180
1507575

1.0

0.2154.0

1.0

0.23010
150

1007575
170

1207575

140

240

140

200

140

270

140

220

25

25

160
130

180
150

1.0

0.2154.0

1.0

0.23010
150

100
170

120

mA

7040mA

70
50

mA

mA

mA

NOTES:

1. 'X' in part number indicates power rating (SA or LA).

CC = 5V, TA = +25°C for typical, and parameters are not production tested.

2. V

MAX = 1/tRC = All inputs cycling at f = 1/tRC (except Output Enable). f = 0 means no address or control lines change. Applies only to inputs at CMOS level standby ISB3.

3. f

4

2720 tbl 06b

IDT7134SA/LA
High-Speed 4K x 8 Dual-Port Static SRAM Military, Industrial and Commercial Temperature Ranges

Data Retention Characteristics Over All Temperature Ranges

(LA Version Only) VLC = 0.2V, VHC = VCC - 0.2V

Symbol Parameter Test Condition Min. Typ.

V

DR

I

CCDR

CDR

t

(3)

t

R

(3)

V

CC

fo r Da ta Re ten ti o n VCC = 2V 2.0

Data Rete ntio n Current

CE >

V

HC

VIN > VHC or < V

MIL. & IND.

LC

COM'L.
Chip Deselect to Data Rete ntio n Time 0
Operation Recovery Time t

___

___

(2)

RC

NOTES:

CC = 2V, TA = +25°C, and are not production tested.

1. V

RC = Read Cycle Time.

2. t

3. This parameter is guaranteed by device characterization, but not production tested.

(1)

Max. Unit

___ ___

100 4000
100 1500

___ ___

___ ___

2720 tbl 07

Data Retention Waveform

DATARETENTION MODE

V

µA

ns
ns

V

CC

CE

AC T est Conditions

Inp ut Pul se Le v e ls
Inp ut Ris e/ Fal l Time s
Inp ut Timing Re fe re nc e L ev e ls
Outp ut Refe re nc e Le v el s
Outp ut Lo ad

DATA

OUT

775Ω

+5V

t

CDR

V

IH

1250Ω

30pF

GND to 3.0V

5ns

1.5V

1.5V

Fi g ure s 1 and 2

2720 tbl 08

DR

≥ 2V

V

V

DR

4.5V4.5V
t

R

V

IH

2720 drw 05

+5V

1250Ω

OUT

DATA

775Ω

5pF *

2720 drw 06

,

Figure 1. AC Output Test Load Figure 2. Output Test Load

LZ, tHZ, tWZ, tOW)

(for t

*Including scope and jig

5

2720 drw 07

,

IDT7134SA/LA
High-Speed 4K x 8 Dual-Port Static SRAM Military, Industrial and Commercial Temperature Ranges

AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage

7134X20

Com'l Only

READ CYCLE

t
t
t
t
t
t
t
t
t

RC

AA

ACE

AOE

OH

LZ

HZ

PU

PD

Re ad Cyc l e Ti me 20

Address Acce ss Time
Chip Enable Access Time
Output E nab le A cc e s s Tim e
Output Hold from Address Change 0
Output Lo w-Z Time
Outp ut Hi g h-Z Tim e
Chip Enable to Po wer Up Time
Chip Disab l e to Po we r Down Tim e

(1,2)

(1,2)

(2)

(2)

____

____

____

0

____

0

____

7134X45
Com'l &
Military

(3)

____

____

____

____

7134X25

Com'l, Ind

& Mil itar y

7134X35
Com'l, Ind
& Military

UnitSymbol Parameter Min.Max.Min.Max.Min.Max.

25
20
20
15

____

____

____

0
0

15

____

0

20

____

____

____

____

____

35
25
25
15

____

____

____

0
0

15

____

0

25

____

7134X55

Com'l, Ind

& Military

7134X70
Com'l &
Military

____

35 ns
35 ns
20 ns

____

____

20 ns

____

35 ns

2 720 tbl 09a

ns

ns
ns

ns

UnitSymbol Parameter Min.Max.Min.Max.Min.Max.

READ CYCLE

t
t
t
t
t
t
t
t
t

RC

AA

ACE

AOE

OH

LZ

HZ

PU

PD

Read Cyc le Time 45
Address Acce ss Time
Chip Enable Access Time
Output Enable Acce ss Time
Output Hold from Address Change 0
Output Low-Z Time
Output High-Z Time
Chip Enabl e to Po we r Up Time
Chi p Disab le to Po we r Down Time

(1,2)

(1,2)

(2)

(2)

____

____

____

5

____

0

____

____

45
45
25

____

____

20

____

45

NOTES:

1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).

2. This parameter is guaranteed by device characterization, but is not production tested.

3. 'X' in part number indicates power rating (SA or LA).

____

____

____

____

____

55

0
5

0

____

____

____

____

70

55
55
30

____

____

____

0
5

25

____

0

50

____

____

70 ns
70 ns
40 ns

____

____

30 ns

____

50 ns

2720 t bl 0 9b

ns

ns
ns

ns

6

IDT7134SA/LA

t

High-Speed 4K x 8 Dual-Port Static SRAM Military, Industrial and Commercial Temperature Ranges

Timing Waveform of Read Cycle No. 1, Either Side

t

RC

(1,2,4)

ADDRESS

(5)

t

t

OH

AA

t

OH

DATA

OUT

PREVIOUS DATA VALID DATA VALID

Timing Waveform of Read Cycle No. 2, Either Side

ACE

CE

(4)

t

AOE

OE

(1)

t

LZ

OUT

DATA

(1)

t

t

PU

CURRENT

I

CC

I

SB

NOTES:

1. Timing depends on which signal is asserted last, OE or CE.

2. Timing depends on which signal is de-asserted first, OE or CE.

3. R/W = V

IH.

4. Start of valid data depends on which timing becomes effective, t

5. tAA for RAM Address Access and tSAA for Semaphore Address Access.

LZ

AOE, tACE or tAA

(1,3)

VALID DATA

2720 drw 08

(2)

t

HZ

(2)

t

HZ

(4)

t

PD

50%50%

2720drw 09

7

IDT7134SA/LA
High-Speed 4K x 8 Dual-Port Static SRAM Military, Industrial and Commercial Temperature Ranges

AC Electrical Characteristics Over the

7134X20

Com'l Only

____

0

____

3

____

____

7134X45
Com ' l &

Military

____

3

____

3

____

____

(5)

____

____

____

____

____

____

____

____

____

____

____

____

____

____

____

____

____

____

7134X25

Com'l, Ind

& Mil itary

25
20
20

0

20

0

15

15

____

0

15

____

3
40
30

____

____

____

____

____

____

____

____

____

____

____

7134X55

Com'l, Ind

& Military

55
50
50

0

50

0

25

20

____

3
20

____

3
70
45

____

____

____

____

____

____

____

____

____

____

____

Operating Temperature and Supply Voltage

Symbol Parameter

WRI TE CY CL E

t

WC

EW

t
t

AW

AS

t

WP

t
t

WR

t

DW

HZ

t
t

DH

WZ

t
t

OW

t

WDD

DDD

t

Symbol Parameter

WRI TE CY CL E

t

WC

EW

t
t

AW

t

AS

WP

t
t

WR

t

DW

HZ

t
t

DH

WZ

t
t

OW

t

WDD

DDD

t

NOTES:

1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2).

2. This parameter is guaranteed by device characterization, but is not production tested.

3. The specification for t
temperature, the actual t

4. Port-to-port delay through RAM cells from writing port to reading port, refer to “Timing Waveform of Write with Port-to-Port Read”.

5. 'X' in part number indicates power rating (SA or LA).

DDD = 35ns for military temperature range.

6. t

Write Cy c le Time 20

Chip Enab le to E nd-o f-Write 15

Address Valid to End-of-Write 15
Address Set-up Time 0
Write Pulse Width 15

Write Recovery Time 0
Data Vali d to End -of-Write 15
Outp ut Hi g h-Z Tim e
Data Hold Ti m e

Write Enable to Output in High-Z
Output A cti v e fro m E nd -o f-Write

Write Pulse to Data Delay

Write Data Valid to Re ad Data Del ay

(1,2)

(3)

(1,2)

(1, 2,3)

(4)

(4,6)

Write Cy c le Time 45
Chip Enab le to E nd-o f-Write 40

Address Valid to End-of-Write 40

Address Set-up Time 0

Write Pulse Width 40

Write Recovery Time 0
Data Vali d to End -of-Write 20
Outp ut Hi g h-Z Tim e
Data Hold Ti m e

Write Enable to Output in High-Z
Output A cti v e fro m E nd -o f-Write

Write Pulse to Data Delay

Write Data Valid to Re ad Data Del ay

DH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values will vary over voltage and

DH will always be smaller than the actual tOW.

(1,2)

(3)

(1,2)

(1, 2,3)

(4)

(4,6)

7134X35
Com'l, Ind
& Military

UnitMin. Max. Min. Max. Min. Max.

35
30
30

0

25

0

20

15

____

3

15

____

3
50
30

____

____

____

____

____

____

____

____

____

20 ns

____

20 ns

____

60 ns
35 ns

2 720 tbl 10a

ns
ns
ns
ns
ns
ns
ns

ns

ns

7134X70
Com'l &

Military

UnitMin. Max. Min. Max. Min. Max.

70
60
60

0

60

0

30

25

____

3
25

____

3
80
55

____

____

____

____

____

____

____

____

____

30 ns

____

30 ns

____

90 ns
70 ns

2720 tbl 10b

ns
ns
ns
ns
ns
ns
ns

ns

ns

8

IDT7134SA/LA
High-Speed 4K x 8 Dual-Port Static SRAM Military, Industrial and Commercial Temperature Ranges

Timing Waveform of Write with Port-to-Port Read

t

WC

ADDR

R/W

"A"

"A"

(1)

MATCH

t

WP

t

DW

(1,2,3)

t

AW

DATA

IN "A"

ADDR

"B"

DATA

OUT "B"

NOTES:

1. Write cycle parameters should be adhered to, in order to ensure proper writing.

L = CER = VIL. OE"B" = VIL.

2. CE

3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".

VALID

t

WDD

MATCH

t

DDD

Timing Waveform of Write Cycle No. 1, R/W Controlled Timing

t

WC

ADDRESS

(6)

t

AS

OE

(3)

t

t

AW

WR

VALID

2720 drw 10

(1,5,8)

CE

t

WP

(2)

(7)

t

HZ

R/W

(7)

t

(4)

WZ

t

DW

t

DH

t

OW

(7)

t

LZ

DATA

OUT

DATA

IN

NOTES:

1. R/W or CE must be HIGH during all address transitions.

2. A write occurs during the overlap (t

WR is measured from the earlier of CE or R/W going to VIH to the end-of-write cycle.

3. t

4. During this period, the I/O pins are in the output state, and input signals must not be applied.

5. If the CE = V

6. Timing depends on which enable signal (CE or R/W) is asserted last.

7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load
(Figure 2).

8. If OE = V
for the required t

IL transition occurs simultaneously with or after the R/W = VIL transition, the outputs remain in the High-impedance state.

IL during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off data to be placed on the bus

DW. If OE = VIH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP.

EW or tWP) of a CE =VIL and R/W = VIL.

9

(4)

t

HZ

(7)

2720 drw 11

IDT7134SA/LA

1

High-Speed 4K x 8 Dual-Port Static SRAM Military, Industrial and Commercial Temperature Ranges

Timing Waveform of Write Cycle No. 2, CE Controlled Timing

t

WC

(1,4)

ADDRESS

t

AW

CE

(5)

t

AS

(2)

t

EW

t

WR

(3)

R/W

t

DW

DATA

IN

NOTES:

1. R/W or CE must be HIGH during all address transitions.

2. A write occurs during the overlap (t

WR is measured from the earlier of CE or R/W going HIGH to the end-of-write cycle.

3. t

4. If the CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state.

5. Timing depends on which enable signal (CE or R/W) is asserted last.

EW or tWP) of a CE =VIL and R/W = VIL.

t

DH

2720 drw 12

Functional Description

The IDT7134 provides two ports with separate control, address,

and I/O pins that permit independent access for reads or writes to any
location in memory. These devices have an automatic power down
feature controlled by CE. The CE controls on-chip power down circuitry
that permits the respective port to go into standby mode when not
selected (CE HIGH). When a port is enabled, access to the entire
memory array is permitted. Each port has its own Output Enable
control (OE). In the read mode, the port’s OE turns on the output drivers
when set LOW. Non-contention READ/WRITE conditions are illustrated
inTruth Table I.

Truth Table I – Read/Write Control

Left or Right Port

R/W

CE OE

X H X Z Port Deselected and in Power-Down

XHX Z

LLXDATAINData o n p o rt w ri tte n in to memo r y
HLLDATA
X X H Z High impedance o utputs

NOTE:

0L - A11L ≠ A0R - A11R

1. A
"H" = VIH, "L" = VIL, "X" = Don’t Care, and "Z" = High Impedance

(1)

D

0-7

Mode, I

R

= CEL = H, P o w er Do wn

CE

Mode I

OUT

Data in memory output on port

SB2

SB1

or I

or I

Function

SB4

SB3

2720 tb l 1

10

IDT7134SA/LA
High-Speed 4K x 8 Dual-Port Static SRAM Military, Industrial and Commercial Temperature Ranges

Ordering Information

IDT XXXX A 999 A A

Device Type Power Speed Package Process/

NOTES:

1. Contact your local sales office for industrial temp. range for other speeds, packages and powers.

2. Green parts available. For specific speeds, packages and powers contact your local sales office.

A

Temperature

Range

Blank

(1)

I
B

(2)

G
P

C
J
L48
F

20
25
35
45
55
70

LA
SA

7134

Commercial(0°Cto+70°C)
Industrial (-40°Cto+85°C)
Military (-55°C to +125°C)
Compliant to MIL-PRF-38535 QML

Green
48-pin Plastic DIP (P48-1)

48-pin Ceramic DIP (C48-2)
52-pin PLCC (J52-1)
48-pin LCC (L48-1)
48-pin Ceramic Flatpack (F48-1)

Commercial Only
Commercial, Industrial & Military
Commercial, Industrial & Military
Commercial & Military
Commercial, Industrial & Military
Commercial & Military

Low Power
Standard Power

32K (4K x 8-Bit) Dual-Port RAM

Datasheet Document History

,

Speed in nanoseconds

2720 drw 13

03/25/99: Initiated datasheet document history

Converted to new format
Cosmetic and typographical corrections

Pages 2 Added additional notes to pin configurations
060/9/99: Changed drawing format
10/01/99: Added Industrial Temperature Ranges and removed corresponding notes
11/10/99: Replaced IDT logo
12/22/99: Page 1 Made corrections to drawing
03/03/00: Corrected block diagram and pin configurations

Changed ±500mV to 0mV

01/12/00: Pages 1 2 Moved "Description to page 2 and adjusted page layout

Page 1 Added "LA only)" to paragraph

Page 2 Fixed P48-1 package description

Page 3 Increased storage temperature parameters

Clarified TA parameter
Page 4 DC Electrical parameters–changed wording from "open" to "disabled"
Page 10 Fixed Truth Table specification in "Functional Description" paragraph

01/17/06: Page 1 Added green availability to features

Page 11 Added green indicator to ordering information
Page 1 & 11 Replaced old IDTTM with new IDTTM logo

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San Jose, CA 95138 fax: [phone] [e-mail]

www.idt.com

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11