Datasheet IDT71256L120DB, IDT71256L120LB, IDT71256L120PB, IDT71256L120TDB, IDT71256L120YB Datasheet (Integrated Device Technology Inc)
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CMOS STATIC RAM
256K (32K x 8-BIT)
Integrated Device Technology, Inc.
FEATURES:
• High-speed address/chip select time
— Military: 25/30/35/45/55/70/85/100/120/150ns (max.)
— Commercial: 20/25/35/45ns (max.) Low Power only.
• Low-power operation
• Battery Backup operation — 2V data retention
• Produced with advanced high-performance CMOS
technology
• Input and output directly TTL-compatible
• Available in standard 28-pin (300 or 600 mil) ceramic
DIP, 28-pin (600 mil) plastic DIP, 28-pin (300 mil) SOJ
and 32-pin LCC
• Military product compliant to MIL-STD-883, Class B
IDT71256S
IDT71256L
DESCRIPTION:
The IDT71256 is a 262,144-bit high-speed static RAM
organized as 32K x 8. It is fabricated using IDT’s highperformance, high-reliability CMOS technology.
Address access times as fast as 20ns are available with
power consumption of only 350mW (typ.). The circuit also
offers a reduced power standby mode. When CS goes HIGH,
the circuit will automatically go to, and remain in, a low-power
standby mode as long as CS remains HIGH. In the full standby
mode, the low-power device consumes less than 15µW,
typically. This capability provides significant system level
power and cooling savings. The low-power (L) version also
offers a battery backup data retention capability where the
circuit typically consumes only 5µW when operating off a 2V
battery.
The lDT71256 is packaged in a 28-pin (300 or 600 mil)
ceramic DIP, a 28-pin 300 mil J-bend SOlC, and a 28-pin (600
mil) plastic DIP, and 32-pin LCC providing high board-level
packing densities.
The IDT71256 military RAM is manufactured in compliance
with the latest revision of MIL-STD-883, Class B, making it
ideally suited to military temperature applications demanding
the highest level of performance and reliability.
FUNCTIONAL BLOCK DIAGRAM
A
0
ADDRESS
DECODER
A14
I/O 0
INPUT
DATA
CIRCUIT
I/O
7
CS
OE
WE
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
CONTROL
CIRCUIT
262,144 BIT
MEMORY ARRAY
I/O CONTROL
MILITARY AND COMMERCIAL TEMPERATURE RANGES AUGUST 1996
1996 Integrated Device Technology, Inc. DSC-2946/7
7.2
V
CC
GND
2946 drw 01
1
IDT71256 S/L
CMOS STATIC RAM 256K (32K x 8-BIT) MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
A
A
I/O
I/O
I/O
GND
INDEX
A6
A5
A4
A3
A2
A1
A
0
NC
I/O0
CS
CS
(1)
OE
OE
I/O Function
IN Write Data
(1)
1
14
2
12
3
A
7
4
A
6
5
A
5
A
4
A
3
A
2
A
1
A
0
0
1
2
6
7
8
9
10
11
12
13
14
D28-3
P28-1
P28-2
D28-1
SO28-5
28
27
26
25
24
23
22
21
20
I/O
19
18
I/O
17
I/O
16
I/O
15
I/O
2946 drw 02
V
WE
A
A
A
A
OE
A
CS
CC
13
8
9
11
10
7
6
5
4
3
DIP/SOJ
TOP VIEW
TRUTH TABLE
WE
WE
X H X High-Z Standby (ISB)
XVHC X High-Z Standby (ISB1)
H L H High-Z Output Disabled
HLLDOUT Read Data
LLXD
NOTE: 2946 tbl 02
1. H = VIH, L = VIL, X = Don’t Care
ABSOLUTE MAXIMUM RATINGS
Symbol Rating Com’l. Mil. Unit
TERM Terminal Voltage –0.5 to +7.0 –0.5 to +7.0 V
V
with Respect
to GND
A Operating 0 to +70 –55 to +125 °C
7
A
32
4
5
6
7
8
9
10
11
12
13
15 16 17 18 19
1
I/O
A12
2
I/O
14
A
1
L32-1
GND
NC
32 31
NC
WE
VCC
2014
3
I/O4I/O
30
29
28
27
26
25
24
23
22
21
5
13
A
2946 drw 03
I/O
A
A
A
NC
OE
A
CS
I/O
I/O
8
9
11
10
7
6
T
Temperature
BIAS Temperature –55 to +125 –65 to +135 °C
T
Under Bias
STG Storage –55 to +125 –65 to +150 °C
T
Temperature
PT Power Dissipation 1.0 1.0 W
OUT DC Output 50 50 mA
I
Current
NOTE: 2946 tbl 03
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
32-Pin LCC
TOP VIEW
PIN DESCRIPTIONS
Name Description
A0–A14 Addresses
I/O0–I/O7 Data Input/Output
CS
WE
OE
GND Ground
CC Power
V
Chip Select
Write Enable
Output Enable
CAPACITANCE (TA = +25°C, f = 1.0MHz)
Symbol Parameter
CIN Input Capacitance VIN = 0V 11 pF
C
I/O I/O Capacitance VOUT = 0V 11 pF
NOTE: 2946 tbl 04
1. This parameter is determined by device characterization, but is not
production tested.
2946 tbl 01
7.2 2
(1)
Conditions Max. Unit
IDT71256S/L
CMOS STATIC RAM 256K (32K x 8-BIT) MILITARY AND COMMERCIAL TEMPERATURE RANGES
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Grade Temperature GND VCC
Military –55°C to +125°C 0V 5.0V ± 10%
Commercial 0°C to +70°C 0V 5.0V ± 10%
2946 tbl 05
DC ELECTRICAL CHARACTERISTICS
(1, 2)
RECOMMENDED DC OPERATING
CONDITIONS
Symbol Parameter Min. Typ. Max. Unit
VCC Supply Voltage 4.5 5.0 5.5 V
GND Supply Voltage 0 0 0 V
VIH Input High Voltage 2.2 — 6.0 V
IL Input Low Voltage –0.5
V
NOTE: 2946 tbl 06
1. VIL (min.) = –3.0V for pulse width less than 20ns, once per cycle.
(1)
— 0.8 V
(VCC = 5.0V ± 10%, VLC = 0.2V, VHC = VCC - 0.2V)
71256S/L20 71256S/L25 71256S/L30 71256S/L35
Symbol Parameter Power Com’l. Mil. Com’l. Mil. Com’l. Mil. Com’l. Mil. Unit
I
CC Dynamic Operating Current S — — — 150 — 145 — 140 mA
CS
≤ V
IL, Outputs Open
VCC = Max., f = fMAX
SB Standby Power Supply S — — — 20 — 20 — 20 mA
I
Current (TTL Level)
CS
≥ V
IH, VCC = Max., L 3 — 3 3 — 3 3 3
Outputs Open, f = fMAX
ISB1 Full Standby Power Supply S — — — 20 — 20 — 20 mA
Current (CMOS Level)
CS
≥ V
HC, VCC = Max., f = 0 L 0.4 — 0.4 1.5 — 1.5 0.4 1.5
(2)
L 135 — 115 130 — 125 105 120
(2)
71256S/L45 71256S/L55 71256S/L70 71256S/L85
(3)
71256S/L100
(3)
Symbol Parameter Power Com’l. Mil. Com’l. Mil. Com’l. Mil. Com’l. Mil. Com'l. Mil. Unit
CC Dynamic Operating Current S — 135 — 135 — 135 — 135 — 135 mA
I
CS
≤ V
IL, Outputs Open
VCC = Max., f = fMAX
SB Standby Power Supply S — 20 — 20 — 20 — 20 — 20 mA
I
(2)
L 100 115 — 115 — 115 — 115 — 115
Current (TTL Level)
CS
≥ V
IH, VCC = Max., L 3 3 — 3 — 3 — 3 — 3
Outputs Open, f = fMAX
(2)
ISB1 Full Standby Power Supply S — 20 — 20 — 20 — 20 — 20 mA
Current (CMOS Level)
CS
≥ V
HC, VCC = Max., f = 0 L 0.4 1.5 — 1.5 — 1.5 — 1.5 — 1.5
NOTES: 2946 tbl 07
1. All values are maximum guaranteed values.
MAX = 1/tRC, all address inputs cycling at fMAX; f = 0 means no address pins are cycling.
2. f
3. Also available: 120 and 150 ns military devices.
7.2 3
IDT71256 S/L
CMOS STATIC RAM 256K (32K x 8-BIT) MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC TEST CONDITIONS
Input Pulse Levels GND to 3.0V
Input Rise/Fall Times 5ns
Input Timing Reference Levels 1.5V
Output Reference Levels 1.5V
AC Test Load See Figures 1 and 2
2946 tbl 08
DATA
OUT
255
Ω
Figure 1. AC Test Load
5V
480
30pF*
Ω
2946 drw 04
DATA
*Includes scope and jig capacitances
OUT
Ω
255
Figure 2. AC Test Load
CLZ, tOLZ, tCHZ, tOHZ, tOW, tWHZ)
(for t
5V
480
5pF*
Ω
2946 drw 05
DC ELECTRICAL CHARACTERISTICS
VCC = 5.0V ± 10%
IDT71256S IDT71256L
Symbol Parameter Test Condition Min. Typ. Max. Min. Typ. Max. Unit
LI| Input Leakage Current VCC = Max., MIL. — — 10 — — 5 µA
|I
VIN = GND to VCC COM’L. — — 5 — — 2
|I
LO| Output Leakage Current VCC = Max., CS = VIH, MIL. — — 10 — — 5 µA
VOUT = GND to VCC COM’L. — — 5 — — 2
OL Output Low Voltage IOL = 8mA, VCC = Min. — 0.4 — — 0.4 V
V
IOL = 10mA, VCC = Min. — — 0.5 — — 0.5
OH Output High Voltage IOH = –4mA, VCC = Min. 2.4 — — 2.4 — — V
V
2946 tbl 09
DATA RETENTION CHARACTERISTICS OVER ALL TEMPERATURE RANGES
(L Version Only) VLC = 0.2V, VHC = VCC – 0.2V
(1)
Typ.
V
CC @VCC @
Symbol Parameter Test Condition Min. 2.0v 3.0V 2.0V 3.0V Unit
DR VCC for Data Retention — 2.0 — — — — V
V
CCDR Data Retention Current MIL. — — — 500 800 µA
I
COM’L. — — — 120 200
t
CDR Chip Deselect to Data
CS
≥ VHC 0————ns
Retention Time
(3)
R
t
NOTES: 2946 tbl 10
1. TA = +25°C.
RC = Read Cycle Time.
2. t
3. This parameter is guaranteed, but not tested.
Operation Recovery Time tRC
7.2 4
(2)
————ns
Max.
IDT71256S/L
CMOS STATIC RAM 256K (32K x 8-BIT) MILITARY AND COMMERCIAL TEMPERATURE RANGES
LOW VCC DATA RETENTION WAVEFORM
DATA
RETENTION
VCC
CS
4.5V 4.5V
IH VIH
V
MODE
V
DR≥2V
VDR
tRtCDR
2946 drw 06
AC ELECTRICAL CHARACTERISTICS (VCC = 5.0V ± 10%, All Temperature Ranges)
71256S25 71256S30
71256L20
(1)
71256L25 71256L30
Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
Read Cycle
tRC Read Cycle Time 20 — 25 — 30 — 35 — 45 — ns
tAA Address Access Time — 20 — 25 — 30 — 35 — 45 ns
tACS Chip Select Access Time — 20 — 25 — 30 — 35 — 45 ns
(2)
tCLZ
tCHZ
Chip Select to Output in Low-Z 5 — 5 — 5 — 5 — 5 — ns
(2)
Chip Deselect to Output in High-Z — 10 — 11 — 15 — 15 — 20 ns
tOE Output Enable to Output Valid — 10 — 11 — 13 — 15 — 20 ns
(2)
tOLZ
tOHZ
Output Enable to Output in Low-Z 2 — 2 — 2 — 2 — 0 — ns
(2)
Output Disable to Output in High-Z 2 8 2 10 2 12 2 15 — 20 ns
tOH Output Hold from Address Change 5 — 5 — 5 — 5 — 5 — ns
Write Cycle
tWC Write Cycle Time 20 — 25 — 30 — 35 — 45 — ns
tCW Chip Select to End-of-Write 15 — 20 — 25 — 30 — 40 — ns
tAW Address Valid to End-of-Write 15 — 20 — 25 — 30 — 40 — ns
tAS Address Set-up Time 0 — 0 — 0 — 0 — 0 — ns
tWP Write Pulse Width 15 — 20 — 25 — 30 — 35 — ns
tWR Write Recovery Time 0 — 0 — 0 — 0 — 0 — ns
tDW Data to Write Time Overlap 11 — 13 —14—15— 20—ns
(2)
tWHZ
Write Enable to Output in High-Z — 10 — 11 — 15 — 15 — 20 ns
tDH Data Hold from Write Time 0 — 0 — 0 — 0 — 0 — ns
(2)
t
OW
NOTES: 2946 tbl 11
1. 0° to +70°C temperature range only.
2. This parameter guaranteed by device characterization, but is not production tested.
3. –55° to +125°C temperature range only.
Output Active from End-of-Write 5 — 5 — 5 — 5 — 5 — ns
(3)
71256S35 71256S45
(3)
71256L35 71256L45
7.2 5
IDT71256 S/L
CMOS STATIC RAM 256K (32K x 8-BIT) MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS (VCC = 5.0V ± 10%, All Temperature Ranges)
71256S55
71256L55
(1)
(1)
71256S70
71256L70
Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Unit
Read Cycle
tRC Read Cycle Time 55 — 70 — 85 — 100 — ns
tAA Address Access Time — 55 — 70 — 85 — 100 ns
tACS Chip Select Access Time — 55 — 70 — 85 — 100 ns
(2)
tCLZ
tCHZ
Chip Deselect to Output in Low-Z 5 — 5 — 5 — 5 — ns
(2)
Output Enable to Output in Low-Z — 25 — 30 — 35 — 40 ns
tOE Output Enable to Output Valid — 25 — 30 — 35 — 40 ns
(2)
tOLZ
tOHZ
Output Enable to Output in Low-Z 0 — 0 — 0 — 0 — ns
(2)
Output Disable to Output in High-Z 0 25 0 30 — 35 — 40 ns
tOH Output Hold from Address Change 5 — 5 — 5 — 5 — ns
Write Cycle
tWC Write Cycle Time 55 — 70 — 85 — 100 — ns
tCW Chip Select to End-of-Write 50 — 60 — 70 — 80 — ns
tAW Address Valid to End-of-Write 50 — 60 — 70 — 80 — ns
tAS Address Set-up Time 0 — 0 — 0 — 0 — ns
tWP Write Pulse Width 40 — 45 — 50 — 55 — ns
tWR Write Recovery Time 0 — 0 — 0 — 0 — ns
tDW Data to Write Time Overlap 25 — 30 — 35 — 40 — ns
tDH Data Hold from Write Time (WE)0—0—0—0—ns
(2)
tWHZ
tOW
NOTES: 2946 tbl 11
1. –55°C to +125°C temperature range only.
2. This parameter guaranteed by device characterization, but is not production tested.
3. Also available: 120 and 150 ns military devices.
Write Enable to Output in High-Z — 25 — 30 — 35 — 40 ns
(2)
Output Active from End-of-Write 5 — 5 — 5 — 5 — ns
(1)
(1)
71256S85
71256L85
(1)
(1)
71256S100
71256L100
(1,3)
(1,3)
7.2 6
IDT71256S/L
CMOS STATIC RAM 256K (32K x 8-BIT) MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF READ CYCLE NO. 1
ADDRESS
tAA
OE
(5)
tOLZ
CS
tACS
(5)
tCLZ
OUT
DATA
TIMING WAVEFORM OF READ CYCLE NO. 2
tRC
(1)
tRC
tOE
(1, 2, 4)
tOH
tOHZ
tCHZ
(5)
(5)
2946 drw 07
ADDRESS
tAA
tOH
DATA OUT
TIMING WAVEFORM OF READ CYCLE NO. 3
CS
t
ACS
(5)
t
CLZ
DATA
OUT
NOTES:
1.WE is HIGH for Read cycle.
2. Device is continuously selected, CS is LOW.
3. Address valid prior to or coincident with CS transition LOW.
4.OE is LOW.
5. Transition is measured ±200mV from steady state.
(1, 3, 4)
tOH
t
CHZ
2946 drw 08
(5)
2946 drw 09
7.2 7
IDT71256 S/L
CMOS STATIC RAM 256K (32K x 8-BIT) MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE CYCLE NO. 1 (
tWC
ADDRESS
OE
tAW
CS
tWP
WE
DATA OUT
DATA IN
tAS
(4)
tWHZ
(6)
WEWE CONTROLLED TIMING)
(7)
tDW
tWR
DH
t
tOW
(1, 2, 3, 5, 7)
tOHZ
(6)
(4)
2946 drw 10
TIMING WAVEFORM OF WRITE CYCLE NO. 2 (
t
WC
CSCS CONTROLLED TIMING)
(1, 2, 3, 5)
ADDRESS
t
AW
CS
(7)
t
t
AS
CW
t
t
WR
WE
t
DW
DATA
IN
NOTES:
1.WE or CS must be HIGH during all address transitions.
2. A write occurs during the overlap of a LOW CS and a LOW WE.
3. t
WR is measured from the earlier of
4. During this period, I/O pins are in the output state so that the input signals must not be applied.
5. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state.
6. Transition is measured ±200mV from steady state.
7. If OE is LOW during a WE controlled write cycle, the write pulse width must be the larger of t
to be placed on the bus for the required t
be as short as the spectified t
CS
WP. For a
or WE going HIGH to the end of the write cycle.
DW. If
OE
CS
is HIGH during a WE controlled write cycle, this requirement does not apply and the write pulse can
controlled write cycle, OE may be LOW with no degradation to tCW.
WP or (tWHZ + tDW) to allow the I/O drivers to turn off and data
t
DH2
2946 drw 11
7.2 8
IDT71256S/L
CMOS STATIC RAM 256K (32K x 8-BIT) MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDT
71256
Device
Type
X
Power
XXX
Speed
XXX
Package
X
Process/
Temperature
Range
Blank
B
TD
D
Y
P
L
20
25
30
35
45
55
70
85
100
120
150
Commercial (0°C to +70°C)
Military (–55°C to +125°C)
Compliant to MIL-STD-883, Class B
300 mil CERDIP (D28-3)
600 mil CERDIP (D28-1)
300 mil SOJ (SO28-5)
600 mil Plastic DIP (P28-1)
Leadless Chip Carrier (32-pin) (L32-1)
Commercial Only
Military Only
Military Only
Military Only
Speed in nanoseconds
Military Only
Military Only
Military Only
Military Only
S
L
Standard Power
Low Power
2946 drw 12
7.2 9
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