Datasheet IDT71028S12Y, IDT71028S15Y, IDT71028S17Y, IDT71028S20Y Datasheet (Integrated Device Technology Inc)

Integrated Device Technology, Inc.

CMOS STATIC RAM
1 MEG (256K x 4-BIT)

IDT71028

FEATURES:

• 256K x 4 advanced high-speed CMOS static RAM

• Equal access and cycle times
— Commercial: 12/15/17/20ns

• One Chip Select plus one Output Enable pin

• Bidirectional data Inputs and outputs directly

TTL-compatible

• Low power consumption via chip deselect

• Available in 400 mil Plastic SOJ package

FUNCTIONAL BLOCK DIAGRAM

A0

DESCRIPTION:

The IDT71028 is a 1,048,576-bit high-speed static RAM
organized as 256K x 4. It is fabricated using IDT’s high­perfomance, high-reliability CMOS technology. This state-of­the-art technology, combined with innovative circuit design
techniques, provides a cost-effective solution for high-speed
memory needs.

The IDT71028 has an output enable pin which operates as
fast as 6ns, with address access times as fast as 12ns. All
bidirectional inputs and outputs of the IDT71028 are TTL­compatible and operation is from a single 5V supply. Fully
static asynchronous circuitry is used, requiring no clocks or
refresh for operation.

The IDT71028 is packaged in 28-pin 400 mil Plastic SOJ
package.

ADDRESS
DECODER

A17

I/O0 – I/O3

CS

WE

OE

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

CONTROL

4 4

LOGIC

1,048,576-BIT
MEMORY
ARRAY

I/O CONTROL

2966 drw 01

COMMERCIAL TEMPERATURE RANGE AUGUST 1996

1996 Integrated Device Technology, Inc. 9.4 DSC-2966/5

1

IDT71028
CMOS STATIC RAM 1 MEG (256K x 4-BIT) COMMERCIAL TEMPERATURE RANGE

PIN CONFIGURATION

A

0

1

A1

2

A2

3

A3

4

A4

5

A5

6
A6
A7
A8

A9

A10

CS
OE

GND

SO28-6

7

8

9

10 19

11 18

12

13

14

SOJ

TOP VIEW

TRUTH TABLE

(1,2)

CSCSOEOEWEWE I/O Function

L L H DATA
L X L DATA

OUT Read Data

IN Write Data

L H H High-Z Output Disabled

H X X High-Z Deselected - Standby (I

(3)

HC X X High-Z Deselected - Standby (ISB1)

V

NOTES: 2966 tbl 01

1. H = VIH, L = VIL, x = Don't care.

2. V

LC = 0.2V, VHC = VCC -0.2V.

3. Other inputs ≥V

HC or ≤VLC.

28
27
26
25
24
23
22
21
20

17
16
15

2966 drw 02

VCC
A17
A16
A15
A14

13

A

12

A

11

A
NC
I/O3
I/O2
I/O
I/O

WE

1
0

SB)

ABSOLUTE MAXIMUM RATINGS

(1)

Symbol Rating Com’l. Unit

(2)

V

TERM

Terminal Voltage with –0.5 to +7.0 V
Respect to GND

T

A Operating Temperature 0 to +70 °C

T

BIAS Temperature Under –55 to +125 °C

Bias

STG Storage Temperature –55 to +125 °C

T

P

T Power Dissipation 1.25 W

OUT DC Output Current 50 mA

I

NOTES: 2966 tbl 02

1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.

2. V

TERM must not exceed VCC + 0.5V.

CAPACITANCE

(TA = +25°C, f = 1.0MHz, SOJ package)

Symbol Parameter

IN Input Capacitance VIN = 3dV 8 pF

C

I/O I/O Capacitance VOUT = 3dV 8 pF

C

NOTE: 2966 tbl 03

1. This parameter is guaranteed by device characterization, but not prod-

uction tested.

(1)

Conditions Max. Unit

RECOMMENDED DC OPERATING
CONDITIONS

Symbol Parameter Min. Typ. Max. Unit

CC Supply Voltage 4.5 5.0 5.5 V

V
GND Supply Voltage 0 0 0 V

IH Input High Voltage 2.2 — VCC+0.5 V

V

IL Input Low Voltage –0.5

V

NOTE: 2966 tbl 04

1. VIL (min.) = –1.5V for pulse width less than 10ns, once per cycle.

(1)

— 0.8 V

DC ELECTRICAL CHARACTERISTICS

VCC = 5.0V ± 10%

IDT71028

Symbol Parameter Test Condition Min. Max. Unit

LI| Input Leakage Current VCC = Max., VIN = GND to VCC — 5 µA

|I

LO| Output Leakage Current VCC = Max.,

|I

OL Output Low Voltage IOL = 8mA, VCC = Min. — 0.4 V

V

OH Output High Voltage IOH = –4mA, VCC = Min. 2.4 — V

V

CS

= VIH, VOUT = GND to VCC — 5 µA

9.4 2

2966 tbl 05

IDT71028
CMOS STATIC RAM 1 MEG (256K x 4-BIT) COMMERCIAL TEMPERATURE RANGE

DC ELECTRICAL CHARACTERISTICS

(1)

(VCC = 5.0V ± 10%, VLC = 0.2V, VHC = VCC – 0.2V)

71028S12

Symbol Parameter Com'l. Mil. Com'l. Mil. Com'l. Mil. Com'l. Mil. Unit

CC Dynamic Operating Current, 155 — 150 — 145 — 145 — mA

I

CS

≤ V

IL, Outputs Open,

CC = Max., f = fMAX

V

(2)

ISB Standby Power Supply Current 35 — 35 — 35 — 35 — mA

(TTL Level), CS ≥ V
V

CC = Max., f = fMAX

IH, Outputs Open,

(2)

ISB1 Full Standby Power Supply Current 10 — 10 — 10 — 10 — mA

(CMOS Level), CS ≥ V
V

CC = Max., f = 0

NOTES: 2966 tbl 06

1. All values are maximum guaranteed values.

MAX = 1/tRC (all address inputs are cycling at fMAX); f = 0 means no address input lines are changing.

2. f

3. 12ns specification is preliminary.

HC, Outputs Open,

(2)

, VIN ≤ VLC or VIN ≥ VHC

(3)

71028S15 71028S17 71028S20

AC TEST CONDITIONS

Input Pulse Levels GND to 3.0V
Input Rise/Fall Times 3ns
Input Timing Reference Levels 1.5V
Output Reference Levels 1.5V
AC Test Load See Figures 1 and 2

2966 tbl 07

DATA

5V

OUT

30pF

Figure 1. AC Test Load

480

255

Ω

Ω

2966 drw 03

5V

480

Ω

OUT

DATA

255

5pF*

*Including jig and scope capacitance.

Figure 2. AC Test Load

(for t

CLZ, tOLZ, tCHZ, tOHZ, tOW, and tWHZ)

9.4 3

Ω

2966 drw 04

IDT71028
CMOS STATIC RAM 1 MEG (256K x 4-BIT) COMMERCIAL TEMPERATURE RANGE

AC ELECTRICAL CHARACTERISTICS (VCC = 5.0V ± 10%, Commercial Temperature Range)

71028S12

Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Unit
Read Cycle

tRC Read Cycle Time 12 — 15 — 17 — 20 — ns
tAA Address Access Time — 12 — 15 — 17 — 20 ns
tACS Chip Select Access Time — 12 — 15 — 17 — 20 ns

(2)

tCLZ
tCHZ

Chip Select to Output in Low-Z 3 — 3 — 3 — 3 — ns

(2)

Chip Deselect to Output in High-Z 0 6 0 7 0 8 0 8 ns

tOE Output Enable to Output Valid — 6 — 7 — 8 — 8 ns

(2)

tOLZ
tOHZ

Output Enable to Output in Low-Z 0 — 0 — 0 — 0 — ns

(2)

Output Disable to Output in High-Z 0 5 0 5 0 6 0 7 ns

tOH Output Hold from Address Change 4 — 4 — 4 — 4 — ns

(2)

tPU
tPD

Chip Select to Power Up Time 0 — 0 — 0 — 0 — ns

(2)

Chip Deselect to Power Down Time — 12 — 15 — 17 — 20 ns

Write Cycle

tWC Write Cycle Time 12 — 15 — 17 — 20 — ns
tAW Address Valid to End of Write 10 — 12 — 13 — 15 — ns
tCW Chip Select to End of Write 10 — 12 — 13 — 15 — ns
tAS Address Set-up Time 0 — 0 — 0 — 0 — ns
tWP Write Pulse Width 10 — 12 — 13 — 15 — ns
tWR Write Recovery Time 0 — 0 — 0 — 0 — ns
tDW Data Valid to End of Write 7 — 8 — 9 — 9 — ns
tDH Data Hold Time 0 — 0 — 0 — 0 — ns

(2)

tOW

WHZ

t

NOTES: 2966 tbl 08

1. 12ns specification is preliminary.

2. This parameter guaranteed with the AC load (Figure 2) by device characterization, but is not production tested.

Output Active from End of Write 3 — 3 — 3 — 4 — ns

(2)

Write Enable to Output in High-Z 0 5 0 5 0 7 0 8 ns

(1)

71028S15 71028S17 71028S20

9.4 4

IDT71028
CMOS STATIC RAM 1 MEG (256K x 4-BIT) COMMERCIAL TEMPERATURE RANGE

TIMING WAVEFORM OF READ CYCLE NO. 1

ADDRESS

t

AA

OE

(5)

tCLZ

tOLZ

(5)

tACS

DATA

VCC SUPPLY

CURRENT

CS

OUT

ICC
ISB

HIGH IMPEDANCE

tPU

(1)

(3)

tRC

tOE

tOHZ

(5)

tCHZ

DATAOUT VALID

tPD

(5)

2966 drw 05

TIMING WAVEFORM OF READ CYCLE NO. 2

(1,2,4)

tRC

ADDRESS

tAA

tOH tOH

DATAOUT

NOTES:

1.WE is HIGH for Read Cycle.

2. Device is continuously selected, CS is LOW.

3. Address must be valid prior to or coincident with the later of CS transition LOW; otherwise t

4.OE is LOW.

5. Transition is measured ±200mV from steady state.

DATAOUT VALIDPREVIOUS DATAOUT VALID

2966 drw 6

AA is the limiting parameter.

9.4 5

IDT71028
CMOS STATIC RAM 1 MEG (256K x 4-BIT) COMMERCIAL TEMPERATURE RANGE

TIMING WAVEFORM OF WRITE CYCLE NO.1 (

ADDRESS

t

AW

CS

t

AS

WE

(6)

t

WHZ

DATA

DATA

OUT

IN

(4)

TIMING WAVEFORM OF WRITE CYCLE NO.2 (

WEWE CONTROLLED TIMING)

WC

t

t

WP

(3)

t

t

WR

OW

HIGH IMPEDANCE

t

t

DW

DATA

IN

DH

VALID

CSCS CONTROLLED TIMING)

(6)

(1,2,3,5)

(1,2,5)

t

CHZ

(4)

(6)

2966 drw 07

tWC

ADDRESS

tAW

CS

tAS

tCW

tWR

WE

tDW

DATAIN

NOTES:

1.WE or CS must be HIGH during all address transitions.

2. A write occurs during the overlap of a LOW

3.OE is continuously HIGH. If during a WE controlled write cycle OE is LOW, t
off and data to be placed on the bus for the required t
minimum write pulse is as short as the specified t

4. During this period, I/O pins are in the output state, and input signals must not be applied.

5. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state.

6. Transition is measured ±200mV from steady state.

CS

and a LOW WE.

DW. If

WP.

OE

is HIGH during a WE controlled write cycle, this requirement does not apply and the

WP must be greater than or equal to tWHZ + tDW to allow the I/O drivers to turn

DATAIN VALID

tDH

2966 drw 08

9.4 6

IDT71028
CMOS STATIC RAM 1 MEG (256K x 4-BIT) COMMERCIAL TEMPERATURE RANGE

ORDERING INFORMATION

IDT

71028

Device

Type

S

PowerXXSpeedXXPackage

X

Process/

Temperature

Range

Blank Commercial (0°C to +70°C)

Y

400-mil Small Outline J-Bend (SO28-6)

12
15
17

Speed in nanoseconds

20

2966 drw 09

9.4 7